CN109933303B - Multi-user high-speed pseudo-random sequence generator circuit and working method thereof - Google Patents
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Abstract
The invention discloses a multi-user high-speed pseudo-random sequence generator circuit and a working method thereof. The circuit comprises a DDR and an FPGA; the DDR is used for storing respective random number sequences for a large number of users in a queue mode in advance, the FPGA is used for managing the random number queues in the DDR, and length values in the queues are read circularly for different users in sequence. The method comprises the following steps: aiming at each queue in the DDR, establishing a high-speed sub-queue in the FPGA, wherein the high-speed sub-queue is used for caching partial numerical values read from the DDR in a burst mode for a user circuit in the FPGA to read at a high speed; when the depth of the cache data in a certain sub-queue is lower than the threshold, the queue manager reads the length values of the set number from the queue corresponding to the DDR according to the storage position sequence read last time, and writes the length values into the corresponding sub-queue. The pseudo-random sequence provided by the invention has the advantages of large length, low hardware cost and strong real-time property, and can provide pseudo-random length sequences for a large number of users at the same time.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a multi-user high-speed pseudo-random sequence generator circuit and a working method thereof.
Background
The pseudo-random number generation circuit can be widely applied to various communication test equipment and encryption and decryption technologies. The current pseudo-random number generation technology is mature, and typically comprises a linear feedback shift register, a pseudo-random number generator based on a linear congruence algorithm and the like. When applied to communication test equipment such as a network protocol tester, it is generally necessary to simultaneously generate required random data packet length sequences for up to thousands of test service flows, and the length sequences are independent from each other and randomly distributed within a certain value range. If a large number of separate conventional pseudo-random sequence generation circuits are used at this time, hardware resource consumption is very large.
Disclosure of Invention
The invention aims to provide a multi-user high-speed pseudo-random sequence generator circuit with low hardware cost and strong real-time property and a working method thereof, which can provide pseudo-random length sequences for a large number of users at the same time, and the length of the pseudo-random sequences is large.
The technical solution for realizing the purpose of the invention is as follows: a multi-user high-speed pseudo-random sequence generator circuit comprises a DDR memory and an FPGA, wherein:
the DDR memory is used for storing respective random number sequences for users in a queue mode in advance; a user carries out test configuration through a configuration interface of a network tester, test software generates test data packet length sequences for different service flows and writes the test data packet length sequences into the DDR, each test service flow corresponds to a queue storing a data packet length value in the DDR, and the length of each queue is a period of distribution of the test sequence length value;
the FPGA is used for managing a random number queue in the DDR memory and circularly reading length values in the queue for different users in sequence; in the FPGA, aiming at each queue in the DDR, establishing a corresponding sub-queue, and storing corresponding queue data from the DDR; the FPGA is provided with a queue management circuit which is used for managing the establishment and reading of each queue in the DDR and managing the establishment and reading of each sub-queue in the FPGA; when the depth of the cache data in the sub-queues is reduced to a set threshold, the queue management circuit sequentially reads the length values of a set number from the queues corresponding to the DDR according to the storage positions read last time, and writes the length values into the corresponding sub-queues.
Furthermore, the queue management circuit in the FPGA comprises a DDR multi-user pseudo-random sequence management circuit and an on-chip multi-user pseudo-random sequence management circuit, the interior of the FPGA also comprises a multi-user local pseudo-random sequence buffer area maintained by the on-chip multi-user pseudo-random sequence management circuit, a head and tail pointer memory and a read-write pointer memory which are corresponding to the multi-queues in the DDR, and a head and tail pointer memory and a read-write pointer memory which are maintained by the DDR multi-user pseudo-random sequence management circuit and correspond to the multi-queues in the DDR;
after receiving the request of the port user frame generating circuit, the on-chip multi-user pseudo-random sequence management circuit reads out a random number according to the number of the user and the corresponding current internal queue read pointer and sends the random number to the user; when the number of random numbers locally buffered by a user is less than a given threshold, a request is sent to a DDR multi-user pseudo-random sequence management circuit, and the request is to read data from the DDR in a burst mode according to a sequence;
after receiving the request, the DDR multi-user pseudo-random sequence management circuit reads out corresponding queue information including a head pointer, a tail pointer and a current read pointer according to the number of the user, reads out a group of data from the DDR in a burst mode from the position of the current read pointer according to the read-out information, sends the data to the on-chip multi-user pseudo-random sequence management circuit, and sequentially writes the data into a local pseudo-random sequence buffer area according to a write pointer of a local queue of the user.
Furthermore, the FPGA also comprises user frame generating circuits which belong to different ports respectively, length information of data frames to be generated is read from the on-chip multi-user pseudo-random sequence management circuit to generate required test frames, and one user frame generating circuit can simulate a plurality of user service flows simultaneously.
Further, the test software generates test data packet length sequences for different service flows and writes the test data packet length sequences into the DDR as follows:
establishing a test data packet length sequence for each service flow in the DDR, wherein the specific length value distribution is obtained by test software according to user configuration, different service flows have mutually independent test packet length distribution, and the longer the queue length is, the longer the period of the test length sequence is;
and managing queues in the FPGA, namely establishing queues in the DDR according to the configuration of test software, wherein the number of the queues in the DDR is the same as the number of test service flows, and the length of each queue is related to the specific test configuration.
A working method of a multi-user high-speed pseudo-random sequence generator circuit comprises the following steps:
step 2, writing the head and tail addresses stored in each queue into a head and tail pointer storage area maintained by a DDR multi-user pseudo-random sequence management circuit in the FPGA, wherein the read pointer of each queue is the same as the head pointer at the beginning; the CPU distributes buffer areas in the FPGA to form a local random number queue of each user;
step 3, the CPU writes the head and tail pointer and the read-write pointer of each local random number queue into a head and tail pointer and read-write pointer storage area maintained by the on-chip multi-user pseudo random sequence management circuit; in the initial state, the read-write pointer of each queue is the same as the head pointer of the queue;
step 4, when the user circuit needs to generate a test frame, the user frame generating circuit sends a request to the on-chip multi-user pseudo-random sequence management circuit, and the on-chip multi-user pseudo-random sequence management circuit reads out a corresponding head pointer and a corresponding tail pointer and a corresponding read-write pointer according to the user number:
if the current read-write pointers are different, the on-chip multi-user pseudo-random sequence management circuit sends the random number in the storage space pointed by the current read pointer to the current user, then adds 1 to the read pointer, and ends the operation;
if the current read pointer is the same as the tail pointer, jumping to a head pointer; meanwhile, the on-chip multi-user pseudo random sequence management circuit checks the number of the current remaining random numbers: if the number of the data is lower than the request threshold, sending a read-in request to a DDR multi-user pseudo-random sequence management circuit, and then entering the step 5; otherwise, ending the operation;
step 5, after the DDR multi-user pseudo-random sequence management circuit receives the request, reading a head pointer, a tail pointer and a read pointer in a corresponding DDR queue according to the user number, sequentially reading a data block in a burst mode, then sending the request to the on-chip multi-user pseudo-random sequence management circuit, and writing the data into a local buffer area; and then the DDR multi-user pseudo-random sequence management circuit modifies the read pointer, and the operation is finished after the current queue state is stored.
Compared with the prior art, the invention has the following remarkable advantages: (1) the pseudo-random sequence is stored by using the off-chip DDR storage area, and the length of the pseudo-random sequence is large, so that the requirement on randomness can be met; (2) the double-queue circuit structure fully utilizes the characteristics of large capacity and long storable sequence period of the DDR memory, can adapt to the characteristic of DDR burst operation and overcome the problem of large DDR read operation delay; (3) the high-speed buffer area in the chip can be read and written quickly, has strong real-time performance, can meet the requirements of multiple users, and simultaneously provides a pseudo-random length sequence for a large number of users at high speed; (4) DDR is low in price, and hardware cost is reduced.
Drawings
FIG. 1 is a schematic diagram of an applied network structure of a multi-user high-speed pseudo-random sequence generator circuit according to the present invention.
Fig. 2 is a schematic structural diagram of a pseudo-random sequence required by a user in the embodiment of the present invention.
Fig. 3 is a schematic diagram of a queue structure according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a multi-user high-speed pseudo-random sequence generator circuit according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
The main implementation carrier of the multi-user high-speed pseudo-random sequence generator circuit is a programmable device such as an FPGA and a common peripheral device DDR memory matched with the FPGA. The circuit function described by the invention can be realized by using a hardware description language and adopting an FPGA design flow. In conjunction with fig. 1, the circuit of the present invention needs to be used with other test circuits. When the tester simulates a large number of service flows with different characteristics to test the network to be tested at the same time, the multi-user high-speed pseudo-random sequence generator circuit can generate the length sequences required by test data packets for different users in a full hardware mode at high speed in real time under the conditions of less consumption of FPGA hardware resources and more convenient use.
The invention discloses a multi-user high-speed pseudo-random sequence generator circuit, which comprises a DDR memory and an FPGA, wherein:
the DDR memory is used for storing respective random number sequences for users in a queue mode in advance; a user carries out test configuration through a configuration interface of a network tester, test software generates test data packet length sequences for different service flows and writes the test data packet length sequences into the DDR, each test service flow corresponds to a queue storing a data packet length value in the DDR, and the length of each queue is a period of distribution of the test sequence length value;
the FPGA is used for managing a random number queue in the DDR memory and circularly reading length values in the queue for different users in sequence; in the FPGA, aiming at each queue in the DDR, establishing a corresponding sub-queue, and storing corresponding queue data from the DDR; the FPGA is provided with a queue management circuit which is used for managing the establishment and reading of each queue in the DDR and managing the establishment and reading of each sub-queue in the FPGA; when the depth of the cache data in the sub-queues is reduced to a set threshold, the queue management circuit sequentially reads the length values of a set number from the queues corresponding to the DDR according to the storage positions read last time, and writes the length values into the corresponding sub-queues.
Furthermore, the queue management circuit in the FPGA comprises a DDR multi-user pseudo-random sequence management circuit and an on-chip multi-user pseudo-random sequence management circuit, the interior of the FPGA also comprises a multi-user local pseudo-random sequence buffer area maintained by the on-chip multi-user pseudo-random sequence management circuit, a head and tail pointer memory and a read-write pointer memory which are corresponding to the multi-queues in the DDR, and a head and tail pointer memory and a read-write pointer memory which are maintained by the DDR multi-user pseudo-random sequence management circuit and correspond to the multi-queues in the DDR;
after receiving the request of the port user frame generating circuit, the on-chip multi-user pseudo-random sequence management circuit reads out a random number according to the number of the user and the corresponding current internal queue read pointer and sends the random number to the user; when the number of random numbers locally buffered by a user is less than a given threshold, a request is sent to a DDR multi-user pseudo-random sequence management circuit, and the request is to read data from the DDR in a burst mode according to a sequence;
after receiving the request, the DDR multi-user pseudo-random sequence management circuit reads out corresponding queue information including a head pointer, a tail pointer and a current read pointer according to the number of the user, reads out a group of data from the DDR in a burst mode from the position of the current read pointer according to the read-out information, sends the data to the on-chip multi-user pseudo-random sequence management circuit, and sequentially writes the data into a local pseudo-random sequence buffer area according to a write pointer of a local queue of the user.
Furthermore, the FPGA also comprises user frame generating circuits which belong to different ports respectively, length information of data frames to be generated is read from the on-chip multi-user pseudo-random sequence management circuit to generate required test frames, and one user frame generating circuit can simulate a plurality of user service flows simultaneously.
Further, the test software generates test data packet length sequences for different service flows and writes the test data packet length sequences into the DDR as follows:
establishing a test data packet length sequence for each service flow in the DDR, wherein the specific length value distribution is obtained by test software according to user configuration, different service flows have mutually independent test packet length distribution, and the longer the queue length is, the longer the period of the test length sequence is;
and managing queues in the FPGA, namely establishing queues in the DDR according to the configuration of test software, wherein the number of the queues in the DDR is the same as the number of test service flows, and the length of each queue is related to the specific test configuration.
The invention relates to a working method of a multi-user high-speed pseudo-random sequence generator circuit, which comprises the following steps:
step 2, writing the head and tail addresses stored in each queue into a head and tail pointer storage area maintained by a DDR multi-user pseudo-random sequence management circuit in the FPGA, wherein the read pointer of each queue is the same as the head pointer at the beginning; the CPU distributes buffer areas in the FPGA to form a local random number queue of each user;
step 3, the CPU writes the head and tail pointer and the read-write pointer of each local random number queue into a head and tail pointer and read-write pointer storage area maintained by the on-chip multi-user pseudo random sequence management circuit; in the initial state, the read-write pointer of each queue is the same as the head pointer of the queue;
step 4, when the user circuit needs to generate a test frame, the user frame generating circuit sends a request to the on-chip multi-user pseudo-random sequence management circuit, and the on-chip multi-user pseudo-random sequence management circuit reads out a corresponding head pointer and a corresponding tail pointer and a corresponding read-write pointer according to the user number:
if the current read-write pointers are different, the on-chip multi-user pseudo-random sequence management circuit sends the random number in the storage space pointed by the current read pointer to the current user, then adds 1 to the read pointer, and ends the operation;
if the current read pointer is the same as the tail pointer, jumping to a head pointer; meanwhile, the on-chip multi-user pseudo random sequence management circuit checks the number of the current remaining random numbers: if the number of the data is lower than the request threshold, sending a read-in request to a DDR multi-user pseudo-random sequence management circuit, and then entering the step 5; otherwise, ending the operation;
step 5, after the DDR multi-user pseudo-random sequence management circuit receives the request, reading a head pointer, a tail pointer and a read pointer in a corresponding DDR queue according to the user number, sequentially reading a data block in a burst mode, then sending the request to the on-chip multi-user pseudo-random sequence management circuit, and writing the data into a local buffer area; and then the DDR multi-user pseudo-random sequence management circuit modifies the read pointer, and the operation is finished after the current queue state is stored.
As a specific example, first, a CPU inside a tester needs to generate required pseudo-random sequences according to different test traffic flows configured by a user. The generated pseudo-random sequence is then written into the storage area of the DDR3 with the depth of 128M, and in this way, a large number of pseudo-random sequences with different distribution characteristics can be generated and stored. Double queue management circuits are designed in the FPGA, and the names of the two queue management circuits are a DDR3 multi-user pseudo-random sequence management circuit and an on-chip multi-user pseudo-random sequence management circuit respectively. After receiving the request of the port user frame generating circuit, the on-chip multi-user pseudo-random sequence management circuit reads out a random number according to the number of the user and the current internal queue reading pointer of the user and delivers the random number to the user. When the number of random numbers locally buffered by one user is less than a given threshold, a request is sent to the DDR3 multi-user pseudo-random sequence management circuit to read in a part of data in a burst mode according to the sequence from the DDR 3. After receiving the request, the DDR3 multi-user pseudo-random sequence management circuit reads out the corresponding queue information including the head pointer, the tail pointer and the current read pointer according to the number of the user, and reads out a group of data from the DDR3 in a burst mode from the position of the current read pointer according to the information and delivers the data to the on-chip multi-user pseudo-random sequence management circuit, and the circuit writes the data in sequence according to the write pointer of the local queue of the user. The DDR3 operates in a burst mode, and is fast but has a certain operation delay, so that it cannot wait until the corresponding internal queue of the FPGA is empty to request to read data, and the read data is requested to be read in advance. The user local queue in the chip has high reading and writing speed, and can simultaneously meet the high-speed reading requirements of a plurality of users. A complete pseudo-random sequence is stored for each user in the DDR3, the length of the sequence is the period of the pseudo-random sequence, pseudo-random sequence segments which are read in sequentially are stored in the FPGA, and the double-queue structure can effectively combine the large storage capacity of the DDR3 with high-speed reading and writing in the chip, so that the requirement of multi-user random test is met.
Examples
With reference to fig. 1, the multi-user high-speed pseudo-random sequence generator circuit applied to the network tester of the invention is composed of a DDR3 memory and an FPGA for realizing the test function.
The DDR3 memory is used for storing respective random number sequences in a queue manner for a large number of users in advance, the users perform test configuration through a configuration interface of the tester, test data packet length sequences are generated for different service flows and written into the DDR3, each test service flow corresponds to one queue storing a data packet length value in the DDR3, and the length of each queue is a period of distribution of the test sequence length value; for a test port, establishing a corresponding queue according to the number of test service flows simulated by a tester;
the FPGA internally comprises a multi-user local pseudo-random sequence buffer area, a head-tail pointer memory, a read-write pointer memory, a head-tail pointer memory and a read pointer memory which correspond to a plurality of queues in the DDR3, and a user frame generating circuit which belongs to different ports; the multi-user local pseudo-random sequence buffer area and the corresponding head-tail pointer memory and read-write pointer memory are maintained by the on-chip multi-user pseudo-random sequence management circuit, the head-tail pointer memory and the read pointer memory corresponding to the multiple queues in the DDR3 are maintained and managed by the DDR3 multi-user pseudo-random sequence management circuit, the user frame generation circuit reads length information of data frames to be generated from the on-chip multi-user pseudo-random sequence management circuit to generate required test frames, and one user frame generation circuit can simulate a plurality of user service flows at the same time.
Specifically, the FPGA internally includes a multi-user local pseudo random sequence buffer maintained by an on-chip multi-user pseudo random sequence management circuit, and a head-to-tail pointer memory and a read-write pointer memory corresponding to the multi-user local pseudo random sequence buffer. The FPGA also comprises a head-tail pointer memory and a read pointer memory which correspond to a plurality of queues in the DDR3, and the head-tail pointer memory and the read pointer memory are maintained and managed by a DDR3 multi-user pseudo-random sequence management circuit. The FPGA also comprises user frame generating circuits belonging to different ports, the user frame generating circuits read length information of data frames to be generated from the on-chip multi-user pseudo-random sequence management circuit and generate required test frames, and one user frame generating circuit can simulate a plurality of user service flows at the same time.
During testing, a CPU inside the tester first needs to generate a required pseudo-random sequence according to different test traffic configured by a user, as shown in fig. 2. The generated pseudo-random sequences have different distribution characteristics and periodicity, and the randomness of the length of the test frame generated by one user depends on the length sequence generated by the CPU for the user; because the typical length of the Ethernet frame is 64-1518 bytes during actual test, the distribution range is small, the length of the test frame of different users is usually a subset of the Ethernet frame, and the distribution range is small, the sequence period required by meeting the randomness requirement does not need to be too long.
FIG. 3 shows the queue structure of the whole circuit, after the CPU generates a corresponding random length sequence for each user, it needs to allocate continuous storage space for each sequence in DDR3, and write the random sequence into DDR3 to form a storage queue; then, the CPU writes the head and tail addresses stored in each queue into a head and tail pointer storage area (SRAM) maintained by a DDR3 multi-user pseudo-random sequence management circuit in the FPGA, and initially, a read pointer of each queue is the same as a head pointer; then, the CPU distributes the buffer area in the FPGA to form a local random number queue of each user; the CPU writes the head and tail pointer and the read-write pointer of each local queue into a head and tail pointer and read-write pointer storage area (SRAM) maintained by the on-chip multi-user pseudo-random sequence management circuit, and in an initial state, the read-write pointer of each queue is the same as the head pointer of the queue. When the system is initialized, in order to avoid that a local queue inside the FPGA is empty, the CPU directly writes a part of data in the DDR3 into the corresponding internal queue and modifies a queue read pointer of the DDR3, so that the phenomenon that the work speed of the system is influenced because a local buffer is empty initially is avoided.
Fig. 4 is a block diagram of the circuit. When a user circuit needs to generate a test frame, a request is sent to an on-chip multi-user pseudo-random sequence management circuit, the on-chip multi-user pseudo-random sequence management circuit reads a head-tail pointer and a read-write pointer of the on-chip multi-user pseudo-random sequence management circuit according to a user number, if the current read-write pointer is different, an available pseudo-random number exists, at the moment, the on-chip multi-user pseudo-random sequence management circuit gives a random number in a storage space pointed by the current read pointer to a current user, then the read pointer is added with 1, if the current read pointer is the same as the tail pointer, the head pointer is jumped to, then the on-chip multi-user pseudo-random sequence management circuit checks the number of the current residual random number, if the number is lower than a request; after receiving the request, the DDR3 multi-user pseudo-random sequence management circuit reads a head pointer, a tail pointer and a read pointer in a corresponding DDR3 queue according to the user number, sequentially reads a data block in a burst mode, then sends a request to the on-chip multi-user pseudo-random sequence management circuit, and writes data into a local buffer area; and then the DDR3 multi-user pseudo-random sequence management circuit modifies the read pointer, saves the current queue state and then ends the operation.
In summary, the off-chip DDR3 realizes the expansion of the circuit memory space, and the FPGA can access the memory space in the DDR3 and can generate the required pseudo-random length value sequence at high speed for up to thousands of users in real time.
Claims (5)
1. A multi-user high-speed pseudo-random sequence generator circuit is characterized by comprising a DDR memory and an FPGA, wherein:
the DDR memory is used for storing respective random number sequences for users in a queue mode in advance; a user carries out test configuration through a configuration interface of a network tester, test software generates test data packet length sequences for different service flows and writes the test data packet length sequences into the DDR, each test service flow corresponds to a queue storing a data packet length value in the DDR, and the length of each queue is a period of distribution of the test sequence length values;
the FPGA is used for managing a random number queue in the DDR memory and circularly reading length values in the queue for different users in sequence; in the FPGA, aiming at each queue in the DDR, establishing a corresponding sub-queue, and storing corresponding queue data from the DDR; the FPGA is provided with a queue management circuit which is used for managing the establishment and reading of each queue in the DDR and managing the establishment and reading of each sub-queue in the FPGA; when the depth of the cache data in the sub-queues is reduced to a set threshold, the queue management circuit sequentially reads the length values of a set number from the queues corresponding to the DDR according to the storage positions read last time, and writes the length values into the corresponding sub-queues.
2. The multi-user high-speed pseudo-random sequence generator circuit according to claim 1, wherein the queue management circuit in the FPGA comprises a DDR multi-user pseudo-random sequence management circuit and an on-chip multi-user pseudo-random sequence management circuit, the FPGA further comprises a multi-user local pseudo-random sequence buffer area maintained by the on-chip multi-user pseudo-random sequence management circuit and a corresponding head and tail pointer memory and a read and write pointer memory, and the DDR multi-user pseudo-random sequence management circuit maintains a head and tail pointer memory and a read pointer memory corresponding to a plurality of queues in the DDR;
after receiving the request of the port user frame generating circuit, the on-chip multi-user pseudo-random sequence management circuit reads out a random number according to the number of the user and the corresponding current internal queue read pointer and sends the random number to the user; when the number of random numbers locally buffered by a user is less than a given threshold, a request is sent to a DDR multi-user pseudo-random sequence management circuit, and the request is to read data from the DDR in a burst mode according to a sequence;
after receiving the request, the DDR multi-user pseudo-random sequence management circuit reads out corresponding queue information including a head pointer, a tail pointer and a current read pointer according to the number of the user, reads out a group of data from the DDR in a burst mode from the position of the current read pointer according to the read-out information, sends the data to the on-chip multi-user pseudo-random sequence management circuit, and sequentially writes the data into a local pseudo-random sequence buffer area according to a write pointer of a local queue of the user.
3. The multi-user high-speed pseudo-random sequence generator circuit according to claim 2, wherein the FPGA further comprises user frame generating circuits respectively belonging to different ports, length information of data frames to be generated is read from the on-chip multi-user pseudo-random sequence management circuit to generate required test frames, and one user frame generating circuit can simultaneously simulate a plurality of user traffic streams.
4. The multi-user high-speed pseudorandom sequence generator circuit of claim 1, 2 or 3, wherein said test software generates test packet length sequences for different traffic streams and writes into the DDR as follows:
establishing a test data packet length sequence for each service flow in the DDR, wherein the specific length value distribution is obtained by test software according to user configuration, different service flows have mutually independent test packet length distribution, and the longer the queue length is, the longer the period of the test length sequence is;
and managing queues in the FPGA, namely establishing queues in the DDR according to the configuration of test software, wherein the number of the queues in the DDR is the same as the number of test service flows, and the length of each queue is related to the specific test configuration.
5. A working method of a multi-user high-speed pseudo-random sequence generator circuit is characterized by comprising the following steps:
step 1, after each user generates a corresponding random length sequence, distributing continuous storage space for each sequence in the DDR, and writing the random sequence into the DDR to form a storage queue;
step 2, writing the head and tail addresses stored in each queue into a head and tail pointer storage area maintained by a DDR multi-user pseudo-random sequence management circuit in the FPGA, wherein the read pointer of each queue is the same as the head pointer at the beginning; the CPU distributes buffer areas in the FPGA to form a local random number queue of each user;
step 3, the CPU writes the head and tail pointer and the read-write pointer of each local random number queue into a head and tail pointer and read-write pointer storage area maintained by the on-chip multi-user pseudo random sequence management circuit; in the initial state, the read-write pointer of each queue is the same as the head pointer of the queue;
step 4, when the user circuit needs to generate a test frame, the user frame generating circuit sends a request to the on-chip multi-user pseudo-random sequence management circuit, and the on-chip multi-user pseudo-random sequence management circuit reads out a corresponding head pointer and a corresponding tail pointer and a corresponding read-write pointer according to the user number:
if the current read-write pointers are different, the on-chip multi-user pseudo-random sequence management circuit sends the random number in the storage space pointed by the current read pointer to the current user, then adds 1 to the read pointer, and ends the operation;
if the current read pointer is the same as the tail pointer, jumping to a head pointer; meanwhile, the on-chip multi-user pseudo random sequence management circuit checks the number of the current remaining random numbers: if the number of the data is lower than the request threshold, sending a read-in request to a DDR multi-user pseudo-random sequence management circuit, and then entering the step 5; otherwise, ending the operation;
step 5, after the DDR multi-user pseudo-random sequence management circuit receives the request, reading a head pointer, a tail pointer and a read pointer in a corresponding DDR queue according to the user number, sequentially reading a data block in a burst mode, then sending the request to the on-chip multi-user pseudo-random sequence management circuit, and writing the data into a local buffer area; and then the DDR multi-user pseudo-random sequence management circuit modifies the read pointer, and the operation is finished after the current queue state is stored.
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