CN109922337A - AVS2 intra mode decision fast algorithm and realization device - Google Patents

AVS2 intra mode decision fast algorithm and realization device Download PDF

Info

Publication number
CN109922337A
CN109922337A CN201711325014.0A CN201711325014A CN109922337A CN 109922337 A CN109922337 A CN 109922337A CN 201711325014 A CN201711325014 A CN 201711325014A CN 109922337 A CN109922337 A CN 109922337A
Authority
CN
China
Prior art keywords
mode
avs2
fast algorithm
intra
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711325014.0A
Other languages
Chinese (zh)
Inventor
蔡斌斌
李源
彭聪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boya Cloud (beijing) Technology Co Ltd
Original Assignee
Boya Cloud (beijing) Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Boya Cloud (beijing) Technology Co Ltd filed Critical Boya Cloud (beijing) Technology Co Ltd
Priority to CN201711325014.0A priority Critical patent/CN109922337A/en
Publication of CN109922337A publication Critical patent/CN109922337A/en
Pending legal-status Critical Current

Links

Abstract

The present invention provides a kind of AVS2 intra mode decision fast algorithm and realization device.The fast algorithm generates prediction block as reference pixel interpolation when carrying out model selection, using the original pixels of video, and not referring again to the intra prediction mode of periphery block, to break data dependency, reduces mode selection module runing time.Intra mode decision fast algorithm proposed by the present invention can shorten the scramble time while guaranteeing coding quality.Meanwhile the fast algorithm is simply regular, hardware design is easily achieved.Frame mode in hardware circuit realization device is divided into 5 road circuit structures and does model selection parallel, finally selects 1 optimization model.

Description

AVS2 intra mode decision fast algorithm and realization device
Technical field
The present invention is one kind at AVS2 hardware coder intra mode decision (MD, Mode Decision), efficiently quickly The method for selecting intra prediction mode.
Background technique
AVS2 national standard is the standard of a new generation after AVS1, including three video, audio and system parts.AVS2 The target of Video coding is at least encoded than AVS1 under high definition or higher resolution while guaranteeing Subjective video quality Performance improves 1 times.
In MD, luma prediction encoding block can successively traverse all 33 kinds of modes, in total include 30 angle modes, DC mould Formula, Plane mode and Bilinear mode.Wherein, it is DC mode that MODE NUMBER, which is respectively as follows: 0,;1 is Plane mode;2 are Bilinear mode;3~32 be angle mode.The prediction direction figure of angle mode in AVS2 frame is shown with reference to Fig. 1, Fig. 1.? In 30 angle modes, 12 and 24 be vertical mode and horizontal pattern respectively.Colorimetric prediction can traverse 5 kinds of modes, respectively bright It spends exported schema (DM, Derived Mode), Bilinear mode, DC mode, horizontal pattern, vertical mode.
33 kinds of modes compare according to cost function calculation in MD, select several corresponding candidate moulds of smaller Cost Formula.Cost calculation formula is formula (1), and D represents the distortion of original pixels and prediction pixel;λ represents Lagrange's multiplier, according to QP size and the determination of frame type in configuration file obtain;R represents the number of coded bits of current coding mode needs.
Cost=D+ λ * R (1)
By (1) it is found that model selection is determined by the calculating selection of rate distortion costs value.But it is all different size of bright Coding unit (CU, Coding Unit) is top-down that 33 kinds of modes will be successively traversed from 64x64 to 8x8 for degree, then calculates and loses True D and code rate R, it is final relatively to select the corresponding mode of smaller Cost.Standard ensure that coding quality, but be the introduction of coding meter Complexity is calculated, this brings great challenge for the application and exploitation of encoder.
Firstly, there is strong data dependency between CU.Present encoding block CU is adjacent after selecting optimization model Next CU just can carry out model selection according to the periphery reconstructed pixel that optimization model decision obtains.Such dependence increases The scramble time of encoder, the flowing water design particularly with hardware coder are a challenges.Secondly, in MD decision numerous moulds Formula number brings a large amount of calculation amount, consumes additional scramble time and computing resource.
Summary of the invention
To sum up, 33 kinds of intra prediction modes are defined in AVS2 standard, when carrying out model selection, if 33 kinds of moulds of traversal Formula can obtain highest coding quality, but scramble time cost is too big.
The present invention provides a kind of AVS2 intra mode decision fast algorithm, which is characterized in that when carrying out model selection, adopts The original pixels of video are used to generate prediction block as reference pixel interpolation, and not referring again to the intra prediction mode of periphery block, To break data dependency, reduce mode selection module runing time.
Preferably, using absolute residuals and progress model selection.
Preferably, using the angle mode for being divided into 2 between MODE NUMBER and 3 non-angled mode operation mode selections, angle mould The collection of formula is combined into { 4,6,8,10,12,14,16,18,20,22,24,26,28,30,32 }, and 3 non-angled modes are respectively DC mould Formula, Plane mode and Bilinear mode.
Preferably, coloration does not do model selection, directlys adopt the optimal prediction modes that corresponding brightness block is selected.
The present invention also provides a kind of AVS2 intra mode decision fast algorithm implementation devices, for realizing according to the present invention AVS2 intra mode decision fast algorithm, which is characterized in that the realization device be 5 road hardware circuit realization devices.
Preferably, which is divided into 6 parts:
Part 1 is original pixels storage array, stores the original pixels of encoding block;
Part 2 is that reference pixel obtains circuit, which obtains the week that the prediction of present encoding block needs to use from part 1 Side reference pixel;
Part 3 is model prediction circuit;
Part 4 is absolute residuals and counting circuit, is used to obtain the distortion of original pixels and prediction pixel;
Part 5 is divided into 2 angle mode between MODE NUMBER and the Cost of 3 non-angled modes, 18 kinds of modes in total compares Circuit selects a kind of optimization model by the circuit;
Part 6 is optimization model storage circuit, is used to store the optimization model that selection obtains.
Preferably, the mode of 5 road hardware circuits coding is DC mode, Plane mode, Bilinear mode, mode 4 respectively ~10 and mode 26~32, mode 12~24.
The frame mode fast selection algorithm that this patent proposes, while guaranteeing coding quality, when can shorten coding Between.Meanwhile the fast algorithm is simply regular, hardware design is easily achieved.Frame mode in hardware circuit realization device is divided into 5 Road circuit structure does mode pre-selection, finally selects 1 optimization model.
Detailed description of the invention
Fig. 1 is the prediction direction figure of angle mode in AVS2 frame;
Fig. 2 is 5 road hardware circuit realization device of MD according to the present invention.
Specific embodiment
Illustrate the principle of the present invention and illustrative embodiments with reference to the accompanying drawings.
As described above, AVS2 canonical algorithm needs decision all 33 kinds of angle modes, and the data dependency between CU So that hardware design becomes a big bottleneck.In order to reduce the computation complexity of mode decision, the invention proposes one kind based on hard The high-speed decision algorithm and optimization circuit framework of part:
1. eliminating data dependency between CU
Just as previously outlined, the data dependency between CU causes hardware flowing water to be designed to a big bottleneck.Adjacent Next CU goes out optimization model in current CU decision, after obtaining the optimal reconstructed pixel in periphery, could start the operation mode in MD and select It selects.
In order to eliminate the strong data dependency between CU, the waiting time of ancillary cost in MD is reduced, hardware module is facilitated Grade flowing water design when CU carries out model selection in MD module, is generated using the original pixels of video as reference pixel interpolation Prediction block, and not referring again to the intra prediction mode of periphery block, to break data dependency, reduce model selection mould Block runing time.
2. carrying out model selection using absolute residuals and (SAD, Sum of Absolute Difference)
In order to save the calculation amount in MD, pixel distortion is assessed using the sad value of residual error, such method shortens place Manage the time.
3. using angle mode in 2 frame is divided between MODE NUMBER
In AVS2 frame mode, there is very strong spatial coherence between neighboring modes.So we adopt in MD With the angle mode for being divided into 2 between MODE NUMBER and 3 non-angled mode operation mode selections.The collection of angle mode be combined into 4,6,8, 10,12,14,16,18,20,22,24,26,28,30,32 }.3 non-angled modes are respectively DC mode, Plane mode and Bilinear mode.Such processing mode reduces the prediction mode of half, so that design is more simple regular.
4. brightness decision-making mode determines chroma mode
15 kinds of angle modes corresponding to luminance block and 3 kinds of non-angled modes in MD, 18 kinds of modes elect in total.And color Degree mode does not do model selection, directlys adopt the optimal prediction modes that corresponding brightness block is selected.Such design further saves The circuit layout area and computation complexity of MD module are saved.
5 road hardware circuit realization device of 5.MD
MD directly does model selection in 18 kinds of prediction modes.In 15 kinds of angle modes, set of modes { 4,6,8,10 } The offset pixels of X-axis can only be referred to;Set of modes { 26,28,30,32 } can only refer to the offset pixels of Y-axis;And set of modes { 12,14,16,18,20,22,24 } can refer to the offset pixels of X-axis and Y-axis.It has furthermore been found that in set { 4,6,8,10 } and Gather in { 26,28,30,32 }, mode 4 and mode 32, mode 6 and mode 30, mode 8 and mode 28, mode 10 and mode 26, It is consistent respectively in the deviation post and weight coefficient of X-axis and Y-axis, is as shown in table 1 single coordinate axle offset (weight) phase Mode corresponding relationship simultaneously;In set { 12,14,16,18,20,22,24 }, mode 12 and 24, mode 14 and mode 22, mould Formula 16 and mode 20 respectively for the deviation post of X-axis and Y-axis (or Y-axis and X-axis) be also it is corresponding consistent, as shown in table 2 Mode corresponding relationship when identical for double coordinate axle offsets (weight).
Mode corresponding relationship when the single coordinate axle offset (weight) of table 1 is identical
Mode corresponding relationship when 2 pairs of coordinate axle offsets (weight) of table are identical
After above-mentioned analysis, we can be realized the identical two mode common circuit kits design of deviation post.Cause This, we have proposed 5 road hardware circuit realization devices.5 road hardware circuit realization device of MD is shown with reference to Fig. 2, Fig. 2.
The device is divided into 6 parts: 1 is original pixels storage array, the circuit storage the original pixels of encoding block;2 Circuit is obtained for reference pixel, which obtains the periphery reference pixel that the prediction of present encoding block needs to use from 1;3 be mould The mode of formula prediction circuit, 5 road hardware circuits coding is DC mode, Plane mode, Bilinear mode, mode 4~10 respectively With mode 26~32, mode 12~24;4 be SAD counting circuit, obtains the distortion of original pixels and prediction pixel;5 be 18 kinds of moulds The Cost comparison circuit of formula selects 1 optimization model by the circuit;6 be candidate pattern storage circuit, for storing selection Obtained optimization model.
Such hardware circuit device makes design area reduce 1 times, reduces the waste of circuit area, and the 4th Road and the 5th road circuit model number to be treated are suitable, and the delay of circuit will not be brought to wait, can meet encoder well The demand of real-time saves the scramble time.
Algorithm part, the present invention are specifically simplified the design of MD using following 4 technological means, quickly select intra prediction mould Formula:
1. replacing reconstructed pixel with original pixels, the data dependency between CU is eliminated;
2. assessing pixel distortion with SAD, reduce computation complexity;
3. being selected using the angle mode for being divided into 2 between uniform MODE NUMBER, pattern count reduces 1/2, reduces circuit Design area, save hardware resource;
The selection of optimal luminance patterns 4. chroma mode places one's entire reliance upon reduces calculation amount and saves hardware circuit money Source.
Hardware components, the optimization based on software to MD module, the present invention proposes 5 road hardware circuit realization devices, wherein locating The pattern count for managing the 2 road circuits entrance of angle mode is suitable, will not generate delay and wait;And it is shared to the identical mode of offset Same set of hardware circuit, design are simple regular.
Above with reference to Detailed description of the invention the preferred embodiment of the present invention, it is understood, however, that above description is only example Property.Those skilled in the art can make the present invention various under the premise without departing from the spirit and scope of the present invention Modifications and variations.Protection scope of the present invention is limited by the accompanying claims.

Claims (7)

1. a kind of AVS2 intra mode decision fast algorithm, which is characterized in that when carrying out model selection, using the original of video Pixel generates prediction block as reference pixel interpolation, and not referring again to the intra prediction mode of periphery block, to break number According to dependence, reduce mode selection module runing time.
2. AVS2 intra mode decision fast algorithm according to claim 1, which is characterized in that using absolute residuals and into Row model selection.
3. AVS2 intra mode decision fast algorithm according to claim 1, which is characterized in that use MODE NUMBER interval For 2 angle mode and the selection of 3 non-angled mode operation modes, the collection of angle mode be combined into 4,6,8,10,12,14,16,18, 20,22,24,26,28,30,32 }, 3 non-angled modes are respectively DC mode, Plane mode and Bilinear mode.
4. AVS2 intra mode decision fast algorithm according to claim 1, which is characterized in that coloration does not do mode choosing It selects, directlys adopt the optimal prediction modes that corresponding brightness block is selected.
5. a kind of AVS2 intra mode decision fast algorithm implementation device, for realizing described in any one of claims 1 to 4 AVS2 intra mode decision fast algorithm, which is characterized in that the realization device be 5 road hardware circuit realization devices.
6. realization device according to claim 5, which is characterized in that the realization device is divided into 6 parts:
Part 1 is original pixels storage array, stores the original pixels of encoding block;
Part 2 is that reference pixel obtains circuit, which obtains the periphery ginseng that the prediction of present encoding block needs to use from part 1 Examine pixel;
Part 3 is model prediction circuit;
Part 4 is absolute residuals and counting circuit, is used to obtain the distortion of original pixels and prediction pixel;
Part 5 be divided between MODE NUMBER 2 angle mode and 3 non-angled modes, 18 kinds of modes in total Cost it is more electric 1 kind of optimization model is selected by the circuit in road;
Part 6 is optimization model storage circuit, is used to store the optimization model that selection obtains.
7. realization device according to claim 5, which is characterized in that the mode of 5 road hardware circuits coding is DC mould respectively Formula, Plane mode, Bilinear mode, mode 4~10 and mode 26~32, mode 12~24.
CN201711325014.0A 2017-12-13 2017-12-13 AVS2 intra mode decision fast algorithm and realization device Pending CN109922337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711325014.0A CN109922337A (en) 2017-12-13 2017-12-13 AVS2 intra mode decision fast algorithm and realization device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711325014.0A CN109922337A (en) 2017-12-13 2017-12-13 AVS2 intra mode decision fast algorithm and realization device

Publications (1)

Publication Number Publication Date
CN109922337A true CN109922337A (en) 2019-06-21

Family

ID=66958268

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711325014.0A Pending CN109922337A (en) 2017-12-13 2017-12-13 AVS2 intra mode decision fast algorithm and realization device

Country Status (1)

Country Link
CN (1) CN109922337A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112804524A (en) * 2019-11-13 2021-05-14 北京大学 Intra-frame fast mode decision method for AVS2

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103428501A (en) * 2013-09-08 2013-12-04 张新安 AVS intra-frame prediction mode fast selection algorithm
CN106162176A (en) * 2016-10-09 2016-11-23 北京数码视讯科技股份有限公司 Method for choosing frame inner forecast mode and device
CN106162175A (en) * 2015-03-26 2016-11-23 北京君正集成电路股份有限公司 Method for choosing frame inner forecast mode and device
US20170230673A1 (en) * 2016-02-05 2017-08-10 Blackberry Limited Rolling intra prediction for image and video coding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103428501A (en) * 2013-09-08 2013-12-04 张新安 AVS intra-frame prediction mode fast selection algorithm
CN106162175A (en) * 2015-03-26 2016-11-23 北京君正集成电路股份有限公司 Method for choosing frame inner forecast mode and device
US20170230673A1 (en) * 2016-02-05 2017-08-10 Blackberry Limited Rolling intra prediction for image and video coding
CN106162176A (en) * 2016-10-09 2016-11-23 北京数码视讯科技股份有限公司 Method for choosing frame inner forecast mode and device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
魏荣国 等: "一种快速AVS2帧内预测算法", 《科技创新与应用》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112804524A (en) * 2019-11-13 2021-05-14 北京大学 Intra-frame fast mode decision method for AVS2
CN112804524B (en) * 2019-11-13 2022-11-25 北京大学 Intra-frame fast mode decision method for AVS2

Similar Documents

Publication Publication Date Title
CN107071416B (en) HEVC intra-frame prediction mode rapid selection method
CN104935943B (en) The method being decoded to intra prediction mode
CN103248895B (en) A kind of quick mode method of estimation for HEVC intraframe coding
CN105763875B (en) Picture decoding apparatus and its method and picture coding device and its method
CN103546749B (en) Method for optimizing HEVC (high efficiency video coding) residual coding by using residual coefficient distribution features and bayes theorem
CN106688232A (en) Perceptual optimization for model-based video encoding
CN103260018B (en) Intra-frame image prediction decoding method and Video Codec
CN105208387B (en) A kind of HEVC Adaptive Mode Selection Method for Intra-Prediction
CN103517069A (en) HEVC intra-frame prediction quick mode selection method based on texture analysis
CN104853192B (en) Predicting mode selecting method and device
CN106878717A (en) The method and apparatus for deriving intra prediction mode
CN106060547A (en) Apparatus for decoding high-resolution images
CN105898332B (en) For the fast deep figure frame mode decision method of 3D-HEVC coding standards
CN103596004A (en) Intra-frame prediction method and device based on mathematical statistics and classification training in HEVC
CN107318016A (en) A kind of HEVC inter-frame forecast mode method for rapidly judging based on zero piece of distribution
CN107623857A (en) Video coding/decoding method, equipment and generation and the method for stored bits stream
CN106028047A (en) Hadamard transform-based fast intra-prediction mode selection and PU partition method
CN109819250A (en) A kind of transform method and system of the full combination of multicore
CN104954787B (en) HEVC inter-frame forecast mode selection methods and device
CN101754022A (en) Motion estimation method with low complexity
Chen et al. Rough mode cost–based fast intra coding for high-efficiency video coding
CN103702131B (en) Pattern-preprocessing-based intraframe coding optimization method and system
CN104811730A (en) Video image intra-frame encoding unit texture analysis and encoding unit selection method
CN106534855A (en) Lagrange factor calculation method for SATD
CN109922337A (en) AVS2 intra mode decision fast algorithm and realization device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190621