CN109920823B

CN109920823B - Pixel unit, manufacturing method thereof and display substrate

Info

Publication number: CN109920823B
Application number: CN201910172155.6A
Authority: CN
Inventors: 刘军; 闫梁臣; 周斌; 苏同上; 刘宁; 宋威; 刘融; 冯波
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2019-03-07
Filing date: 2019-03-07
Publication date: 2020-12-11
Anticipated expiration: 2039-03-07
Also published as: CN109920823A; WO2020177666A1

Abstract

A pixel unit, a manufacturing method thereof and a display substrate are provided. The pixel unit includes a dielectric layer, a switching element, and a first light shielding structure. The switching element comprises an active layer and is positioned on the dielectric layer, the first light shielding structure is at least partially positioned on the same layer as the dielectric layer, and the orthographic projection of the first light shielding structure on the surface of the active layer is positioned outside the orthographic projection of the active layer on the surface of the active layer. The first light shielding structure is arranged around the active layer and can shield light which is emitted to the side surface of the active layer along the dielectric layer, so that the increase of leakage current caused by photo-generated carriers generated by irradiating the active layer with light is reduced, and the stability of the switching element is improved.

Description

Pixel unit, manufacturing method thereof and display substrate

Technical Field

At least one embodiment of the disclosure relates to a pixel unit, a manufacturing method thereof and a display substrate.

Background

In general, a thin film transistor is used as a driving element of a display panel. An active layer in the thin film transistor generates photo-generated carriers after being irradiated by light, so that leakage current of the thin film transistor is increased, the quality of a display picture of the display panel is affected, and phenomena such as crosstalk, residual image and the like can be generated.

Disclosure of Invention

At least one embodiment of the present disclosure provides a pixel unit including a dielectric layer, a switching element, and a first light shielding structure. The switching element comprises an active layer and is positioned on the dielectric layer, the first light shielding structure is at least partially positioned on the same layer as the dielectric layer, and the orthographic projection of the first light shielding structure on the surface of the active layer is positioned outside the orthographic projection of the active layer on the surface of the active layer.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, the dielectric layer is disposed on at least two opposite sides of a portion of the first light shielding structure that is on the same layer as the dielectric layer.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, at least a portion of a sidewall of the dielectric layer, which is on a same layer as the first light shielding structure and faces the first light shielding structure, is formed as a protrusion and depression structure.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, the dielectric layer is provided with an opening or a groove surrounding the switching element on a plane parallel to the dielectric layer, and a sidewall of the opening or the groove is formed as the projection and depression structure.

For example, in a pixel unit provided by at least one embodiment of the present disclosure, the dielectric layer is a stacked layer composed of at least two sub-dielectric layers.

For example, in a pixel unit provided by at least one embodiment of the present disclosure, the openings in the adjacent sub-dielectric layers are communicated or the opening of one of the adjacent sub-dielectric layers is communicated with the trench of the other sub-dielectric layer, and an orthogonal projection of the opening in the adjacent sub-dielectric layer or the opening of one of the adjacent sub-dielectric layers and the trench of the other sub-dielectric layer on the surface where the active layer is located is at least partially non-overlapping.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer is located between the second sub-dielectric layer and the active layer, a first opening is provided in the first sub-dielectric layer, a second opening or a second groove is provided in the second sub-dielectric layer, the first opening is communicated with the second opening or the second groove, and an orthogonal projection of the first opening on a surface where the active layer is located within an orthogonal projection of the second opening or the second groove on the surface where the active layer is located.

For example, in a pixel unit provided by at least one embodiment of the present disclosure, the dielectric layer includes at least three sub-dielectric layers, and projections of orthogonal projections of the openings or slots of the sub-dielectric layers located at two sides on the surface where the active layer is located are located within an orthogonal projection of an opening of the sub-dielectric layer located in the middle on the surface where the active layer is located.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, the first light shielding structure includes a first portion and a second portion, the first portion is located on the same layer as the dielectric layer, and the second portion is located on a different layer from the dielectric layer.

For example, in a pixel unit provided by at least one embodiment of the present disclosure, a distance from an end of the second portion facing away from the dielectric layer to a surface of the dielectric layer is greater than or equal to a distance from a surface of the active layer facing away from the dielectric layer to the surface of the dielectric layer.

For example, the pixel unit provided in at least one embodiment of the present disclosure further includes a black matrix, the pixel unit includes a display area and a non-display area located around the display area, the black matrix and the first light shielding structure are located in the non-display area, and the black matrix and the second portion are in the same layer and are in an integrated structure.

For example, the pixel unit provided by at least one embodiment of the present disclosure further includes a second light shielding structure, where the second light shielding structure is located on a side of the dielectric layer facing away from the active layer, and an orthogonal projection of the active layer on a surface where the active layer is located coincides with an orthogonal projection of the second light shielding structure on a surface where the active layer is located, or an orthogonal projection of the active layer on a surface where the active layer is located within an orthogonal projection of the second light shielding structure on a surface where the active layer is located.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, an orthogonal projection of the second light shielding structure on the surface of the active layer is located inside an orthogonal projection of the first light shielding structure on the surface of the active layer.

For example, a pixel unit provided in at least one embodiment of the present disclosure further includes a light emitting device located on a side of the switching element facing away from the dielectric layer, the light emitting device includes a first electrode layer, a light emitting functional layer, and a second electrode layer stacked in this order on the switching element, and one of the first electrode layer and the second electrode layer is a reflective electrode layer.

At least one embodiment of the present disclosure provides a display substrate including the pixel unit described in any one of the above embodiments.

At least one embodiment of the present disclosure provides a method for manufacturing a pixel unit, including: forming a dielectric layer; forming a switching element including an active layer on the dielectric layer; forming a first shading structure at least partially on the same layer as the dielectric layer; wherein, the orthographic projection of the first light shielding structure on the surface of the active layer is positioned outside the orthographic projection of the active layer on the surface of the active layer.

For example, in a method for manufacturing a pixel unit provided in at least one embodiment of the present disclosure, forming the dielectric layer includes: the dielectric layer is patterned to form sidewalls at least partially of the relief structure in the dielectric layer.

For example, in a method of manufacturing a pixel unit provided in at least one embodiment of the present disclosure, patterning the dielectric layer to form an opening or a groove in the dielectric layer, a sidewall of the opening or the groove being formed as the projection and depression structure, the forming of the first light shielding structure includes: depositing a light shielding material layer on the dielectric layer to fill the opening or the groove, and patterning the light shielding material layer to form the first light shielding structure; wherein the dielectric layer surrounds the switching element.

For example, in a method for manufacturing a pixel unit provided in at least one embodiment of the present disclosure, the dielectric layer is formed as a stacked layer composed of at least two sub-dielectric layers.

For example, in a method for manufacturing a pixel unit provided by at least one embodiment of the present disclosure, the dielectric layer is a stacked layer composed of at least two sub-dielectric layers, and forming the dielectric layer includes: forming a second sub-dielectric layer and forming a first sub-dielectric layer on the second sub-dielectric layer; patterning the first sub-dielectric layer and the second sub-dielectric layer to form a first opening in the first sub-dielectric layer; after the first opening is formed in the first sub-dielectric layer, the second sub-dielectric layer is etched by using atmosphere by taking the first sub-dielectric layer as a mask so as to form a second opening or a second groove in the second sub-dielectric layer; wherein the materials forming the first sub-dielectric layer and the second sub-dielectric layer are different, and the etching ratio of the atmosphere to the material of the second sub-dielectric layer is greater than that to the material of the first sub-dielectric layer.

In the pixel unit, the manufacturing method thereof and the display substrate provided by at least one embodiment of the present disclosure, the first light shielding structure is located around the active layer and at least partially in the same layer as the dielectric layer, so that at least for light rays which are emitted to the active layer from the side surface of the active layer along the dielectric layer, the first light shielding structure can shield at least part of the light rays, thereby reducing increase of leakage current caused by photo-generated carriers generated by light irradiation on the active layer, and improving stability of the switching element.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description only relate to some embodiments of the present invention and are not limiting on the present invention.

Fig. 1 is a cross-sectional view of a partial structure of a pixel unit according to some embodiments of the present disclosure;

fig. 2A is a cross-sectional view of a portion of another pixel cell according to some embodiments of the present disclosure;

FIG. 2B is a plan view of one configuration of the pixel cell shown in FIG. 2A;

FIG. 2C is a plan view of another structure of the pixel cell shown in FIG. 2A;

fig. 3 is a cross-sectional view of a portion of another pixel cell according to some embodiments of the present disclosure;

fig. 4 is a cross-sectional view of a partial structure of another pixel unit according to some embodiments of the present disclosure;

fig. 5 is a cross-sectional view of a portion of another pixel cell provided in some embodiments of the present disclosure;

fig. 6 is a cross-sectional view of a partial structure of another pixel unit according to some embodiments of the present disclosure;

fig. 7 is a cross-sectional view of another pixel cell provided by some embodiments of the present disclosure;

fig. 8A is a cross-sectional view of another pixel cell provided by some embodiments of the present disclosure;

FIG. 8B is a plan view of the pixel cell shown in FIG. 8A;

fig. 9 is a plan view of a display substrate according to some embodiments of the present disclosure; and

fig. 10A to 10F are process diagrams of a method for manufacturing a pixel unit according to some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The large-sized Organic Light-Emitting Diode (OLED) display panel has the advantages of high contrast, self-luminescence, and the like, thereby having a good development prospect. A switching element such as a Thin Film Transistor (TFT) or the like needs to be provided in the OLED display panel to implement a control circuit, thereby controlling functions such as light emission of the OLED display panel. In the direction from the display side to the non-display side of the OLED display panel, a light blocking structure may be disposed above and/or below the TFT to prevent light from irradiating an active layer in the thin film transistor in the direction, but signal lines and the like in the OLED display panel are very densely arranged, light may be reflected by the signal lines and the like in the display panel and then may be emitted to a side surface of the active layer, and the light blocking structure disposed above and/or below the TFT cannot block the light, which may cause leakage current in the active layer due to photo-generated carriers, and unstable performance of the thin film transistor, which may cause poor display of the OLED display panel.

At least one embodiment of the present disclosure provides a pixel unit, a manufacturing method thereof and a display substrate. The pixel unit includes a dielectric layer, a switching element, and a first light shielding structure. The switching element comprises an active layer and is positioned on the dielectric layer, the first light shielding structure is at least partially in the same layer with the dielectric layer, and the orthographic projection of the first light shielding structure on the surface of the active layer is positioned outside the orthographic projection of the active layer on the surface of the active layer. The first light shielding structure is located around the active layer and at least partially has the same layer with the dielectric layer, so that at least for light rays which are emitted to the active layer from the side surface of the active layer along the dielectric layer, the first light shielding structure can shield at least part of the light rays, thereby reducing the increase of leakage current caused by photo-generated carriers generated by irradiating the active layer with light and improving the stability of the switching element.

A pixel unit, a manufacturing method thereof, and a display substrate according to at least one embodiment of the present disclosure are described below with reference to the accompanying drawings.

Fig. 1 is a cross-sectional view of a partial structure of a pixel unit according to some embodiments of the present disclosure, which illustrates a partial structure of a region where a switching element of the pixel unit is located.

For example, in at least one embodiment of the present disclosure, as shown in fig. 1, a pixel unit includes a dielectric layer 100, a switching element (not shown, which may refer to the switching element 200 in fig. 2A), and a first light shielding structure 300. The switching element comprises an active layer 210 and is located on the dielectric layer 100, at least part of the first light shielding structure 300 is in the same layer as the dielectric layer 100, and an orthographic projection of the first light shielding structure 300 on the surface of the active layer 210 is located outside an orthographic projection of the active layer 210 on the surface of the active layer 210. For example, as shown in fig. 1, a portion of the first light shielding structure 300 is in the same layer as the dielectric layer 100, and another portion protrudes out of the dielectric layer 100, thereby shielding light (dashed line "→" in fig. 1) from being emitted from the side surface of the pixel unit to the active layer 210. For example, the portion of the first light shielding structure 300 on the same layer as the dielectric layer 100 may shield the light ray S1 directed to the side surface of the active layer 210 along the dielectric layer 100, and the portion of the first light shielding structure 300 protruding out of the dielectric layer 100 may shield the light ray S2 directed to the side surface of the active layer 210 from the outside of the dielectric layer 100.

For example, the material of the active layer may include amorphous silicon, polycrystalline silicon, or metal oxides such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Gallium Zinc Oxide (GZO), and the like.

In at least one embodiment of the present disclosure, the type and material of the dielectric layer may be set according to the type of the switching element, and the type of the switching element may be selected as needed. For example, the switching element may be a thin film transistor, and the thin film transistor may be a top gate type thin film transistor, a bottom gate type thin film transistor, a double gate type thin film transistor, or the like.

For example, in some embodiments of the present disclosure, the switching element in the pixel unit is a top gate type thin film transistor. Illustratively, as shown in fig. 2A, the switching element 200 in the pixel unit includes an active layer 210, a gate electrode 220, and source and drain electrode layers (including a drain electrode 231 and a source electrode 232), the active layer 210 is located between the gate electrode 220 and the dielectric layer 100, and a gate insulating layer 240 is disposed between the active layer 210 and the gate electrode 220. For example, the switching element 200 includes an interlayer dielectric layer 250 covering the gate electrode 220, the drain electrode 231 and the source electrode 232 are located on a surface of the interlayer dielectric layer 250 facing away from the gate electrode 220, and vias are provided in the interlayer dielectric layer 250, with which the drain electrode 231 and the source electrode 232 are connected to both ends of the source layer 210, respectively. For example, the pixel unit includes a substrate base plate 10 to support the respective structures of the pixel unit.

For example, in the case where the switching element in the pixel unit is a top gate type thin film transistor, the dielectric layer 100 may be a buffer layer. The buffer layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like, has high density, and prevents ions in the base substrate 10 from penetrating into the active layer 210.

For example, in other embodiments of the present disclosure, the switching element in the pixel unit is a top gate thin film transistor. For example, the switching element in the pixel unit includes an active layer, a gate electrode, and source and drain electrode layers, and a dielectric layer is located between the gate electrode and the active layer. For example, the switching element includes an interlayer dielectric layer covering the active layer, the source and drain electrode layers are located on a surface of the interlayer dielectric layer away from the active layer, and a via hole is provided in the interlayer dielectric layer, and a drain electrode and a source electrode of the source and drain electrode layers are connected to both ends of the active layer respectively by using the via hole. In this case, the dielectric layer may be a gate insulating layer to separate the active layer and the gate electrode. The material of the gate insulating layer may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or other suitable materials.

Next, a description will be given of a technical solution of at least one embodiment of the present disclosure, which will be described below, by taking a switching element as a top gate thin film transistor as an example.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, the dielectric layer is disposed on at least two opposite sides of the portion of the first light shielding structure that is on the same layer as the dielectric layer.

For example, the dielectric layer may be provided on a side of the light shielding structure facing the active layer and a side facing away from the active layer in a direction parallel to the substrate base plane (or the active layer plane).

Illustratively, as shown in fig. 2A, at least two sides of the portion of the first light shielding structure 300 that is in the same layer as the dielectric layer 100 have the dielectric layer 100 along the X-axis direction. As such, the portion of the first light shielding structure 300 on the same layer as the dielectric layer 100 is interposed in the dielectric layer 100. For example, in at least one embodiment of the present disclosure, as shown in fig. 2A, a sidewall of a portion of the first light shielding structure 300 that is on the same layer as the dielectric layer 100 is in contact with a sidewall of the dielectric layer 100 that faces the first light shielding structure 300.

For example, in some embodiments of the present disclosure, a planar shape of a portion of the first light shielding structure on the same layer as the dielectric layer is a closed loop shape, such as a "square" shape. The dielectric layer is arranged on two opposite sides of the part of the first light shielding structure on the same layer as the dielectric layer in the direction parallel to the surface of the active layer. Illustratively, as shown in fig. 2A and 2B, an orthographic projection of a portion of the first light shielding structure 300 on the same layer as the dielectric layer 100 on the surface of the active layer 210 is a closed ring shape, so that a shielding area of the first light shielding structure 300 for light emitted to the side surface of the active layer 210 along the dielectric layer 100 can be enhanced, and a risk of the active layer 210 being irradiated by light can be further reduced.

For example, in other embodiments of the present disclosure, a planar shape of a portion of the first light shielding structure on the same layer as the dielectric layer is a line segment shape. As shown in fig. 2A and 2C, the first light shielding structure 300 (not shown in fig. 2C) includes a plurality of sub light shielding structures having a line segment shape in a planar shape, such as a first sub light shielding structure 3001, a second sub light shielding structure 3002, a third sub light shielding structure 3003, and a fourth sub light shielding structure 3004. The first sub light shielding structure 3001, the second sub light shielding structure 3002, the third sub light shielding structure 3003, and the fourth sub light shielding structure 3004 are distributed around the active layer 210 to shield the active layer 210 from light. For example, as shown in fig. 2A and 2C, the dielectric layer 100 is disposed at all side surfaces of the first light shielding structure 300 that are in the same layer as the dielectric layer 100 in a direction parallel to the surface of the active layer 210. It should be noted that the number of the sub light shielding structures included in the first light shielding structure may be set as required, for example, the sub light shielding structure may be set on the side of the active layer 210 most affected by the illumination, so that the first light shielding structure has a smaller design volume while shielding the active layer of the switching element, the usage amount of the material forming the first light shielding structure is reduced to reduce the cost, the adverse effect on the manufacturing process of the switching element due to the setting of the first light shielding structure is reduced, the structure of the pixel unit is simplified, and the difficulty in the manufacturing process of the pixel unit is reduced.

The planar shape of the portion of the first light shielding structure on the same layer as the dielectric layer may be selected as needed, and is not limited to the closed loop shape and the segment shape described above. Next, a technical solution in at least one embodiment of the present disclosure described below will be described by taking, as an example, a case where a planar shape of a portion of the first light shielding structure that is in the same layer as the dielectric layer is a closed loop shape as shown in fig. 2A and 2B.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, in a direction parallel to a plane of the dielectric layer, the dielectric layer is provided with a recessed structure surrounding the switching element, and a portion of the first light shielding structure on a same layer as the dielectric layer is filled in the recessed structure. Illustratively, as shown in fig. 2A, a recess structure 101 is formed in the dielectric layer 100, and a portion of the first light shielding structure 300 fills the recess structure 101.

For example, in some embodiments, the recess structure may be provided as an opening as shown in fig. 2A, i.e., the dielectric layer 100 is disconnected at the recess structure 101, and the first light shielding structure 300 penetrates the dielectric layer 100. In this way, the shielding of the first light shielding structure 300 from light directed to the side surface of the active layer 210 along the dielectric layer 100 may be enhanced, further reducing the risk of the active layer 210 being irradiated with light. For example, in other embodiments, the recessed features may be provided as trenches having a depth greater than zero and less than the thickness of the dielectric layer.

In at least one embodiment of the present disclosure, the shape of the recessed feature (opening or slot) may be configured as desired. For example, the side walls of the recessed structure may be provided as a plane, a curved surface, a surface having a concavo-convex shape, or the like. Note that the sidewall of the recess structure is also a sidewall of the dielectric layer that is the same layer as the first light shielding structure and faces the first light shielding structure. For example, in the pixel unit provided by some embodiments of the present disclosure, the dielectric layer may be a single-layer structure or a stack of multiple sub-dielectric layers. For example, in the case where the dielectric layer is a stack of a plurality of sub-dielectric layers, a sidewall of the dielectric layer which is the same layer as the first light shielding structure and faces the first light shielding structure may be constituted by a sidewall of one sub-dielectric layer or may be constituted by sidewalls of a plurality of sub-dielectric layers. The first light shielding structure is related to the structure (e.g., sidewall) of the dielectric layer, and the first light shielding structure will be described below with reference to different arrangements of the sidewall of the dielectric layer.

For example, in some embodiments, as shown in fig. 2A, the sidewalls 1011 of the recessed feature 101 are substantially planar. For example, the sidewall 1011 is substantially perpendicular to the active layer 210. As such, when the first light shielding structure 300 is formed, in the case that the first light shielding structure 300 can fill the recessed structure 101, the flowability requirement of the material forming the first light shielding structure 300 is low or the material is not required to have the flowability, so that the process difficulty of filling the recessed structure 101 by the first light shielding structure 300 is low.

For example, in the pixel unit provided in other embodiments of the present disclosure, at least a portion of a sidewall of the dielectric layer, which is on a same layer as the first light blocking structure and faces the first light blocking structure, is formed as a protrusion and depression structure.

Illustratively, as shown in fig. 3, the sidewall 1011a of the recess structure 101a of the dielectric layer 300a is formed as an uneven structure 1012a such that the sidewall 1011a of the recess structure 101a has an uneven surface. For example, the concave structure 101a is an opening, and all of the side walls 1011a of the opening are formed as the concave-convex structure 1012 a. In this way, in the direction perpendicular to the surface of the active layer 210, the sidewall 1011a of the concave-convex structure 1012a makes the widths of the portions of the concave structure 101a different, and the sidewall 1011a formed with the concave-convex structure 1012a can make the first light shielding structure extend in the direction parallel to the surface of the active layer 210, so as to increase the shielding area of the first light shielding structure 300a for the light obliquely incident on the active layer 210 from the side of the dielectric layer 300a away from the active layer 210, and further reduce the risk of the active layer 210 being irradiated by the light.

For example, in at least one embodiment of the present disclosure, in a case where the sidewall of the recess structure of the dielectric layer is formed to have a concave-convex structure, a portion where the width of the concave-convex structure is large is located at the bottom of the recess structure (see the recess structure 101a in fig. 3) or at the middle of the recess structure (see the recess structure 101c in fig. 5) in a direction perpendicular to the plane of the active layer. In this way, it is possible to prevent a substance (e.g., hydrogen, etc.) of the first light shielding structure from invading the active layer due to a too close distance between the first light shielding structure and the active layer while extending the first light shielding structure toward the active layer to improve the light shielding effect of the first light shielding structure on the active layer. In addition, the first shading structure and the dielectric layer are not easy to separate due to the design, and the stability of the first shading structure is improved.

In at least one embodiment of the present disclosure, a manner of forming the recess structure in the dielectric layer and forming the sidewall of the recess structure to have the concave-convex structure is not limited, and the design may be performed according to an actual process. For example, in a pixel unit provided in at least one embodiment of the present disclosure, the dielectric layer is a stacked layer composed of at least two sub-dielectric layers. In this way, in the process of manufacturing each sub-dielectric layer, the patterning process can be respectively carried out on different sub-dielectric layers, so that the side wall of the concave structure is formed to have a concave-convex structure, and the difficulty of the manufacturing process is reduced.

For example, in a pixel unit provided by at least one embodiment of the present disclosure, the openings in the adjacent sub-dielectric layers are communicated or the opening of one of the adjacent sub-dielectric layers is communicated with the groove of the other sub-dielectric layer, and an orthogonal projection of the opening in the adjacent sub-dielectric layer or the opening of one of the adjacent sub-dielectric layers and the groove of the other sub-dielectric layer on the surface of the active layer is at least partially non-overlapped. For example, an orthogonal projection of the opening or the trench of one of the adjacent sub-dielectric layers on the surface on which the active layer is located is at least partially outside an orthogonal projection of the opening or the trench of the other of the adjacent sub-dielectric layers on the surface on which the active layer is located. In this way, the sub-recess structures (openings or grooves) having different widths in the direction parallel to the surface of the active layer are formed in the different sub-dielectric layers, and accordingly, the side walls of the recess structures formed by the sub-recess structures having different sizes may be formed to have the concave-convex structure.

Several ways of providing the recess structure will be described below with reference to the different number of sub-dielectric layers in the dielectric layer.

For example, in a pixel unit provided in some embodiments of the present disclosure, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer is located between the second sub-dielectric layer and the active layer, a first opening is disposed in the first sub-dielectric layer, a second opening or a second groove is disposed in the second sub-dielectric layer, the first opening and the second opening or the second groove are in communication, and an orthographic projection of the first opening on a plane where the active layer is located within an orthographic projection of the second opening or the second groove on the plane where the active layer is located.

Illustratively, as shown in fig. 4, the dielectric layer 100b includes a first sub-dielectric layer 110b and a second sub-dielectric layer 120b, and the first sub-dielectric layer 110b is located between the active layer 210 and the second sub-dielectric layer 120 b. The first sub-dielectric layer 110b is provided with a first opening 111b, the second sub-dielectric layer 120b is provided with a second opening 121b, the first opening 111b and the second opening 121b are communicated, and an orthographic projection of the first opening 111b on the surface (or the substrate 10) of the active layer 210 is positioned within an orthographic projection of the second opening 121b on the surface (or the substrate 10) of the active layer 210. In this way, the first opening 111b and the second opening 121b form the sidewall 1011b of the dielectric layer 100b into a concave-convex structure, the portion of the first light shielding structure 300b located at the second opening 121b may extend toward the active layer 210 to improve the light shielding effect of the first light shielding structure 300b on the active layer 210, and a certain distance is maintained between the portion of the first light shielding structure 300b located at the first opening 111b and the active layer 210, so as to prevent substances (such as hydrogen, etc.) of the first light shielding structure 300b from invading the active layer 210 due to the first light shielding structure 300b being too close to the active layer 210.

The method for forming the first opening 111B in the first sub-dielectric layer 110B and the second opening 121B in the second sub-dielectric layer 120B can refer to the description in the embodiment shown in fig. 10A to 10B, which is not repeated herein.

For example, in a pixel unit provided by at least one embodiment of the present disclosure, the dielectric layer includes at least three sub-dielectric layers, and projections of orthogonal projections of openings or slots of the sub-dielectric layers located at two sides on the surface where the active layer is located are located within an orthogonal projection of an opening of the sub-dielectric layer located in the middle on the surface where the active layer is located.

Illustratively, as shown in fig. 5, the dielectric layer 100c includes a third sub-dielectric layer 130c, a second sub-dielectric layer 120c, and a first sub-dielectric layer 110c stacked on the substrate base plate 10 in this order, and the active layer 210 is positioned on the first sub-dielectric layer 110 c. The first sub-dielectric layer 110c has a first opening 111c, the second sub-dielectric layer 120c has a second opening 121c, the third sub-dielectric layer 120c has a third opening 131c, the first opening 111c, the second opening 121c and the third opening 131c are communicated, and an orthogonal projection of the first opening 111c and the third opening 131c on the surface (or the substrate 10) where the active layer 210 is located within an orthogonal projection of the second opening 121c on the surface (or the substrate 10) where the active layer 210 is located. In this way, the first opening 111c, the second opening 121c and the third opening 131c form the sidewall 1011c of the dielectric layer 100c into a concave-convex structure, the portion of the first light shielding structure 300c located in the second opening 121c may extend toward the active layer 210 to improve the light shielding effect of the first light shielding structure 300c on the active layer 210, and a certain distance is maintained between the portion of the first light shielding structure 300c located in the first opening 111c and the active layer 210, so as to prevent substances (such as hydrogen and the like) of the first light shielding structure 300c from invading into the active layer 210 due to the first light shielding structure 300c being too close to the active layer 210.

For example, in other embodiments of the present disclosure, the structure of the dielectric layer 100c as shown in fig. 5 may be modified such that the orthographic projections of the first opening 111c and the second opening 121c on the substrate 10 are located within the orthographic projection of the third opening 131c on the substrate 10, or such that the orthographic projection of the first opening 111c on the substrate 10 is located within the orthographic projection of the second opening 121c and the third opening 131c on the substrate 10.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, the first light shielding structure includes a first portion and a second portion, the first portion is located on the same layer as the dielectric layer, and the second portion is located on a different layer from the dielectric layer. Illustratively, as shown in fig. 5, the first light shielding structure 300c includes a first portion 310c on the same layer as the dielectric layer 100c and a second portion 320c protruding beyond the dielectric layer 100 c. The thickness of the second portion 320c affects the light shielding effect of the first light shielding structure 300c on the active layer 210. For example, the greater the thickness of the second portion 320c, the better the light shielding effect of the first light shielding structure 300 c. The thickness of the second portion 320c may be determined according to an actual process, for example, the design thickness of the second portion 320c may be made as large as possible without affecting the performance of a switching element or the like in a pixel unit.

For example, in a pixel unit provided by at least one embodiment of the present disclosure, a distance from an end of the second portion facing away from the dielectric layer to a surface (or a substrate) on which the dielectric layer is located is greater than or equal to a distance from a surface of the active layer facing away from the dielectric layer to the surface (or the substrate) on which the dielectric layer is located. Illustratively, as shown in fig. 5, the height L2 of the second portion 320c is greater than the height L1 of the active layer 210, so that the shielding area of the first light shielding structure 300c for the dielectric layer 300c can be increased, and the risk of the active layer 210 being irradiated by light can be further reduced.

For example, the pixel unit provided by at least one embodiment of the present disclosure further includes a second light shielding structure, where the second light shielding structure is located on a side of the dielectric layer away from the active layer, and an orthogonal projection of the active layer on the active layer surface coincides with an orthogonal projection of the second light shielding structure on the active layer surface, or an orthogonal projection of the active layer on the active layer surface is located within an orthogonal projection of the second light shielding structure on the active layer surface. Illustratively, as shown in fig. 6, a second light shielding structure 400 is disposed between the substrate base plate 10 and the dielectric layer 100 c. The second light shielding structure 400 may shield light emitted from the substrate base plate 10 side toward the active layer 210.

For example, in some embodiments of the present disclosure, the switching element is a top gate thin film transistor as shown in fig. 6, and the second light shielding structure 400 may be separately disposed, for example, the second light shielding structure 400 is a light shielding metal and is not connected to other conductive structures such as signal lines and the like. For example, in other embodiments of the present disclosure, the switching element is a bottom gate type or dual gate type thin film transistor, and the second light shielding structure may be provided as a gate electrode.

For example, the second light shielding structure may include a metal material, and may be formed in a single layer or a multilayer structure, for example, a single layer of molybdenum or a molybdenum-niobium alloy, a single layer of aluminum, a single layer of molybdenum, or a structure in which two layers of molybdenum sandwich one layer of aluminum.

For example, in a pixel unit provided in at least one embodiment of the present disclosure, an orthogonal projection of the second light shielding structure on the surface of the active layer is located inside an orthogonal projection of the first light shielding structure on the surface of the active layer. The inner side here means a side of an orthographic projection of the first light shielding structure on the active layer-located face closer to an orthographic projection of the active layer on the active layer-located face. Thus, as shown in fig. 6, the first light shielding structure 300c and the second light shielding structure 400 cooperate to shield light emitted from the substrate 10 side to the active layer 210. For example, as shown in fig. 6, the dielectric layer 100c is disposed such that the portions of the first light shielding structure 300c and the second sub-dielectric layer 120c can extend toward the active layer 210, so that the gap between the first light shielding structure 300c and the second light shielding structure 400 can be reduced, and the light shielding effect of the first light shielding structure 300c and the second light shielding structure 400 on light can be improved.

For example, a pixel unit provided in at least one embodiment of the present disclosure further includes a light emitting device on a side of the switching element facing away from the dielectric layer, and the light emitting device may include a first electrode layer, a light emitting function layer, and a second electrode layer sequentially stacked on the switching element. Illustratively, as shown in fig. 7, the pixel unit includes a light emitting device 500, the light emitting device 500 includes a first electrode layer 510, a light emitting function layer 520, and a second electrode layer 530, the light emitting function layer 520 is interposed between the first electrode layer 510 and the second electrode layer 530, and the first electrode layer 510 is electrically connected to the drain electrode 231 of the switching element. For example, the pixel unit includes a passivation layer 260, the passivation layer 260 being positioned between the switching element (e.g., the drain electrode 231 therein) and the light emitting device 500, the passivation layer 260 having an opening formed therein, through which the first electrode layer 510 and the drain electrode 231 are connected.

For example, in some embodiments, a planarization layer may be disposed between the passivation layer and the light emitting device to improve the planarity of the first electrode layer, thereby improving the light emitting performance of the light emitting device. For example, in other embodiments, in the case that the passivation layer is configured to have a planarization effect, the planarization layer may not be required to be disposed between the passivation layer and the light emitting device, which simplifies the structure of the pixel unit and reduces the design thickness of the pixel unit, thereby facilitating the light and thin design of the pixel unit and the product (e.g., display substrate, display panel) including the pixel unit.

For example, in at least one embodiment of the present disclosure, one of the first electrode layer and the second electrode layer is provided as a reflective electrode layer. For example, the other of the first electrode layer and the second electrode layer may be provided as a transparent electrode layer or a translucent electrode layer. In this way, the display mode of the pixel unit can be realized as top emission or bottom emission. For example, as shown in fig. 7, in the case where the first electrode layer 510 is provided as a reflective electrode, the display mode of the pixel unit is top emission; in the case where the second electrode layer 520 is provided as a reflective electrode, the display mode of the pixel unit is bottom emission.

For example, in at least one implementation of the present disclosure, the first electrode layer is an anode of the light emitting device and the second electrode layer is a cathode of the light emitting device. The anode is used as a connecting layer of forward voltage of the light-emitting device and has better conductivity and higher work function value. For example, the anode may be formed of a conductive material having a high work function, and the electrode material of the anode may include Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Gallium Zinc Oxide (GZO), zinc oxide (ZnO), indium oxide (In)₂O₃) Aluminum Zinc Oxide (AZO), carbon nanotubes, and the like; the cathode is used as a connecting layer of the negative voltage of the light-emitting device, has better conductivity and lower work function value, and can be made of metal materials with low work function values, such as lithium, magnesium, calcium, strontium, aluminum, indium and the like, or the metal materials with low work function values and alloys of copper, gold and silver. In addition, in the case where the cathode formed of the metal material is required to transmit light, the thickness of the cathode is required to be designed to transmit light.

For example, in at least one embodiment of the present disclosure, in a case where the first electrode layer (anode) of the light emitting device is configured as a reflective electrode, the anode may be designed as a stack of a plurality of film layers, a portion of the film layers may be formed of a transparent conductive material (e.g., ITO, IZO, etc.), and another portion of the film layers may be an opaque conductive material (e.g., chromium, silver, etc.).

For example, in at least one embodiment of the present disclosure, transparent may represent a transmittance of light of 75% to 100%, and translucent may represent a transmittance of light of 25% to 75%.

For example, in at least one embodiment of the present disclosure, there is provided a light emitting device including a light emitting layer. For example, the light emitting function layer may further include one or a combination of a hole injection layer, a hole transport layer, an electron injection layer, and the like. For example, in a light emitting device, an anode, a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and a cathode are sequentially stacked. For example, an electron blocking layer and a hole blocking layer may be further disposed in the organic light emitting functional layer, the electron blocking layer being disposed between the anode and the organic light emitting layer, and the hole blocking layer being disposed between the cathode and the organic light emitting layer, but not limited thereto.

For example, in at least one embodiment of the present disclosure, the light emitting color of the light emitting device is not limited. For example, in the light emitting device, the material of the organic light emitting layer of the light emitting function layer may be selected according to a desired emission color. For example, the organic light emitting layer may emit red, green, blue, yellow, white, or other colors of light depending on the organic light emitting material used. For example, in some embodiments, the light emitting functional layers of the light emitting devices of the plurality of pixel units are integrated to emit light of the same color, such as white light, blue light, yellow light, or other colors. For example, in other embodiments, as shown in fig. 7, a pixel defining layer 501 is disposed in a pixel unit, and the pixel defining layer 501 spaces the light emitting function layers of the light emitting devices in different pixel units, so that the light emitting devices of different pixel units can be configured to emit light of different colors, respectively.

For example, at least one embodiment of the present disclosure provides a pixel unit further including a black matrix, the pixel unit including a display area and a non-display area located around the display area, the black matrix and the first light shielding structure being located in the non-display area. The black matrix is used for limiting the display area and the non-display area, light leakage is prevented, and mutual interference of light rays emitted between adjacent pixels is avoided.

For example, in at least one embodiment of the present disclosure, in a case where the first light blocking structure includes a first portion that is layered with the dielectric layer and a second portion that protrudes outside the dielectric layer, the black matrix may be disposed layered with the second portion and be an integrated structure. Illustratively, as shown in fig. 8A and 8B, the pixel unit is configured to have a bottom emission type display function, and the black matrix 600 and the first light shielding structure 300c (the second portion of the first light shielding structure 300 c) are integrated, so that the black matrix 600 is manufactured synchronously in the process of manufacturing the first light shielding structure 300c, the manufacturing process of the pixel unit is simplified, and the cost is reduced. Further, as shown in fig. 8A and 8B, the black matrix 600, the first light shielding structure 300c, and the switching element 200 are located in the non-display region 1100 of the pixel unit and serve to define the display region 1200 of the pixel unit. For example, the light emitting device 500 is at least partially located in the display region 1200. For example, as shown in fig. 8A, the second light shielding structure 400 is disposed in the area where the switching element 200 is located, so that the black matrix 600, the first light shielding structure 300c, and the second light shielding structure 400 cooperate to prevent light leakage in the non-display area of the pixel unit.

At least one embodiment of the present disclosure provides a display substrate, which may include the pixel unit in any one of the embodiments. For example, as shown in fig. 9, the display substrate is composed of a plurality of pixel units (the

pixel units

1000a, 1000b, 1000c, 1000d, etc. in fig. 9) arranged in an array, and the structures of the pixel units can refer to the related descriptions in the foregoing embodiments, which are not repeated herein.

For example, the display panel includes a plurality of rows and a plurality of columns of pixel cells. For example, each four pixel units may be a group, for example, in each row (along the X-axis direction) of pixel units, the

pixel units

1000a, 1000B, 1000c, 1000d of each group may be a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, respectively. Embodiments of the present disclosure do not limit the number and types of pixel units of each group, for example, each group may include a red subpixel R, a green subpixel G, a blue subpixel B and not include a white subpixel W, and for example, each pixel unit may include a red subpixel R, a green subpixel G, a blue subpixel B, a yellow subpixel Y, and the like.

For example, in at least one embodiment of the present disclosure, the display substrate may be a rigid substrate; or the display substrate can also be a flexible substrate, so that the display substrate can be applied to the field of flexible display. For example, when the display substrate is a rigid substrate, the base substrate may be a glass plate, a quartz plate, a metal plate, a resin plate, or the like. For example, in the case where the display substrate is a flexible substrate, the material of the base substrate may include an organic material, and for example, the organic material may be a resin-based material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

For example, in at least one embodiment of the present disclosure, the display substrate may be used in the field of micro OLED display, and accordingly, the substrate may be a silicon wafer. For example, the silicon wafer may be made of single crystal silicon, and the planar shape of the silicon wafer may be circular or may have other shapes.

For example, in at least one embodiment of the present disclosure, the display substrate may further include an encapsulation layer, the encapsulation layer being located on a side of the light emitting device facing away from the substrate, the encapsulation layer at least covering the light emitting device. The encapsulation layer can encapsulate the display substrate and prevent external water, oxygen and the like from entering the display substrate, so that components (such as a light emitting device) in the display substrate are protected.

For example, the encapsulation layer may have a single-layer structure or a composite structure of at least two layers. For example, the material of the encapsulation layer may include an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or polymer resin. For example, the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer sequentially disposed on the light emitting device. For example, the materials of the first encapsulation layer and the third encapsulation layer may include inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, and the like, and the inorganic materials have high compactness and can prevent the invasion of water, oxygen, and the like; for example, the material of the second encapsulation layer may be a polymer material containing a desiccant, a polymer material that blocks moisture, or the like, such as a polymer resin, to planarize the surface of the display substrate, and may relieve stress of the first encapsulation layer and the third encapsulation layer, and may further include a water-absorbing material such as a desiccant to absorb substances such as water, oxygen, and the like that intrude into the inside.

At least one embodiment of the present disclosure provides a display panel including the display substrate of any one of the foregoing embodiments. For example, in a display panel provided in at least one embodiment of the present disclosure, a package cover plate may be provided, and a switching element, a light emitting device, and the like in a display substrate are located between the package cover plate and a substrate of the display substrate, so that the package cover plate may protect the above elements. For example, in the display panel provided in at least one embodiment of the present disclosure, a touch substrate may be disposed on a display side of the display substrate so that the display panel obtains a touch display function.

For example, in the display panel provided by at least one embodiment of the present disclosure, a polarization layer may be disposed on the display side of the display substrate, and the polarization layer may include a polarizer, a retarder (e.g., 1/4 wave plate), and the like, so that light rays incident into the display substrate from the external environment do not exit from the display substrate, thereby eliminating adverse effects of ambient light on the display image of the display panel and improving the display effect of the display panel.

For example, in a display panel provided in at least one embodiment of the present disclosure, a color film may be disposed on a display side of a display substrate. The color film can absorb light of the external environment, so that the adverse effect of the ambient light on the display image of the display panel is reduced, and the display effect of the display panel is improved. For example, in a display panel provided in at least one embodiment of the present disclosure, a light splitting element (e.g., a light splitting grating, etc.) may be disposed on a display side of the display panel, so that the display panel may have a three-dimensional display function.

For example, the display panel may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, and a navigator.

For clarity, the entire structure of the display substrate and the display panel including the display substrate are not described. In order to implement the necessary functions of the display substrate and the display panel, a person skilled in the art may set other structures according to a specific application scenario, and the embodiment of the disclosure is not limited thereto.

At least one embodiment of the present disclosure provides a method for manufacturing a pixel unit, including: forming a dielectric layer; forming a switching element including an active layer on the dielectric layer; forming a first shading structure at least partially on the same layer as the dielectric layer; the orthographic projection of the first light shielding structure on the surface of the active layer is positioned outside the orthographic projection of the active layer on the surface of the active layer. In the pixel unit manufactured by the method, the first light shielding structure is positioned around the active layer and at least partially has the same layer with the dielectric layer, so that at least part of light rays which are emitted to the active layer from the side surface of the active layer along the dielectric layer can be shielded by the first light shielding structure, the increase of leakage current caused by photo-generated carriers generated by irradiating the active layer with light is reduced, and the stability of the switching element is improved.

For example, in a method for manufacturing a pixel unit provided in at least one embodiment of the present disclosure, forming a dielectric layer includes: the dielectric layer is patterned to form sidewalls at least partially of the relief structure in the dielectric layer. In this way, in the pixel unit manufactured by the method, in the direction perpendicular to the surface of the active layer, the first light shielding structure can extend in the direction parallel to the surface of the active layer by using the side wall formed with the concave-convex structure, so that the shielding area of the first light shielding structure for light obliquely incident to the active layer from the side of the dielectric layer, which is far away from the active layer, is increased, and the risk of the active layer being irradiated by light is further reduced.

For example, in a method of manufacturing a pixel unit provided in at least one embodiment of the present disclosure, patterning a dielectric layer to form an opening or a groove in the dielectric layer, sidewalls of the opening or the groove being formed as a convex-concave structure, the forming of the first light blocking structure includes: depositing a shading material layer on the dielectric layer to fill the opening or the groove, and patterning the shading material layer to form a first shading structure; wherein the dielectric layer surrounds the switching element.

For example, in a method for manufacturing a pixel unit provided in at least one embodiment of the present disclosure, a dielectric layer is formed as a stack of at least two sub-dielectric layers. In this way, in the pixel unit manufactured by the method, in the process of manufacturing each sub-dielectric layer, the patterning process can be respectively carried out on different sub-dielectric layers, so that the side wall of the concave structure is formed to have the concave-convex structure, and the difficulty of the manufacturing process can be reduced.

For example, in a method for manufacturing a pixel unit provided in at least one embodiment of the present disclosure, the dielectric layer is a stacked layer composed of at least two sub-dielectric layers, and forming the dielectric layer includes: forming a second sub-dielectric layer and forming a first sub-dielectric layer on the second sub-dielectric layer; patterning the first sub-dielectric layer and the second sub-dielectric layer to form a first opening in the first sub-dielectric layer; after forming a first opening in the first sub-dielectric layer, etching the second sub-dielectric layer by using the atmosphere with the first sub-dielectric layer as a mask to form a second opening or a second groove in the second sub-dielectric layer; wherein the materials forming the first sub-dielectric layer and the second sub-dielectric layer are different, and the etching ratio of the atmosphere to the material of the second sub-dielectric layer is larger than that to the material of the first sub-dielectric layer. In this way, in the pixel unit manufactured by the method, while the part of the first light shielding structure in the same layer with the second sub-dielectric layer extends towards the active layer to improve the light shielding effect of the first light shielding structure on the active layer, the part of the first light shielding structure in the same layer with the first sub-dielectric layer is prevented from being too close to the active layer to cause substances (such as hydrogen and the like) of the first light shielding structure to invade the active layer. In addition, the method ensures that the first shading structure and the dielectric layer are not easy to separate, and the stability of the first shading structure is improved.

It should be noted that, the structure of the pixel unit obtained by the above manufacturing method can refer to the relevant contents in the foregoing embodiments (for example, the embodiments shown in fig. 1 to fig. 8B), and is not repeated herein.

Next, taking the manufacturing of the pixel unit as shown in fig. 6 as an example, the manufacturing process of the pixel unit may include the following processes as shown in fig. 10A to 10F and fig. 6.

As shown in fig. 10A, a substrate base plate 10 is provided and a light blocking material film is deposited on the substrate base plate, a patterning process is performed on the light blocking material film to form a second light blocking structure 400, and then three insulating material films are sequentially deposited on the second light blocking structure 400 to form a third sub-dielectric layer 130c, a second sub-dielectric layer 120c, and a first sub-dielectric layer 110c covering the second light blocking structure 400 and sequentially stacked on the substrate base plate 10.

For example, in at least one embodiment of the present disclosure, the patterning process may be a photolithographic patterning process, which may include, for example: the method includes the steps of coating a photoresist layer on a structural layer to be patterned, exposing the photoresist layer using a mask plate, developing the exposed photoresist layer to obtain a photoresist pattern, etching the structural layer using the photoresist pattern, and then optionally removing the photoresist pattern.

For example, the material forming the second light shielding structure 400 may be a metal, such as molybdenum or a molybdenum-niobium alloy, and the thickness may be 0.1-0.2 um. For example, in the photolithography patterning process to form the second light shielding structure 400, wet etching may be performed using a mixed acid (e.g., including at least two of hydrochloric acid, nitric acid, sulfuric acid, hydrofluoric acid, or other types of acids).

For example, the material of the third sub-dielectric layer 130c is silicon oxide, the material of the second sub-dielectric layer 120c is silicon nitride, and the material of the first sub-dielectric layer 110c is silicon oxide. For example, the thickness of the third sub-dielectric layer 130c may be 0.2 to 0.25um, the thickness of the second sub-dielectric layer 120c may be 0.07 to 0.1um, and the thickness of the first sub-dielectric layer 110c may be 0.2 to 0.25 um. Within the above range, the dielectric layer 100c may enable the first light shielding structure to have a better light shielding effect, and the first light shielding structure is spaced from the active layer by a distance that is sufficient for a substance (e.g., hydrogen, etc.) of the first light shielding structure to hardly intrude into the active layer.

As shown in fig. 10B, a photoresist is deposited on the dielectric layer 100c, and the photoresist is developed to form a photoresist pattern 1. The photoresist pattern 1 includes an opening 2 exposing the dielectric layer 100 c. For example, the thickness of the photoresist pattern may be 2.0um to 2.2 um. The width of the portion of the photoresist pattern 1 between the openings 2 may be designed according to the size of the switching element, for example, the width of the portion of the photoresist pattern 1 between the openings 2 may be 6um to 10 um. For example, in a process of patterning a photoresist using a mask, a post Bake (Hard baker) process may not be performed on the photoresist, and in this case, the photoresist pattern 1 may be formed in an inner concave shape, that is, an intermediate portion of the photoresist pattern 1 in a direction perpendicular to the surface of the substrate base plate 10 is inwardly contracted.

As shown in fig. 10C, the first sub-dielectric layer 110C is patterned (e.g., dry-etched) using the photoresist pattern 1 as a mask to form a first opening 111C corresponding to the opening 2 in the first sub-dielectric layer 110C. For example, the material of the second sub-dielectric layer 120c is silicon nitride, the material of the first sub-dielectric layer 110c is silicon oxide, and an atmosphere for etching the first sub-dielectric layer 110c during the patterning process may be carbon tetrafluoride (CF)₄) And oxygen (O)₂) Mixed, the etching selectivity of the atmosphere to silicon oxide is greater with respect to silicon nitride, so that the atmosphere is used only for etching the first sub-dielectric layer 110 c. For example, CF₄The flow rate of (A) may be 2000-2500 sccm, O₂The flow rate of (2) can be 1000-1500 sccm, and high source power and high bias power are performed. Example (b)For example, in the case where the photoresist pattern 1 is formed to have an inner concave shape as shown in fig. 10C, lateral oxygen ashing is slow, and after dry etching, the sidewall of the first opening 111C is substantially perpendicular to the surface of the substrate 100.

As shown in fig. 10D, the second sub-dielectric layer 120c is patterned (e.g., dry-etched) using the photoresist pattern 1 and the first sub-dielectric layer 110c as a mask to form a second opening 121c corresponding to the first opening 111c in the second sub-dielectric layer 120 c. For example, the material of the third sub-dielectric layer 130c is silicon oxide, the material of the second sub-dielectric layer 120c is silicon nitride, the material of the first sub-dielectric layer 110c is silicon oxide, and during the patterning process, the atmosphere may be carbon tetrafluoride (SF)₆) And oxygen (O)₂) Mixed, the etching selectivity of the atmosphere to silicon nitride is greater with respect to silicon oxide, so that the atmosphere is used only for etching the second sub-dielectric layer 120 c. For example, SF₆The flow rate of (A) may be 2000-2500 sccm, O₂The flow rate of (1) can be 600-800 sccm, and high source power and low bias power are performed due to SF₆The fluorine content is high, the etching gas is isotropic, under the condition of low bias power, the etching rate of the atmosphere to silicon oxide is very slow (silicon oxide is easier to etch by opening Si-O bonds through bias power bombardment), and the etching rate to silicon nitride is higher (Si-N bonds are low in energy and active SF groups can directly react with the Si-O bonds). As such, the second opening 121c is larger than the width of the first opening 111c, i.e., the orthographic projection of the first opening 111c on the substrate base 10 is located within the orthographic projection of the second opening 121c on the substrate base 10.

As shown in fig. 10E, the third sub-dielectric layer 130c is patterned (e.g., dry-etched) using the photoresist pattern 1 and the first sub-dielectric layer 110c as a mask to form a third opening 131c corresponding to the first opening 1 in the third sub-dielectric layer 130 c. For example, the material of the second sub-dielectric layer 120c is silicon nitride, the material of the third sub-dielectric layer 130c is silicon oxide, and an atmosphere for etching the third sub-dielectric layer 130c during the patterning process may be carbon tetrafluoride (CF)₄) And oxygen (O)₂) Mixed, the etching of silicon oxide in the atmosphere is selected relative to silicon nitrideThe ratio is chosen larger such that the atmosphere is only used for etching the third sub-dielectric layer 130 c. For example, CF₄The flow rate of (A) may be 2000-2500 sccm, O₂The flow rate of (2) can be 1000-1500 sccm, and high source power and high bias power are performed. For example, in the case where the photoresist pattern 1 is formed to have an internal concave shape as shown in fig. 10E, lateral oxygen ashing is slow, and after dry etching, the sidewall of the third opening 131c is substantially perpendicular to the surface of the substrate 100, and the third opening 131c corresponds to and has substantially the same size as the first opening 111c, that is, the third opening 131c substantially overlaps the orthographic projection of the first opening 111c on the substrate 10. For example, after the third opening 131c is formed, the remaining photoresist pattern 1 may be removed by wet stripping. The first opening 111c, the second opening 121c, and the third opening 131c constitute a concave structure 101c, and a side wall 1011c of the concave structure 101c is a surface having an uneven structure.

As shown in fig. 10F, a light shielding material is applied (e.g., coated, ink-jet printed, or otherwise) on the dielectric layer 100c, the light shielding material fills the recess structure 101c, and a patterning process is performed on a film layer formed of the light shielding material to form a first light shielding structure 300 c. For example, the light shielding material for forming the first light shielding structure 300c may be BM (Black Matrix) glue. The BM glue has a certain fluidity so that the concave structure 101c (e.g., the first opening 111c, the second opening 121c, and the third opening 131c) can be filled, and after the BM glue fills the concave structure 101c, the BM glue is subjected to a post-baking treatment. For example, the thickness of the BM may be 0.8um to 1.1 um. For example, the thickness of the portion (the first portion in the foregoing embodiment) of the first light shielding structure 300c that is on the same layer as the dielectric layer 100c may be 0.6-0.8 um, and the thickness of the portion (the second portion in the foregoing embodiment) of the first light shielding structure 300c that protrudes out of the dielectric layer 100c may be 0.2-0.3 um.

Note that in the process of forming the first light shielding structure 300c as shown in fig. 10F, a patterning process may be performed on a film layer formed by the BM glue to form the first light shielding structure 300c and the black matrix 600 as shown in fig. 8A.

As shown in fig. 6, a manufacturing process of the switching element is performed on the dielectric layer 100c, which may include the following processes.

A semiconductor material, which may be indium tin oxide (IGZO) and may have a thickness of 0.05 to 0.1um, is deposited on the dielectric layer 100c to perform a patterning process (e.g., photolithography, wet etching) to form the active layer 210.

A gate insulating material film is deposited on the active layer 210, and the material may be silicon oxide, and the thickness may be 0.1um to 0.2 um.

A conductive material film is deposited on the gate insulating material film and a patterning process is performed to form a gate electrode 220, for example, the gate electrode may be made of a metal such as copper, and the thickness of the gate electrode may be 0.4 to 0.5 um.

For example, in the process of forming the gate electrode through the patterning process, the thickness of the photoresist used may be 2.0 to 2.2um, the photoresist may be a positive photoresist, and the side surface of the photoresist pattern formed after the masking by the photoresist may be an inclined surface, for example, the inclined surface may have an inclination angle of 60 to 70 °. The conductive material film layer is first wet etched using the photoresist pattern as a mask to form a gate electrode, for example, in the case where the gate electrode material includes copper, the copper wet etch may be H₂O₂And (4) carrying out liquid medicine.

After the wet etching is completed, the gate insulating material film is dry etched through the photoresist pattern and the gate electrode 220 to form the gate insulating layer 240 using a dry etching apparatus, for example, CF with a high content may be used₄And low content of O₂Dry etching with mixed gas, CF₄The flow rate can be 2000-2500 sccm, O₂The flow rate is 1000-1500 sccm.

For example, after the gate electrode 220 and the gate insulating layer 240 are formed, a portion of the active layer 210 not covered with the gate electrode 220 and the gate insulating layer 240 may be subjected to a conductor forming process. For example, ammonia (NH) gas may be used in the conductor forming process₃) Or helium (He).

For example, after the gate electrode 220 and the gate insulating Layer 240 are formed or the active Layer 210 is subjected to a conductor processing, a residual photoresist may be removed by wet stripping, and then an insulating material film is deposited on the substrate 10 to form an interlayer Dielectric Layer 250 (ILD), where the interlayer Dielectric Layer 250 may be silicon oxide, silicon nitride, silicon oxynitride, or the like, and the thickness may be 0.45 to 0.6 um.

For example, a via hole exposing the active layer 210 is formed in the interlayer dielectric layer 250, and then a conductive material film layer connected to the active layer 210 through the via hole of the interlayer dielectric layer 250 is deposited on the interlayer dielectric layer 250, patterned to form source and drain electrode layers (a drain electrode 231 and a source electrode 232), and the drain electrode 231 and the source electrode 232 are respectively connected to the active layer 210 through different via holes formed in the interlayer dielectric layer 250. For example, the source/drain electrode layer can be made of copper, aluminum, or other metal with a thickness of 0.5-0.7 um

For example, after forming the source and drain electrode layers, an insulating material may be deposited on the substrate to form a passivation layer (PVX), wherein the material may be silicon oxide, silicon nitride, silicon oxynitride, or the like, and the thickness may be 0.3 to 0.5 um. For example, after the passivation layer is formed, a manufacturing process of the light emitting device may be performed on the passivation layer. The manufacturing process of the passivation layer and the light emitting device may refer to a conventional manufacturing process, and the structures of the formed passivation layer and the light emitting device may refer to the description in the embodiment shown in fig. 7, which is not described herein again.

For the present disclosure, there are also the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A pixel cell, comprising:

a dielectric layer;

a switching element including an active layer and located on the dielectric layer; and

the first shading structure is at least partially arranged on the same layer as the dielectric layer;

wherein, the orthographic projection of the first light shielding structure on the surface of the active layer is positioned outside the orthographic projection of the active layer on the surface of the active layer;

at least a portion of a sidewall of the dielectric layer, which is on the same layer as the first light shielding structure and faces the first light shielding structure, is formed as a convex-concave structure.

2. The pixel cell of claim 1,

the dielectric layer is arranged on at least two opposite sides of the part of the first shading structure, which is on the same layer as the dielectric layer.

3. The pixel cell of claim 1,

the dielectric layer is provided with an opening or a groove surrounding the switching element on a face parallel to the dielectric layer, and a sidewall of the opening or the groove is formed as the projection and depression structure.

4. The pixel cell of claim 3,

the dielectric layer is a stack of at least two sub-dielectric layers.

5. The pixel cell of claim 4,

the openings in the adjacent sub-dielectric layers communicate or the opening of one of the adjacent sub-dielectric layers communicates with the groove of the other, an

The openings in the adjacent sub-dielectric layers or the openings of one of the adjacent sub-dielectric layers and the orthographic projection of the grooves of the other sub-dielectric layer on the surface of the active layer are at least partially not overlapped.

6. The pixel cell of claim 5,

the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer is positioned between the second sub-dielectric layer and the active layer, a first opening is arranged in the first sub-dielectric layer, a second opening or a second groove is arranged in the second sub-dielectric layer,

the first opening is communicated with the second opening or the second groove, and the orthographic projection of the first opening on the surface of the active layer is positioned in the orthographic projection of the second opening or the second groove on the surface of the active layer.

7. The pixel cell of claim 5,

the dielectric layer comprises at least three sub-dielectric layers, and projections of the openings or grooves of the sub-dielectric layers on two sides on the surface of the active layer are located in the orthographic projection of the opening of the sub-dielectric layer in the middle on the surface of the active layer.

8. The pixel cell of any one of claims 1-7,

the first light shielding structure comprises a first part and a second part, the first part and the dielectric layer are on the same layer, and the second part and the dielectric layer are on different layers.

9. The pixel cell of claim 8,

the distance from one end of the second part, which is far away from the dielectric layer, to the surface of the dielectric layer is greater than or equal to the distance from the surface, which is far away from the dielectric layer, of the active layer to the surface of the dielectric layer.

10. The pixel cell of claim 8, further comprising a black matrix, wherein,

the pixel unit comprises a display area and a non-display area positioned around the display area, the black matrix and the first light shielding structure are positioned in the non-display area,

the black matrix and the second part are on the same layer and are of an integrated structure.

11. The pixel cell of any of claims 1-7, further comprising:

the second light shielding structure is positioned on one side of the dielectric layer, which is far away from the active layer;

wherein an orthographic projection of the active layer on the surface of the active layer coincides with an orthographic projection of the second light shielding structure on the surface of the active layer, or

The orthographic projection of the active layer on the surface of the active layer is positioned in the orthographic projection of the second light shielding structure on the surface of the active layer.

12. The pixel cell of claim 11,

the orthographic projection of the second light shielding structure on the surface of the active layer is positioned inside the orthographic projection of the first light shielding structure on the surface of the active layer.

13. The pixel cell of any of claims 1-7, further comprising:

a light emitting device located on a side of the switching element facing away from the dielectric layer;

wherein the light emitting device includes a first electrode layer, a light emitting function layer, and a second electrode layer sequentially stacked on the switching element,

one of the first electrode layer and the second electrode layer is a reflective electrode layer.

14. A display substrate comprising a plurality of pixel cells according to any one of claims 1-13 arranged in an array.

15. A method of fabricating a pixel cell, comprising:

forming a dielectric layer;

forming a switching element including an active layer on the dielectric layer;

forming a first shading structure at least partially on the same layer as the dielectric layer;

16. The method of manufacturing of claim 15, wherein forming the dielectric layer comprises:

the dielectric layer is patterned to form sidewalls at least partially of the relief structure in the dielectric layer.

17. The manufacturing method according to claim 16, wherein patterning the dielectric layer to form an opening or a groove in the dielectric layer, a sidewall of the opening or the groove being formed as the projection and depression structure, the forming of the first light shielding structure comprises:

depositing a light shielding material layer on the dielectric layer to fill the opening or the groove, and patterning the light shielding material layer to form the first light shielding structure;

wherein the dielectric layer surrounds the switching element.

18. The manufacturing method according to claim 17,

the dielectric layer is formed as a stack of at least two sub-dielectric layers.

19. The manufacturing method of claim 18, wherein the dielectric layer is a stack of at least two sub-dielectric layers, forming the dielectric layer comprising:

forming a second sub-dielectric layer and forming a first sub-dielectric layer on the second sub-dielectric layer;

patterning the first sub-dielectric layer and the second sub-dielectric layer to form a first opening in the first sub-dielectric layer;

after the first opening is formed in the first sub-dielectric layer, the second sub-dielectric layer is etched by using atmosphere by taking the first sub-dielectric layer as a mask so as to form a second opening or a second groove in the second sub-dielectric layer;

wherein the materials forming the first sub-dielectric layer and the second sub-dielectric layer are different, and the etching ratio of the atmosphere to the material of the second sub-dielectric layer is greater than that to the material of the first sub-dielectric layer.