CN109918133A - A kind of electrical power transmission system multi-core task processing method - Google Patents
A kind of electrical power transmission system multi-core task processing method Download PDFInfo
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- CN109918133A CN109918133A CN201910068431.4A CN201910068431A CN109918133A CN 109918133 A CN109918133 A CN 109918133A CN 201910068431 A CN201910068431 A CN 201910068431A CN 109918133 A CN109918133 A CN 109918133A
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Abstract
The present invention relates to electric power system data processing technology field, according to the solution procedure of task problem, task especially a kind of electrical power transmission system multi-core task processing method, comprising the following steps: task is parallel: is divided into several subtasks；Data parallel: according to the mode of processing data, multiple relatively independent data fields is formed, are handled respectively by different processors；Multiple programming: selection Parallel Programming Environment carries out the parallel Programming of CPU；As a result parallel compilation: the parallel Programming for carrying out CPU is compiled.After adopting the above method, core cpu utilization rate of the present invention is higher, and the processing of electric power system data task is faster；When there is a CPU core free time in system, appropriate task execution is just chosen from the task waiting list of the core, the advantages of this method is that task switches in the heart substantially without in multiple CPU cores, is conducive to improve core cpu Local C ache hit rate.
Description
Technical field
The present invention relates to electric power system data processing technology field, especially a kind of electrical power transmission system multi-core task
Processing method.
Background technique
Buck converter provides electric power to multi-core processor due to being advantageously used for high power efficiency.But
It is that in traditional design, each core in multi-core processor is powered by identical step down voltage redulator.Unfortunately, due to
Be not the equal duchy of each core in identical load condition in the same time, thus it is such design reduce it is whole
Power efficiency.The expectation level of core voltage needed for some cores may be high, while core voltage needed for other cores
It is expected that level may be low.By identical step down voltage redulator by identical voltage supplied to different cores will lead to it is unnecessary
Power dissipation, and reduce whole power efficiency.
107306085 A of Chinese invention patent CN discloses a kind of power transmission system and multicore processing chip, wherein electricity
Power conveyer system includes: the first power transmission unit, is coupled to the first power-supply device, for will be from first power-supply device
Supply power to the first core of multicore processing chip；And second power transmission unit, it is coupled to second source equipment, is used
In the level of the core voltage according to needed for first core, selectively by supplying power to from the second source equipment
First core.
Summary of the invention
The technical problem to be solved by the invention is to provide at a kind of efficient multi-core task of electrical power transmission system
Reason method.
In order to solve the above technical problems, a kind of electrical power transmission system multi-core task processing method of the invention,
The following steps are included:
Task is parallel: according to the solution procedure of task problem, task being divided into several subtasks；
Data parallel: according to the mode of processing data, multiple relatively independent data fields are formed, by different processor point
Other places reason；
Multiple programming: selection Parallel Programming Environment carries out the parallel Programming of CPU；
As a result parallel compilation: the parallel Programming for carrying out CPU is compiled.
Preferably, the parallel compilation of the step results is further comprising the steps of:
Flow point analysis: related to control to source code progress correlation analysis, including stream correlation, inverse correlation, output correlation；And
Carry out data dependence test；
Program optimization: code optimization, including code vector and code parallelization；
Code building: the specific machine object code that the code conversion journey of the intermediate form after optimization can be performed.
Preferably, the parallel Programming of CPU includes implicitly parallel, data parallel, shares in the step multiple programming
Variable and message transmission；Wherein,
Stealthy parallel: by known serial Programming with Pascal Language, compiler and operation support system are automatically converted to parallel generation
Code；
Data parallel: being the natural model of SIMD, local calculation and data routing operation；
Shared variable: being the natural model of PVP, SMP and DSM；
Message transmission: being the natural model of MPP and COW.
Preferably, the basic skills of parallelization used in programming includes mutually parallel, flowing water in the step multiple programming
Line is parallel, Master-slave parallel, parallel and work pool of dividing and ruling are parallel.
Preferably, the mode that serial program performance optimizes in the step multiple programming includes calling high-performance library, selection
Compiler Optimization option appropriate, reasonable definition array dimension pay attention to the sequence and loop unrolling of nested circulation.
Preferably, the mode that parallel program performance optimizes in the step multiple programming includes: to reduce the traffic, improve and lead to
Believe granularity；Global communication, which uses, utilizes efficient collective communication algorithm；The degree of parallelism of mining algorithm reduces CPU idle waiting；Load
It is balanced；Communication, the overlapping calculated；It is computed repeatedly by introducing to reduce communication.
After adopting the above method, core cpu utilization rate of the present invention is higher, and the processing of electric power system data task is faster；When being
When having a CPU core free time in system, appropriate task execution, this method are just chosen from the task waiting list of the core
The advantages of be that task switches in the heart substantially without in multiple CPU cores, be conducive to improve core cpu Local C ache hit rate.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
Fig. 1 is multithreading schematic diagram of the present invention.
Fig. 2 is hyperthread CPU operational efficiency schematic diagram of the present invention.
Fig. 3 is the parallel computation schematic diagram of multicore of the present invention.
Specific embodiment
A kind of electrical power transmission system multi-core task processing method of the invention, comprising the following steps:
Task is parallel: according to the solution procedure of task problem, task being divided into several subtasks.One process can possess
Multiple threads, and a thread can only belong to a process.Each process contains at least one thread --- and main thread, it is responsible for
The initial work of program, and execute the initial order of program.Then, main thread can be to execute a variety of different tasks and difference
Create multiple sub threads.
Multiple operations of one program can be completed by starting multiple examples (i.e. multiple processes) of the program,
An example (process) for the program can be only run, and is accomplished by the multiple threads of the process creation.Obvious the latter wants
It is more more efficient than the former, it can more save the limited resources of system.This requests needs in the thousands of a users of synchronization response
Web server program and Network package capture program etc. for be vital.As shown in Figure 1, in which: A serves as theme
Journey, B, C, D are all the sub thread of A, and the sub thread of the same name in different parallel tasks can be different.
As shown in Fig. 2, in time can be in the same time using hyperthread, the different portions of chip can be used in application program
Point.Although single thread chip is capable of handling thousands of item instructions each second, it is merely able to instruct one at any one time
It is operated.And Hyper-Threading can make chip while carry out multiple threads, and chip performance is made to get a promotion.Hyperthread skill
Art allows processor in the case where only increasing by 5% chip area, so that it may bring 15%~30% enhancing efficiency.But it is practical
On, in certain programs or not for the program of multithreading compiling, hyperthread can reduce efficiency instead.In addition to this, hyperthread
CPU technology is also required to the cooperation of board chip set and operating system, can just give full play to the efficiency of hyperthread.
Data parallel: according to the mode of processing data, multiple relatively independent data fields are formed, by different processor point
Other places reason.Traditional serial computing, is divided into " instruction " and " data " two parts, and when program executes " independently application and
Occupy " memory headroom, and all calculating are confined to the memory headroom.As shown in figure 3, parallel computation is relatively independent by process
It is allocated on different nodes, is dispatched by operating system independent；Enjoying independent CPU and memory source, (memory can be with
It is shared)；Mutual information exchange passes through message transmission between process.
Multiple programming: selection Parallel Programming Environment carries out the parallel Programming of CPU.Wherein, common multiple programming ring
Mainly there are three classes in border: message transmission, shared storage and data parallel, referring to table 1, the data parallel mode that we use.
1 Parallel Programming Environment table of table
We are related to 4 levels using the multiple programming of multi-core CPU in total in this way:
● instruction level: very thin granularity；
● data Layer: fine granularity；
● control layer: middle granularity；
● task layer: big granularity.
Processing is mostly responsible for by hardware and compiler first two layers, two layers parallel after programmer is usually handled.CPU and stroke
Sequence design, following four kinds of models:
■ implicitly parallel (Implicit Parallel) --- programmer (is not defined with known serial Programming with Pascal Language
Formulation concurrency), compiler and operation support system are automatically converted to parallel codes.Have a characteristic that it is semantic simple, can
Transplantability is good, single thread (being easy to debugging and verification correctness), fine grained parallel, efficiency are very low.
■ data parallel (Data Parallel) --- it is the natural model of SIMD, local calculation and data routing operation.
Have a characteristic that single thread, parallel work-flow in aggregated data structure (array), loose synchronization, single address space, implicit friendship
Interaction, explicit data distribution.The advantages of data parallel is that the relatively easy and serial parallel program of programming is consistent；Disadvantage has program
Performance is largely dependent upon compiling system and user used and is confined to data to the understanding of compiling system, parallel granularity
Grade is parallel, granularity is smaller.
■ shared variable (Shared Variable) --- it is the natural model of PVP, SMP and DSM.It has a characteristic that
Multithreading (SPMD, MPMD), asynchronous, single address space, explicit synchronization, hidden data distribution, implicit communication.
■ message transmission (Message Passing) --- it is the natural model of MPP and COW.It has a characteristic that multi-thread
Journey, the asynchronous, multiple address space, explicit synchronization, explicit data mapping and load distribution, explicit communication.
Wherein: using the most common parallel data processing, make full use of the multicore ability of CPU, also reduce the difficulty of exploitation
Degree.
Wherein, the basic skills of parallelization used in programming has:
■ phase is parallel (Phase Parallel)
■ pipeline parallel method (Pipeline Parallel)
■ Master-slave parallel (Master-Slave Parallel)
■ divides and rules parallel (Divide and Conquer Parallel)
■ work pool is parallel (Work Pool Parallel)
Serial program performance optimal way:
■ calls high-performance library, such as the BLAS (Basic Linear Algebra Subprograms, the fundamental line that optimize
Property algebra subprogram), (Fastest Fourier Transformin the West, west Fast Fourier Transform are FFTW
Most fast FFT free software library) etc.；
■ selects Compiler Optimization option appropriate；
■ reasonable definition array dimension；
■ pays attention to the sequence of nested circulation, improves the locality of data access as far as possible；
■ loop unrolling.
Parallel program performance optimal way:
■ reduces the traffic, improves communication granularity；
■ global communication utilizes efficient collective communication algorithm as far as possible；
The degree of parallelism of ■ mining algorithm reduces CPU idle waiting；
■ load balancing；
The overlapping that ■ is communicated, calculated；
■ computes repeatedly to reduce communication by introducing, i.e., changes communication to calculate.
As a result parallel compilation: being compiled the parallel Programming for carrying out CPU, specifically includes the following steps:
A, flow point is analysed
Flow point analysis mainly correlation analysis, including stream correlation, inverse correlation, output correlation are related to control.Also need into
Row data dependence test, the correlation between subscript reference pair to prove same aray variable are not present.
B, program optimization
Program optimization is exactly code optimization, mainly includes code vector and code parallelization:
■ code vector --- in scalar program by it is a kind of can the operational transformation completed of vectorization circulation at vector
Operation.
The optimization of ■ code parallelization --- parallel codes is that a program is launched into multithreading with while at more
Reason machine executes parallel, and its purpose is to reduce total execution time.
C, code building
Parallel codes, which generate, is related to the specific machine mesh that the code conversion journey of the intermediate form after optimizing can be performed
Mark code.Including execution order, instruction selection, register distribution, load balance, parallel granularity, Code schedule and rear optimization
The problems such as.
Although specific embodiments of the present invention have been described above, those skilled in the art should be appreciated that this
It is merely illustrative of, various changes or modifications can be made to present embodiment, without departing from the principle and substance of the present invention,
Protection scope of the present invention is only limited by the claims that follow.
Claims (6)
1. a kind of electrical power transmission system multi-core task processing method, which comprises the following steps:
Task is parallel: according to the solution procedure of task problem, task being divided into several subtasks；
Data parallel: according to the mode of processing data, multiple relatively independent data fields are formed, respectively by different processors
Reason；
Multiple programming: selection Parallel Programming Environment carries out the parallel Programming of CPU；
As a result parallel compilation: the parallel Programming for carrying out CPU is compiled.
2. electrical power transmission system described in accordance with the claim 1 multi-core task processing method, which is characterized in that the step
As a result parallel compilation is further comprising the steps of:
Flow point analysis: related to control to source code progress correlation analysis, including stream correlation, inverse correlation, output correlation；And carry out
Data dependence test；
Program optimization: code optimization, including code vector and code parallelization；
Code building: the specific machine object code that the code conversion journey of the intermediate form after optimization can be performed.
3. electrical power transmission system described in accordance with the claim 1 multi-core task processing method, it is characterised in that: the step
The parallel Programming of CPU includes implicitly parallel, data parallel, shared variable and message transmission in multiple programming；Wherein,
Stealthy parallel: by known serial Programming with Pascal Language, compiler and operation support system are automatically converted to parallel codes；
Data parallel: being the natural model of SIMD, local calculation and data routing operation；
Shared variable: being the natural model of PVP, SMP and DSM；
Message transmission: being the natural model of MPP and COW.
4. electrical power transmission system described in accordance with the claim 1 multi-core task processing method, it is characterised in that: the step
The basic skills of parallelization used in programming includes parallel phase, pipeline parallel method, Master-slave parallel, divides and rules parallel in multiple programming
It is parallel with work pool.
5. electrical power transmission system described in accordance with the claim 1 multi-core task processing method, it is characterised in that: the step
The mode that serial program performance optimizes in multiple programming includes calling high-performance library, selects Compiler Optimization option appropriate, is closed
Dimension of defining arrays is managed, pays attention to the sequence and loop unrolling of nested circulation.
6. electrical power transmission system described in accordance with the claim 1 multi-core task processing method, it is characterised in that: the step
The mode that parallel program performance optimizes in multiple programming includes: to reduce the traffic, improve communication granularity；Global communication is using utilization
Efficient collective communication algorithm；The degree of parallelism of mining algorithm reduces CPU idle waiting；Load balancing；Communication, the overlapping calculated；It is logical
Introducing is crossed to compute repeatedly to reduce communication.
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