CN109905124B - Analog-to-digital converter and analog-to-digital conversion method - Google Patents
Analog-to-digital converter and analog-to-digital conversion method Download PDFInfo
- Publication number
- CN109905124B CN109905124B CN201711282347.XA CN201711282347A CN109905124B CN 109905124 B CN109905124 B CN 109905124B CN 201711282347 A CN201711282347 A CN 201711282347A CN 109905124 B CN109905124 B CN 109905124B
- Authority
- CN
- China
- Prior art keywords
- sub
- converter
- stage
- analog
- weight
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims description 8
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 claims description 4
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- 101100434411 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ADH1 gene Proteins 0.000 description 4
- 101150102866 adc1 gene Proteins 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
An analog-to-digital converter and an analog-to-digital conversion method enable a pipeline analog-to-digital converter to be corrected by using a code density-based correction algorithm, and therefore a pipeline ADC is corrected for capacitance mismatch by using the code density-based correction algorithm.
Description
Technical Field
The present invention relates to analog-to-digital conversion technologies, and in particular, to an analog-to-digital converter and an analog-to-digital conversion method.
Background
A pipelined ADC (analog-to-digital converter or analog-to-digital converter), also called a sub-area ADC, is an efficient and powerful analog-to-digital converter. It can provide high speed, high resolution analog to digital conversion, and has satisfactory low power consumption and small chip size; through reasonable design, excellent dynamic characteristics can be provided. In high-speed and high-precision application occasions, the assembly line is a widely applied and favored structure. The pipelined ADC includes multiple stages of sub-converters connected in series, each sub-converter is a single-stage ADC, and an amplifier (also called a residual amplifier) is connected in series between adjacent sub-converters.
The sub-converter comprises a capacitor and a comparator, and the mismatch of the capacitor (capacitor mismatch) affects the accuracy of the sub-converter and thus the accuracy of the pipelined ADC.
Disclosure of Invention
The present invention is directed to an analog-to-digital converter and an analog-to-digital conversion method, which can facilitate calibration.
In order to solve the above problems, according to an aspect of the present invention, there is provided an analog-to-digital converter including: the system comprises X-level sub-converters connected in series, wherein at least part of the sub-converters have at least one redundancy, and X is more than or equal to 2; the operation unit is used for carrying out iterative shift addition on the outputs of all the sub-converters according to the weight to obtain a total output; wherein when the iterative phase shift is performed, the output of the previous sub-converter is sequentially left-shifted with respect to the output of the next sub-converter, and the number of bits left-shifted is equal to the number of bits of the next output. Combining the outputs of the multi-stage sub-converters into the total output similar to the output of the single-stage ADC, the number of steps of the total output being greater than the number of bits, the total output being an output result with redundancy, the total output being equivalent to the output of the single-stage ADC, the ADC equivalent to the total output being capable of correcting using a code-density based correction algorithm (code-density correction algorithm), thereby correcting the pipeline ADC for capacitance mismatch using the code-density based correction algorithm.
Optionally, in the adc, if the y-th stage of the sub-converter is an Ny-bit My step, the total output equivalent single-stage adc is an N-bit M step, and y takes a value from 1 to X, then the total output equivalent single-stage adc is an N-bit M step
Optionally, in the analog-to-digital converter, in the single-stage analog-to-digital converter with equivalent total output,
S(j)＝Sy(a y )×2 N(y+1) ×2 N(y+2) ×...×2 NX ，
Wherein,
s (j) is the weight of the j step in the single-stage analog-digital converter with equivalent total output, Sy (a) y ) For the a-th sub-converter of the y-th order y Step weight, step j in the single-stage analog-digital converter with equivalent total output corresponds to step a in the y-th sub-converter y And step (2), the h-th-level sub-converter is an Nh bit, y takes values from 1 to X, j takes values from 1 to M, and the total output equivalent single-stage analog-digital converter is M steps.
Optionally, in the adc, the y-th sub-converter is Ny bits, the y-th sub-converter has My steps, My > Ny ≧ 2, and at least one subsequent step has a weight less than half of the weight of the previous step, so as to form redundancy in the y-th sub-converter, and y takes a value from 1 to X. Wherein, the weight of the next step is less than half of the weight of the previous step and can be expressed as:
sy (i) > 2 XSy (i-1), Sy (i) is the weight of the ith step in the y-th stage of the sub-converter.
Optionally, in the analog-to-digital converter, the operation unit obtains a final output Dout according to the following relationship:
the total output equivalent single-stage analog-digital converter is M steps, b [ i ] is the ith bit, S (i) is the weight of the ith step, S (M) is the weight of the Mth step, and S (0) represents the least significant bit of the equivalent single-stage analog-digital converter.
Optionally, in the analog-to-digital converter, all the sub-converters are successive approximation type converters, and each step of the sub-converters is implemented by one comparison capacitor; an amplifier is connected in series between the adjacent sub-converters; correcting the capacitance mismatch of the total output equivalent single stage analog to digital converter using a code density based correction algorithm.
Optionally, in the adc, the y-th sub-converter includes a main step lookup, where the main step lookup is used to determine that the y-th sub-converter is Ny bit, and y takes a value from 1 to X.
Optionally, in the analog-to-digital converter, the main step search of at least one of the sub-converters includes redundancy, and the weight of at least one subsequent step is less than half of the weight of the previous step.
Optionally, in the adc, at least one of the z-th stage sub-converters further includes at least one additional search, where the additional search is located after the main step search, and in the z-th stage sub-converter, the main step search is configured to determine a magnification factor of a weight in the z-1 th stage sub-converter, the additional search is configured to increase a margin coverage of the z-th stage sub-converter, a value of z is 2 to X, and each of the additional searches is a redundancy.
Wherein, in one of the sub-converters, redundancy may be included in the main step search without including additional search; redundancy can also be excluded from the main step search, but additional searches are included; alternatively, redundancy is included in the main step lookup, along with additional lookups.
The invention also provides an analog-digital conversion method, which comprises the following steps:
providing X-level sub-converters connected in series, wherein at least part of the sub-converters have at least one redundancy, and X is more than or equal to 2; and
and carrying out iterative shift addition on the outputs of all the sub-converters, sequentially carrying out left shift addition on the output of the previous sub-converter relative to the output of the next sub-converter, and obtaining the total output, wherein the number of left shift bits is equal to the number of steps of the next sub-converter. Combining the outputs of the multi-stage sub-converters into the total output similar to the output of the single-stage ADC, wherein the total output has a step number larger than a bit number, the total output is an output result with redundancy, and the single-stage ADC equivalent to the total output can be corrected by using a code-density based correction algorithm (code-density based correction algorithm), so that the pipeline ADC is corrected for capacitance mismatch by using the code-density based correction algorithm.
Optionally, in the analog-to-digital conversion method, the final output Dout is obtained according to the following relationship:
the total output equivalent single-stage analog-digital converter is N bits, the total output equivalent single-stage analog-digital converter is M steps, b [ i ] is the ith bit, S (i) is the weight of the step corresponding to the ith bit, S (M) is the weight of the M step, and S (0) represents the least significant bit of the equivalent single-stage analog-digital converter;
the sub-converter of the y level is Ny-bit My step, the single-level analog-digital converter with equivalent total output is N-bit M step, y takes values from 1 to X, and then
In a single stage analog to digital converter where the total output is equivalent,
s (j) is the weight of the j step in the single-stage analog-digital converter with equivalent total output, Sy (a) y ) For the a-th sub-converter of the y-th order y Step weight, step j in the single-stage analog-digital converter with equivalent total output corresponds to step a in the y-th sub-converter y Step, the h-th level sub-converter is an Nh bit, y takes values from 1 to X, j takes values from 1 to M, and the total output equivalent single-stage analog-digital converter is M steps;
correcting the capacitance mismatch of the total output equivalent single stage analog to digital converter using a code density based correction algorithm.
Optionally, in the analog-to-digital conversion method, the y-th-stage sub-converter includes a main step search, where the main step search is used to determine that the y-th-stage sub-converter is Ny bit, and y takes a value from 1 to X; the main step search of at least one sub-converter comprises redundancy, and the weight of at least one next step is less than half of the weight of the previous step; at least one of the sub-converters of the z-th level further comprises at least one additional search, the additional search is located after the main step search, in the sub-converter of the z-th level, the main step search is used for determining the magnification factor of the weight in the sub-converter of the z-1 th level, the additional search is used for increasing the margin coverage of the sub-converter of the z-th level, the value of z is 2 to X, and each additional search is a redundancy.
Drawings
The invention is described in detail below with reference to the following figures and embodiments:
FIG. 1 is a block diagram of a two-stage pipelined analog-to-digital converter;
FIG. 2 is a schematic diagram of a 3-bit 4-step search process for a level 1 sub-converter and a 3-bit 4-step search process for a level 2 sub-converter;
FIG. 3 is a logic diagram of iterative shift-and-add;
FIG. 4 is a schematic diagram of the search process of the integrated equivalent single-stage (6-bit 8-step) ADC;
FIG. 5 is a schematic diagram of a 3-bit 4-step search process for a level 1 sub-converter and a 3-bit 5-step search process for a level 2 sub-converter;
FIG. 6 is a logic diagram of iterative shift-and-add;
FIG. 7 is a schematic diagram of the search process of the integrated equivalent (6-bit 9-step) single-stage ADC;
FIG. 8 is a diagram illustrating additional look-ups to increase the voltage coverage of the level 2 sub-converter;
fig. 9 is a flowchart illustrating an analog-to-digital conversion method.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
As shown in fig. 1, which is a schematic circuit diagram of a pipeline analog-to-digital converter with a two-stage structure, a pipeline ADC1 includes two stages of sub-converters connected in series, respectively: a 1 st stage Sub-converter Sub-ADC1 and a 2 nd stage Sub-converter Sub-ADC 2. An amplifier 110 is connected in series between the Sub-ADC1 of the 1 st stage and the Sub-ADC2 of the 2 nd stage, and the amplifier 110 amplifies a residual (residual). The operation unit 120 operates the output D1out of the Sub-ADC1 of the 1 st stage and the output D2out of the Sub-ADC2 of the 2 nd stage to obtain the final output Dout.
The stage 1 Sub-converter Sub-ADC1 may be a SAR (successive approximation register) ADC, and redundancy may be formed by a Sub-binary search method (Sub-binary search). The Sub-ADC2 of the 2 nd stage may also be a SAR (successive approximation register) ADC, and redundancy may be formed by a Sub-binary search method (Sub-binary search). In the sub-binary search method, the weight of at least one subsequent step is less than half the weight of the previous step.
Referring to fig. 2, the 1 st-stage Sub-converter Sub-ADC1 is N1 bits (bit), N1 is 3, the 1 st-stage Sub-converter Sub-ADC1 has M1 steps (step), M1 is 4 (representing comparison 4 times, each step is turned onThe comparison is performed by comparing capacitors, and the magnitude ratio of capacitance values between capacitors determines the weight of each step), and the weight (step size) is S1 ═ 4,1,1]Wherein [4,1,1]The first 4 of (1), (4), (1) and (1)]Represents the weight for comparison, [4,1,1]The last 1 in (1) indicates that S1(0) is 1, and S1(0) is to ensure a 3-bit range, i.e., 2, of the 1 st-stage Sub-converter Sub-ADC1 3 4+1+1+1+ 8. Generally, M1 step requires at least M1+1 weights to guarantee N1 bit range. The Sub-ADC2 of the 2 nd Sub-converter is N2 bits (bit), N2 is 3, the Sub-ADC2 of the 2 nd Sub-converter has M2 steps, M2 is 4 (representing comparison 4 times), and the weight (step size) is S2 in turn [4,1,1,1 ═ 4]Wherein [4,1,1]The first 4 of (1), (4), (1) and (1)]Represents the weight for comparison, [4,1,1]The last 1 in (1) indicates that S2(0) is 1, and S2(0) is to ensure a 3-bit range, i.e., 2, of the 2 nd-stage Sub-converter Sub-ADC2 3 4+1+1+1+ 8. Generally, at least M2+1 weights are needed for the M2 step to guarantee the N2 bit range. The voltage coverage FR1 of the 1 st-stage Sub-ADC1 is 10V, and the voltage coverage FR2 of the 2 nd-stage Sub-ADC2 is 10V. In fig. 2, 4 steps of the 1 st-stage Sub-converter Sub-ADC1 are main step lookups, and 4 steps of the 2 nd-stage Sub-converter Sub-ADC2 are main step lookups.
When the full ranges FS of the 1 st-stage Sub-ADC1 and the 2 nd-stage Sub-ADC2 are both 10V, if the input voltage Vin of the pipeline ADC1 is 7.125V, and Vin is 7.125V, the 1 st-stage Sub-ADC1 starts to perform the lookup, and the pipeline ADC1 inputs the voltage Vin to the 1 st-stage Sub-ADC 1. The sequence of searching (the searching process is the comparison process) is the first searching P11, the second searching P12, the third searching P13 and the fourth searching P14, the sequence numbers of the searching and the sequence numbers of the steps are arranged in reverse, that is, when the first searching P11 is performed (the sequence number of the searching is 1), the sequence number of the step is 4, and so on. In the first search P11, the sequence number of step is 4, i.e. step 4, the weight S1(4) of step 4 is 4, and the 3 rd bit output b1[3 ]]1 is ═ 1; when the second search P12 is performed (sequence number of search is 2), the sequence number of step is 3, that is, step 3, the weight S1(3) of step 3 is 1, and the 2 nd bit output b1[2 ]]1 is ═ 1; when a third search P13 is performed (sequence number of search is 3), the step number is 2, i.e. step number is 2Step 2, weight S1(2) of step 2 is 1, and output b1[ 1] of bit 1]0; when the fourth lookup P14 is performed (the sequence number of the lookup is 4), the sequence number of the step is 1, that is, the step 1, the weight S1(1) of the step 1 is 1, and the 0 th bit output b1[0 []1. After the above searching steps, the output D1out of the Sub-ADC1 of the 1 st stage is [1101]]. Wherein, S1 (a) 1 ) Denotes the a in the 1 st stage 1 Weight of step, b1[ c 1 ]Denotes the c-th in level 1 1 Output of bits, a 1 Values from 0 to M1, c 1 Values from 0 to M1-1.
The 1 st Sub-converter Sub-ADC1 has a margin of 7.125-5 × (10 ÷ 8) ═ 0.875V, and the amplifier 110 amplifies the margin. Since the Sub-ADC2 of the 2 nd stage is 3 bits (bit), the margin is amplified by 8 times (8 ×), the margin voltage vreside input to the Sub-ADC2 of the 2 nd stage is 0.875 × 8, 7V, and the Sub-ADC2 of the 2 nd stage starts to perform the lookup. The sequence of searching is P21 for the first time, P22 for the second time, P23 for the third time and P24 for the fourth time, the sequence number of searching and the sequence number of the step are arranged in reverse, namely when P21 is searched for the first time, the sequence number of the step is 4, and so on. When the first search P21 is performed (the sequence number of the search is 1), the sequence number of the step is 4, that is, the 4 th step, the weight S2(4) of the 4 th step is 4, and the 3 rd bit output b2[3 ]]1 is ═ 1; when the second search P22 is performed (sequence number of search is 2), the sequence number of step is 3, that is, step 3, weight S (3) of step 3 is 1, and 2 nd bit output b2[2 ]]1 is ═ 1; when the third search P23 is performed (the sequence number of the search is 3), the step number is 2, that is, the weight S2(2) of the 2 nd step is 1, and the 1 st bit output b2[ 1]]0; when the fourth lookup P24 is performed (the sequence number of the lookup is 4), the sequence number of the step is 1, that is, the step 1, the weight S2(1) of the step 1 is 1, and the 0 th bit output b2[0 []1. After the above searching steps, the output D2out of the Sub-ADC2 of the 2 nd stage is [1101]]. Wherein, S2 (a) 2 ) Denotes the a in the 2 nd level 2 Weight of step, b2[ c 2 ]Denotes the c-th in level 2 2 Output of bits, a 2 Values from 0 to M2, c 2 Values from 0 to M2-1.
The arithmetic unit 120 Sub-converts the output D1out of the Sub-ADC1 of the 1 st stage Sub-converter and the 2 nd stageThe output D2out of the Sub-ADC2 is subjected to iterative shift addition according to the weight, the digital algorithm logic of the iterative shift addition is shown in FIG. 3, and the output D1out of the Sub-ADC1 of the 1 st stage is [1101]]Left shift by 4 positions to obtain [11010000]Then shifted left [11010000]And the output D2out [1101] of the Sub-ADC2 of the 2 nd stage]Adding to obtain N-bit digital output code with M steps, total output D' [11011101]]，b[i]And the output of the ith bit is represented, i is 8 to 0, N is 6, and M is 9. The total output D' is weighted by S ═ 32,8,8,8,4,1,1]Wherein, the weight of the corresponding step of the left shift is the weight of the corresponding step of the Sub-ADC1 of the 1 st stage multiplied by N2. The total output D' is weighted by S ═ 32,8,8,8,4,1,1]It can be understood that: s ═ 4,1,1 of Sub-ADC1 of stage 1 Sub-converter]Is amplified by 8 times to become S ═ 32,8,8]The 2 nd Sub-converter Sub-ADC2 refines the last 8 to form S ═ 32,8,8,8, [4,1,1,1]]Wherein [32,8,8,8,4,1,1]The first 8 of [32,8,8,8,4,1,1, 1] s]Represents the weight for comparison, [32,8,8,8,4,1,1]The last 1 in (1) indicates that S (0) is 1, S (0) is to ensure a 6-bit range of the total output D', i.e., 2 6 32+8+8+8+4+1+1+1+ 64. Generally, M steps require at least M +1 weights to guarantee N-bit scale.
Thus, the outputs of the two-stage pipeline ADCs of the 1 st-stage Sub-converter Sub-ADC1 and the 2 nd-stage Sub-converter Sub-ADC2 are combined into the output of a single-stage ADC. As shown in fig. 4, in the combined single-stage ADC, the input voltage Vin is 7.125V, and the voltage coverage FR is 10V. The searching sequence is a first searching P1, a second searching P2, …, a seventh searching P7 and an eighth searching P8, wherein the first searching P1 to the fourth searching P4 sequentially correspond to the first searching P11 to the fourth searching P14, and the fifth searching P5 to the eighth searching P8 sequentially correspond to the first searching P21 to the fourth searching P24. The sequence numbers of the searches are arranged in reverse with the sequence numbers of the steps, that is, when the first search is performed at P1, the sequence number of the step is 8, and so on.
When the first search P1 is performed, the sequence number of step is 8, that is, step 8, the weight S (8) of step 8 is 32, and the output b [7] of bit 7 is 1; when the second search P2 is performed, the sequence number of step is 7, that is, step 7, the weight S (7) of step 7 is 1, and the output b [6] of bit 6 is 1; …, respectively; in the eighth search P8, the step number is 1, i.e., step 1, the weight S (1) of step 1 is equal to 1, and the output b [0] of bit 0 is equal to 1. Through the above lookup steps, a total output D' is obtained [11011101 ]. Wherein, S (a) represents the weight of the step a, b [ c ] represents the output of the c bit, a takes the values from 0 to M, and c takes the values from 0 to M-1.
The operation unit 120 converts the total output D' [11011101] into a final output Dout according to the following formula (1),
where S (M) represents the weight of the mth step, S (i) represents the weight of the ith step, S (0) is 1 (where S (0) represents the LSB of the least significant bit of the ADC, and in general, S (0) is 1, and when there is a mismatch in the ADC, S (0) may not be 1), b [ i ] represents the output of the ith bit, and b [0] represents the output of the 0 th bit.
From the total output D' [11011101] and S ═ 32,8,8,8,4,1,1, 1], we get:
Dout＝S(8)+(2×b[7]-1)×S(7)+(2×b[6]-1)×S(6)+(2×b[5]-1)×S(5)+(2×b[4]-1)×S(4)+(2×b[3]-1)×S(3)+(2×b[2]-1)×S(2)+(2×b[1]-1)×S(1)+(b[0]-1)×S(0)
＝32+(2×1-1)×8+(2×1-1)×8+(2×0-1)×8+(2×1-1)×4+(2×1-1)×1+(2×1-1)×1+(2×0-1)×1+(1-1)×1
＝32+8+8-8+4+1+1-1+0
＝45
the merged single stage ADC is 6-bit 8-step, N < M, and redundancy is formed by a sub-binary search method. The merged single stage ADC may be corrected by a code density (code density) based correction algorithm. Some bins (bins) in the histogram or output code density may be zero due to redundancy. The zero code bin represents a missing code. Errors (error) occur when performing the sub-binary search method on the combined single-stage ADC, so that one input (analog information) can be combined into a plurality of 8-step digital output codes, and a part of the digital output codes are empty. Since the input analog information is not lost, errors (error) can be digitally corrected (digital calibration). The total output may be corrected for capacitance mismatch using a code density based correction algorithm (code density based correction algorithm).
In converting the total output D' [11011101] into the final output Dout according to equation (1) and correcting the capacitance mismatch using a correction algorithm based on code density, it is necessary to combine the multi-stage pipeline analog-to-digital converter into a single-stage ADC, and in order to improve the accuracy of correction, to eliminate amplifier mismatch (comparator offset), gain stage offset (gain stage offset) or gain error (gain error), optionally, an additional lookup is added in the Sub-converter Sub-ADC2 of stage 2.
Referring to fig. 5, the 1 st-stage Sub-converter Sub-ADC1 has N1 bits (bit), N1 is equal to 3, the 1 st-stage Sub-converter Sub-ADC1 has M1 steps, M1 is equal to 4 (representing comparison 4 times), and the weights (step size) are S1 in turn equal to [4,1,1, 1] 4]Wherein [4,1,1]The first 4 of (1), (4), (1) and (1)]Represents the weight for comparison, [4,1,1]The last 1 in (1) indicates that S1(0) is 1, S1(0) is 1 indicates that the least significant bit LSB of the 1 st-stage Sub-converter Sub-ADC1 is 1, and S1(0) is to ensure the 3-bit range of the 1 st-stage Sub-converter Sub-ADC1, i.e., 2 3 4+1+1+1+ 8. Generally, at least M1+1 weights are needed for the M1 step to guarantee the N1 bit range. The Sub-ADC2 of the 2 nd Sub-converter is N2 bits (bit), N2 is 3, the Sub-ADC2 of the 2 nd Sub-converter has M2 steps, M2 is 5 (representing 5 comparisons), and the weight (step size) is S2 in turn [4,1,1,1,1,1 ═ 4,1,1,1 ═ 5]Wherein [4,1,1,1,1,1]The first 5 of (3) [4,1, 1)]Represents the weight for comparison, [4,1,1,1,1,1]The last 1 in (1) indicates that S2(0) ═ 1, and S2(0) ═ 1 indicates that the least significant bit LSB of the Sub-ADC2 of the 2 nd stage is 1. In the Sub-ADC2 of the 2 nd-stage Sub-converter, the first 4 steps are main step search, and 3-bit search is realized; step 5 is an additional search for increasing the voltage coverage of the Sub-ADC2 of the stage 2 Sub-converter, so as to realize over-range coverage. The voltage coverage FR1 of the 1 st-stage Sub-ADC1 is 10V, and the voltage coverage FR2 of the 2 nd-stage Sub-ADC2 is 12.5V.
When the 1 st Sub-converter Sub-ADC1When the full scale FS is 10V, if the input voltage Vin of the pipeline ADC1 is 7.125V, and Vin is 7.125V, the input voltage Vin is input to the Sub-ADC1 of the 1 st stage, and the Sub-ADC1 of the 1 st stage starts to perform the lookup. The sequence of searching is P11 for the first time, P12 for the second time, P13 for the third time and P14 for the fourth time, the sequence number of searching and the sequence number of the step are arranged in reverse, namely when P11 is searched for the first time, the sequence number of the step is 4, and so on. In the first search P1, the sequence number of step is 4, i.e. step 4, the weight S1(4) of step 4 is 4, and the 3 rd bit output b1[3 ]]1 is ═ 1; in the second search P12, the sequence number of step is 3, i.e. step 3, the weight S1(3) of step 3 is 1, and the 2 nd bit output b1[2 ]]1 is ═ 1; when the third search P13 is performed, the step number is 2, that is, the weight S1(2) of the 2 nd step is 1, and the 1 st bit output b1[ 1]]0; in the fourth search P14, the sequence number of step is 1, i.e. step 1, the weight S1(1) of step 1 is 1, and the 0 th bit output b1[0 []1. After the above searching steps, the output D1out of the Sub-ADC1 of the 1 st stage is [1101]]. Wherein, S1 (a) 1 ) Denotes the a in the 1 st stage 1 Weight of step, b1[ c 1 ]Denotes the c-th in level 1 1 Output of bits, a 1 Values from 1 to M1, c 1 Values from 0 to M1-1.
The 1 st Sub-converter Sub-ADC1 has a margin of 7.125-5 × (10 ÷ 8) ═ 0.875V, and the amplifier 110 amplifies the margin. Since the 2-stage Sub-converter Sub-ADC2 has 3 bits (bit), the margin is amplified by 8 times (8 ×), the margin voltage vressigue input to the 2 nd-stage Sub-converter Sub-ADC2 is 0.875 × 8, 7V, and the 2 nd-stage Sub-converter Sub-ADC2 starts performing the lookup. The searching sequence includes first searching P21, second searching P22, third searching P23, fourth searching P24 and fifth searching P25, the sequence numbers of the searching and the sequence numbers of the steps are arranged in a reverse way, namely when the first searching P21 is carried out, the sequence numbers of the steps are 5, and so on. In the first search P21, the sequence number of step is 5, i.e. step 5, the weight S2(5) of step 5 is 4, and the 4 th bit output b2[4 ]]1 is ═ 1; in the second search P22, the sequence number of step is 4, i.e. step 4, the weight S2(4) of step 4 is 1, and the 3 rd bit output b2[3]1 is ═ 1; in a third lookup P23, the step number is 3,that is, the weight S2(3) of the 3 rd step is 1 in the 3 rd step, and the 2 nd bit output b2[2 ]]0; in the fourth search for P24, the step number is 2, i.e. the weight S2(2) of step 2 is 1, and the 1 st bit output b2[ 1[ ]]1 is ═ 1; when the fifth search P25 is performed, the sequence number of step is 1, i.e. step 1, the weight S2(1) of step 1 is 1, and the 0 th bit output b2[0 []1. Through the above searching steps, the output D2out of the Sub-ADC2 of the 2 nd-stage Sub-converter is [11010]]. Wherein, S2 (a) 2 ) Denotes the a in the 2 nd stage 2 Weight of step, b2[ c 2 ]Denotes the c-th in level 2 2 Output of bits, a 2 Values from 0 to M2, c 2 Values from 0 to M2-1.
The arithmetic unit 120 iteratively shifts and adds the output D1out of the Sub-ADC1 of the 1 st stage and the output D2out of the Sub-ADC2 of the 2 nd stage according to the weight, and the digital arithmetic logic of the iterative shift and addition is as shown in fig. 6, the output D1out [1101] of the Sub-ADC1 of the 1 st stage is shifted to the left by 5 bits to obtain [110100000], and then [110100000] after the left shift is added to the output D2out [11010] of the Sub-ADC2 of the 2 nd stage to obtain a digital output code of M steps of N bits, i 'total output D' [110111010], bi [ i ] represents the output of the i th bit, i takes a value of 8 to 0, N is 6, and M is 9. The total output D' is weighted by [32,8,8,8,4,1,1,1,1,1] in turn, wherein the weight of the step corresponding to the left shift is the weight of the corresponding step of the 1 st stage Sub-ADC1 multiplied by N2. The total output D' in turn is weighted by S ═ 32,8,8,8,4,1,1,1,1,1] can be understood as: after the Sub-ADC1 of the 1 st stage has been amplified 8 times, S becomes [32,8,8,8,8] and the Sub-ADC2 of the 2 nd stage further refines the last 8, so that S becomes [32,8,8,8, [4,1,1,1,1,1] ]isformed, where the first 9 [32,8,8, 1,1,1,1,1] of [32,8,8, 4,1,1, 1] of [32,8,8, 4,1,1,1,1] represent weights for comparison, the last 1 of [32,8,8,8,4,1,1, 1] represents S (0) 1, and S2(0) represents that the LSB of an equivalent single stage ADC is 1.
Thus, the outputs of the two-stage pipeline ADCs of the 1 st-stage Sub-converter Sub-ADC1 and the 2 nd-stage Sub-converter Sub-ADC2 are combined into the output of a single-stage ADC. As shown in fig. 7, in the combined single-stage ADC, the input voltage Vin is 7.125V, and the over-range coverage OR is 10.3125V. The searching sequence is a first searching P1, a second searching P2, …, a seventh searching P7, an eighth searching P8 and a ninth searching P9, wherein the first searching P1 to the fourth searching P4 sequentially correspond to the first searching P11 to the fourth searching P14, and the fifth searching P5 to the ninth searching P9 sequentially correspond to the first searching P21 to the fifth searching P25. The sequence numbers of the searches are arranged in reverse with the sequence numbers of the steps, that is, when the first search is performed at P1, the sequence number of the step is 9, and so on.
When the first search P1 is performed, the sequence number of step is 9, that is, step 9, the weight S (9) of step 9 is equal to 32, and the output b [8] of bit 8 is equal to 1; when the second search P2 is performed, the sequence number of step is 8, that is, step 8, the weight S (8) of step 8 is 8, and the output b [7] of bit 7 is 1; …, respectively; in the ninth search P9, the step number is 1, i.e., step 1, the weight S (1) of step 1 is 1, and the 0 th bit output b [0] is 0. Through the above lookup steps, the total output D' is obtained [110111010 ]. Wherein, S (a) represents the weight of the step a, b [ c ] represents the output of the c bit, a takes values from 0 to M, and c takes values from 0 to M-1.
The arithmetic unit 120 converts the total output D' [110111010] into a final output Dout according to the following formula (1),
wherein, S (M) represents the weight of the mth step, S (i) represents the weight of the ith step, S (0) is 1 (wherein, S (0) represents the LSB of the least significant bit of the ADC, in general, S (0) is 1, when there is mismatch in the ADC, S (0) may not be 1), b [ i ] represents the output of the ith bit, b [0] represents the output of the 0 th bit.
From the total output D' [110111010] and S ═ 32,8,8,8,4,1,1,1,1,1], we obtain:
Dout＝S(9)+(2×b[8]-1)×S(8)+(2×b[7]-1)×S(7)+(2×b[6]-1)×S(6)+(2×b[5]-1)×S(5)+(2×b[4]-1)×S(4)+(2×b[3]-1)×S(3)+(2×b[2]-1)×S(2)+(2×b[1]-1)×S(1)+(b[0]-1)×S(0)
＝32+(2×1-1)×8+(2×1-1)×8+(2×0-1)×8+(2×1-1)×4+(2×1-1)×1+(2×1-1)×1+(2×0-1)×1+(2×1-1)×1+(0-1)×1
＝32+8+8-8+4+1+1-1+1-1
＝45
the merged single stage ADC is 6-bit 9-step, N < M, and redundancy is formed by a sub-binary search method. The merged single stage ADC may be corrected by a code density (code density) based correction algorithm (calibration algorithm). Some bins (bins) in the histogram or output code density may be zero due to redundancy. The zero code bin represents a missing code. Errors (error) occur when performing the sub-binary search method on the combined single-stage ADC, so that one input (analog information) can be combined into a plurality of 8-step digital output codes, and a part of the digital output codes are empty. Since the input analog information is not lost, errors (errors) can be digitally corrected (digital calibration). The total output may be corrected for capacitance mismatch using a code-density based correction algorithm (calibration algorithm).
As shown in fig. 5, in the Sub-ADC2 of the 2 nd stage, since the additional search, the fifth search P25, is performed after the main step search, the range of the reference level REF is expanded from 0 ~ 7 to-1 ~ 8 compared to the main step search alone; as shown in fig. 8, during amplification, if there is amplifier mismatch, gain stage offset or gain error, the margin Vreside of the input Vin may exceed the Main Range (i.e. 0-7) of the Main search and fall into the extra Range (i.e. -1 or 8) of the Main search, so as to eliminate the influence caused by amplifier mismatch, gain stage offset or gain error and improve the accuracy of the code density-based correction algorithm of the pipeline ADC; when the structures of the 1 st-stage Sub-converter Sub-ADC1 and the 2 nd-stage Sub-ADC2 are combined, as shown in fig. 7, the actual range of the reference level REF is expanded from 0 to 63 to-1 to 64, compared to the main step search alone, and the over-range coverage is realized.
Fig. 9 is a flowchart illustrating an analog-to-digital conversion method. Connecting the sub-converters in series: the 1 st-stage Sub-converter Sub-ADC1 and the 2 nd-stage Sub-converter Sub-ADC2 are connected in series; iteratively shift-adding the outputs of all the sub-converters: performing iterative shift addition on the outputs of the Sub-ADC1 of the 1 st stage and the Sub-ADC2 of the 2 nd stage to obtain a total output D'; the capacitance mismatch is corrected using a code density based correction algorithm.
Specific embodiments of the present invention are described above, but the present invention is not limited to the above-disclosed scope, for example:
the extra search is not limited to 1 step, and can be multiple steps, and each step forms a redundancy;
the weight of each step in the additional search is not limited to 1, and can be other values;
there may be a plurality of redundancies in the main step search, and the main step search of the y-th-stage sub-converter is a Ny-bit My step, and My-Ny is equal to e, so that the main step search has e redundancies.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited by the foregoing examples, which are provided to illustrate the principles of the invention, and that various changes and modifications may be made without departing from the spirit and scope of the invention, which is also intended to be covered by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. An analog-to-digital converter, comprising:
the system comprises X-level sub-converters connected in series, wherein at least part of the sub-converters have at least one redundancy, and X is more than or equal to 2; and
the arithmetic unit is used for carrying out iterative shift addition on the outputs of all the sub-converters, the output of the previous sub-converter is sequentially added after being left-shifted relative to the output of the next sub-converter, and the number of left-shifted bits is equal to the number of steps of the next sub-converter so as to obtain the total output, wherein the sub-converter at the y-th level is Ny-bit My step, the single-stage analog-digital converter equivalent to the total output is N-bit M step, and y takes values from 1 to X, so that the total output is equivalent
In a single stage analog to digital converter where the total output is equivalent,
s (j) is the weight of the j step in the single-stage analog-digital converter with equivalent total output, Sy (a) y ) For the a-th sub-converter of the y-th order y Step weight, step j in the single-stage analog-digital converter with equivalent total output corresponds to step a in the y-th sub-converter y Step, the h-th level sub-converter is Nh bit, y is 1 to X, j is 1 to M, the total output equivalent single-level analog-digital converter is M steps,
the arithmetic unit obtains a final output Dout according to the following relation:
the total output equivalent single-stage analog-digital converter is M steps, b [ i ] is the output of the ith bit, S (i) is the weight of the ith step, S (M) is the weight of the Mth step, S (0) represents the least significant bit of the equivalent single-stage analog-digital converter, all the sub-converters are successive approximation type converters, and each step of the sub-converters is realized by a comparison capacitor; an amplifier is connected in series between the adjacent sub-converters; correcting the capacitance mismatch of the total output equivalent single-stage analog-to-digital converter using a code density based correction algorithm.
2. The ADC of claim 1 wherein said sub-converter of level y is Ny bits, said sub-converter of level y has steps of My, where My > Ny ≧ 2, at least one subsequent step having a weight less than half the weight of the previous step to create redundancy in said sub-converter of level y, and y has a value from 1 to X.
3. An analog to digital converter as claimed in claim 1 or 2, characterized in that the sub-converter of the y-th stage comprises a main step lookup for determining that the sub-converter of the y-th stage is Ny bits, y being 1 to X.
4. An analog to digital converter as claimed in claim 3, characterized in that the main step search of at least one of said sub-converters comprises redundancy, and that the weight of at least one subsequent step is less than half the weight of the previous step.
5. The adc of claim 3, wherein at least one of said sub-converters of level z further comprises at least one additional look-up, said additional look-up being located after said main step look-up, in said sub-converter of level z, said main step look-up being used to determine the amplification of the weights in said sub-converter of level z-1, said additional look-up being used to increase the margin coverage of said sub-converter of level z, z being 2 to X, each of said additional look-ups being redundant.
6. An analog-to-digital conversion method comprising the steps of:
connecting X-level sub-converters in series, wherein at least part of the sub-converters have at least one redundancy, and X is more than or equal to 2; and
performing iterative shift addition on the outputs of all the sub-converters, performing left shift addition on the output of the previous sub-converter relative to the output of the next sub-converter in sequence, and obtaining a total output by the number of left-shifted bits equal to the number of steps of the next sub-converter
The final output Dout is obtained according to the following relation:
the total output equivalent single-stage analog-digital converter is N bits, the total output equivalent single-stage analog-digital converter is M steps, b [ i ] is the output of the ith bit, S (i) is the weight of the step corresponding to the ith bit, S (M) is the weight of the M step, and S (0) represents the least significant bit of the equivalent single-stage analog-digital converter;
the sub-converter of the y level is Ny-bit My step, the single-level analog-digital converter with equivalent total output is N-bit M step, y takes values from 1 to X, and then
In a single-stage analog-to-digital converter where the total output is equivalent,
s (j) is the weight of the j step in the single-stage analog-digital converter with equivalent total output, Sy (a) y ) For the a-th sub-converter of the y-th order y Step weight, step j in the single-stage analog-digital converter with equivalent total output corresponds to step a in the y-th sub-converter y Step, the h-th level sub-converter is an Nh bit, y takes values from 1 to X, j takes values from 1 to M, and the total output equivalent single-stage analog-digital converter is M steps;
all the sub-converters are successive approximation type converters, and each step of the sub-converters is realized by a comparison capacitor; an amplifier is connected in series between the adjacent sub-converters; correcting the capacitance mismatch of the total output equivalent single-stage analog-to-digital converter using a code density based correction algorithm.
7. The analog-to-digital conversion method of claim 6, wherein the y-th stage of said sub-converter comprises a main step lookup for determining that the y-th stage of said sub-converter is Ny bits, y taking a value from 1 to X; the main step search of at least one sub-converter comprises redundancy, and the weight of at least one next step is less than half of the weight of the previous step; at least one of the sub-converters of the z-th level further comprises at least one additional search, the additional search is located after the main step search, in the sub-converter of the z-th level, the main step search is used for determining the magnification factor of the weight in the sub-converter of the z-1 th level, the additional search is used for increasing the margin coverage of the sub-converter of the z-th level, the value of z is 2 to X, and each additional search is a redundancy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711282347.XA CN109905124B (en) | 2017-12-07 | 2017-12-07 | Analog-to-digital converter and analog-to-digital conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711282347.XA CN109905124B (en) | 2017-12-07 | 2017-12-07 | Analog-to-digital converter and analog-to-digital conversion method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109905124A CN109905124A (en) | 2019-06-18 |
| CN109905124B true CN109905124B (en) | 2022-09-30 |
Family
ID=66938998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711282347.XA Active CN109905124B (en) | 2017-12-07 | 2017-12-07 | Analog-to-digital converter and analog-to-digital conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109905124B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102684696A (en) * | 2011-03-10 | 2012-09-19 | 株式会社爱德万测试 | Test apparatus and test method for a/d converter |
| JP2013172296A (en) * | 2012-02-21 | 2013-09-02 | Renesas Electronics Corp | Successive approximation adc and method of testing successive approximation adc |
| CN106936434A (en) * | 2017-03-13 | 2017-07-07 | 中国电子科技集团公司第二十四研究所 | System is corrected based on the code density high-order harmonic wave that FFT is extracted |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60117827T2 (en) * | 2000-09-11 | 2006-11-23 | Broadcom Corp., Irvine | METHOD AND DEVICE FOR FORMING THE FEH-MATCHING OF A RECYCLED WALKER |
| DE102015116786A1 (en) * | 2015-10-02 | 2017-04-06 | Infineon Technologies Ag | Device method for testing an analog-to-digital converter |
-
2017
- 2017-12-07 CN CN201711282347.XA patent/CN109905124B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102684696A (en) * | 2011-03-10 | 2012-09-19 | 株式会社爱德万测试 | Test apparatus and test method for a/d converter |
| JP2013172296A (en) * | 2012-02-21 | 2013-09-02 | Renesas Electronics Corp | Successive approximation adc and method of testing successive approximation adc |
| CN106936434A (en) * | 2017-03-13 | 2017-07-07 | 中国电子科技集团公司第二十四研究所 | System is corrected based on the code density high-order harmonic wave that FFT is extracted |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109905124A (en) | 2019-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6563445B1 (en) | Self-calibration methods and structures for pipelined analog-to-digital converters | |
| JP4532808B2 (en) | Calibration of A / D converter | |
| US9397679B1 (en) | Circuit and method for DAC mismatch error detection and correction in an ADC | |
| US7999719B2 (en) | Multi-stage successive approximation register analog-to-digital converter and analog-to-digital converting method using the same | |
| JP4890561B2 (en) | Digital correction SAR converter including correction DAC | |
| US7978117B2 (en) | Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same | |
| US7893859B2 (en) | Converter circuit, analog/digital converter, and method for generating digital signals corresponding to analog signals | |
| US9059730B2 (en) | Pipelined successive approximation analog-to-digital converter | |
| KR100332243B1 (en) | Pipeline analog-to-digital converter vessel number 2 Architecture and calibration techniques | |
| US20130194115A1 (en) | Successive approximation register analog to digital converter | |
| EP3447921B1 (en) | Hybrid successive approximation register analog to digital converter | |
| US9813073B1 (en) | Sub-ranging SAR analog-to-digital converter with meta-stability detection and correction circuitry | |
| JP5869965B2 (en) | AD conversion circuit and AD conversion method | |
| EP2686960A1 (en) | Adc calibration | |
| US8570206B1 (en) | Multi-bit per cycle successive approximation register ADC | |
| JP2003298418A (en) | Analog/digital converter with automatic error calibration function | |
| US20100060494A1 (en) | Analog to Digital Converter | |
| US6791484B1 (en) | Method and apparatus of system offset calibration with overranging ADC | |
| TWI479806B (en) | Analog-to-digital converting system | |
| EP2760135A1 (en) | Analog/digital converter and method for converting analog signals to digital signals | |
| US20070120720A1 (en) | Analog-to-digital converter with non-linearity compensation | |
| US9252800B1 (en) | Enhanced resolution successive-approximation register analog-to-digital converter and method | |
| JP4526919B2 (en) | A / D converter | |
| CN109905124B (en) | Analog-to-digital converter and analog-to-digital conversion method | |
| JP3559534B2 (en) | Analog / digital conversion circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |