CN109904112B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN109904112B CN109904112B CN201711306943.7A CN201711306943A CN109904112B CN 109904112 B CN109904112 B CN 109904112B CN 201711306943 A CN201711306943 A CN 201711306943A CN 109904112 B CN109904112 B CN 109904112B
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Abstract
The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The method comprises the following steps: providing a substrate structure, the substrate structure comprising: a substrate; an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a trench extending to the substrate, the trench having a first spacer layer on sidewalls thereof, the trench having a first fin and a second fin spaced apart from each other therein, the first fin and the second fin having a gate dielectric layer on surfaces thereof; and a gate filling the trench, the gate including a first gate over the first fin for an NMOS device and a second gate over the second fin for a PMOS device; removing the part of the first spacer on the side wall of the second gate; forming a second spacer on a sidewall of the second gate; wherein the first spacer comprises a dielectric material having a dielectric constant less than 5 and the second spacer comprises a dielectric material having a dielectric constant greater than 10.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
As the critical dimensions of semiconductor devices decrease, fin field effect transistors (finfets) are increasingly being used in place of planar devices in integrated circuit manufacturing processes.
In finfets, the spacers for the gates are important. The spacer is related to the performance of the device such as leakage current, driving current and the like.
Disclosure of Invention
An object of the present application is to provide a semiconductor device and a method of manufacturing the same, which can achieve both performance of an NMOS device and performance of a PMOS device.
According to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, including: providing a substrate structure, the substrate structure comprising: a substrate; an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a trench extending to the substrate, the trench having a first spacer layer on sidewalls thereof, the trench having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on surfaces thereof; and a gate filling the trench, the gate including a first gate over the first fin for an NMOS device and a second gate over the second fin for a PMOS device; removing a portion of the first spacer on a sidewall of the second gate; forming a second spacer on a sidewall of the second gate; wherein the first spacer comprises a dielectric material having a dielectric constant less than 5 and the second spacer comprises a dielectric material having a dielectric constant greater than 10.
In one embodiment, the method further comprises: removing a part of the grid electrode through a back etching process to form a groove; and filling an insulating cap layer in the groove.
In one embodiment, the method further comprises: the remaining portions of the first spacers are removed to form air spacers for the first gates.
In one embodiment, the insulating cap layer comprises a nitride of silicon.
In one embodiment, the second spacers are formed by spin coating.
In one embodiment, the gate comprises a metal gate.
According to another aspect of the present application, there is provided a semiconductor device including: a substrate; an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a trench extending to the substrate, the trench having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on a surface thereof; and a gate filling the trench, the gate including a first gate for an NMOS device over the first fin and a second gate for a PMOS device over the second fin; a first spacer located between the first gate and a sidewall of the trench; a second spacer between the second gate and a sidewall of the trench; wherein the first spacer comprises a dielectric material having a dielectric constant less than 5 and the second spacer comprises a dielectric material having a dielectric constant greater than 10.
In one embodiment, the apparatus further comprises an insulating cap layer on the gate; the first spacer is also positioned between the insulating cap layer and the side wall of the groove, and the second spacer is also positioned between the insulating cap layer and the side wall of the groove.
In one embodiment, the insulating cap layer comprises a nitride of silicon.
In one embodiment, the gate comprises a metal gate.
According to still another aspect of the present application, there is provided a semiconductor device including: a substrate; an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a trench extending to the substrate, the trench having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on a surface thereof; and a gate filling the trench, the gate including a first gate for an NMOS device over the first fin and a second gate for a PMOS device over the second fin; an air spacer between the first gate and a sidewall of the trench; a second spacer between the second gate and a sidewall of the trench; wherein the second spacer comprises a dielectric material having a dielectric constant greater than 10.
In one embodiment, the apparatus further comprises an insulating cap layer on the gate; the air spacer is also positioned between the insulating cap layer and the side wall of the groove, and the second spacer is also positioned between the insulating cap layer and the side wall of the groove.
In one embodiment, the insulating cap layer comprises a nitride of silicon.
In one embodiment, the gate comprises a metal gate.
The manufacturing method of the embodiment of the application forms a first spacer with a dielectric constant less than 5 on the side wall of a first grid used for an NMOS device, and forms a second spacer with a dielectric constant more than 10 on the side wall of a second grid used for a PMOS device. The first spacer is beneficial to reducing the parasitic capacitance of the NMOS device, and the second spacer is beneficial to reducing the series resistance of the PMOS device and improving the driving current of the PMOS device.
Other features, aspects, and advantages of the present application will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description, serve to explain the principles of the application, and in which:
FIG. 1 is a simplified flow diagram of a method of fabricating a semiconductor device according to one embodiment of the present application;
FIG. 2A shows a schematic top view of a substrate structure according to one embodiment of the present application;
FIG. 2B shows a cross-sectional schematic view taken along B-B' shown in FIG. 2A;
FIG. 3A illustrates a schematic top view of a portion of a first spacer on a sidewall of a second gate removed according to one embodiment of the present application;
FIG. 3B shows a cross-sectional schematic view taken along B-B' shown in FIG. 3A;
FIG. 4A illustrates a schematic top view of forming a second spacer according to one embodiment of the present application;
FIG. 4B shows a cross-sectional schematic view taken along B-B' shown in FIG. 4A;
FIG. 5A shows a schematic top view of a stage in a method of manufacturing a semiconductor device according to another embodiment of the present application;
FIG. 5B shows a cross-sectional schematic view taken along B-B' shown in FIG. 5A;
FIG. 6A shows a schematic top view of a stage in a method of manufacturing a semiconductor device according to another embodiment of the present application;
FIG. 6B shows a cross-sectional schematic view taken along B-B' shown in FIG. 6A;
FIG. 7A shows a schematic top view of a stage in a method of manufacturing a semiconductor device according to another embodiment of the present application;
FIG. 7B shows a cross-sectional schematic view taken along B-B' shown in FIG. 7A.
Detailed Description
Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present application unless specifically stated otherwise.
Further, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual scale, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of exemplary embodiments is merely illustrative and is not intended to limit the application and its applications or uses in any way.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification as applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
Fig. 1 is a simplified flow diagram of a method of fabricating a semiconductor device according to one embodiment of the present application.
As shown in fig. 1, first, in step 102, a substrate structure is provided.
Fig. 2A shows a schematic top view of a substrate structure according to an embodiment of the present application. FIG. 2B shows a cross-sectional schematic view taken along B-B' shown in FIG. 2A.
Referring to fig. 2A and 2B, a substrate structure includes a substrate 201 and an interlayer dielectric layer 202 on the substrate 201.
The substrate 201 may be, for example, an elemental semiconductor substrate such as a silicon substrate or a germanium substrate, or a compound semiconductor substrate such as gallium arsenide. The interlayer dielectric layer 202 may be, for example, an oxide of silicon or the like.
The inter-level dielectric layer 202 has a trench 203 extending to the substrate 201. The trench 203 has a first spacer layer 204 on its sidewalls. Here, the first spacer 204 includes a dielectric material having a dielectric constant less than 5 (e.g., 2, 3, 4). The trench 203 has first and second fins spaced apart from each other with a gate dielectric layer, such as silicon oxide, on its surface. Note that fig. 2A and 2B do not show the first fin, the second fin, and the gate dielectric layer in order to highlight the importance of the present application.
The substrate structure further includes a gate 205, such as a metal gate, filling the trench 203. The gate 205 may include a first gate 215 over the first fin for an NMOS device and a second gate 225 over the second fin for a PMOS device. It is understood that the first gate 215 and the second gate 225 may be integrally provided. In one embodiment, the first fin and the second fin may be substantially parallel and the gate 205 may straddle both the first fin and the second fin.
Next, at step 104, the portion of the first spacer 204 on the sidewall of the second gate 225 is removed, as shown in fig. 3A and 3B.
Fig. 3A illustrates a schematic top view of a portion of a first spacer on a sidewall of a second gate removed according to one embodiment of the present application. FIG. 3B shows a cross-sectional schematic view taken along B-B' shown in FIG. 3A. After removing the portion of the first spacer 204 on the sidewall of the second gate 225, a gap is formed between the interlayer dielectric layer 202 and the second gate 225.
Thereafter, at step 106, second spacers 401 are formed on sidewalls of the second gate electrode 225 (i.e., in a gap between the interlayer dielectric layer 202 and the second gate electrode 225), as shown in fig. 4A and 4B.
Fig. 4A illustrates a schematic top view of forming a second spacer according to one embodiment of the present application. FIG. 4B shows a cross-sectional schematic view taken along B-B' shown in FIG. 4A.
Here, the second spacer 401 includes a dielectric material having a dielectric constant greater than 10 (e.g., 12, 14, 16, 20, etc.). Preferably, in order to avoid forming voids in the second spacers 401, the second spacers 401 may be formed by spin coating (spin on).
The manufacturing method of the present embodiment forms a first spacer on the sidewall of the first gate for the NMOS device and a second spacer on the sidewall of the second gate for the PMOS device. The first spacer is beneficial to reducing the parasitic capacitance of the NMOS device, and the second spacer is beneficial to reducing the series resistance of the PMOS device and improving the driving current of the PMOS device.
Fig. 5A-7B show schematic diagrams of stages of a method of manufacturing a semiconductor device according to another embodiment of the present application.
After the processes shown in fig. 2A-4B are performed, the processes shown in fig. 5A-7B may also be performed.
First, as shown in fig. 5A and 5B, a portion of the gate 205 may be removed by an etch-back process to form a recess 501.
Thereafter, as shown in fig. 6A and 6B, the recess 501 is filled with an insulating cap layer 601. The insulating cap layer 601 preferably comprises a nitride of silicon, such as silicon nitride or the like. The insulating cap layer 601 can prevent contact holes formed in the source region and the drain region from being connected to the gate 205, thereby better preventing the occurrence of short circuit.
Thereafter, as shown in fig. 7A and 7B, the remaining portion of the first spacer 204 may also be removed to form an air spacer 701 for the first gate 215. Air spacers 701 help to increase the drive current of the NMOS device.
The present application also provides a semiconductor device, referring to fig. 4A and 4B, including:
a substrate 201;
an interlayer dielectric layer 202 on the substrate 201, the interlayer dielectric layer 202 having a trench 203 extending to the substrate 201, the trench 203 having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on surfaces thereof; and
a gate 205 (e.g., a metal gate) filling the trench 203, the gate 205 including a first gate 215 over the first fin for an NMOS device and a second gate 225 over the second fin for a PMOS device;
a first spacer 204 positioned between the first gate 215 and a sidewall of the trench 203, the first spacer 204 comprising a dielectric material having a dielectric constant less than 5; and
a second spacer 401 located between the second gate 225 and the sidewall of the trench 203, the second spacer 401 comprising a dielectric material having a dielectric constant greater than 10.
In one embodiment, the semiconductor device may further include an insulating cap 601, such as silicon nitride, on the gate 205, as shown in fig. 6A and 6B. The first spacers 204 are also located between the insulating cap layer 601 and the sidewalls of the trench 203, and the second spacers 401 are also located between the insulating cap layer 601 and the sidewalls of the trench 203.
The present application also provides another semiconductor device, referring to fig. 7A and 7B, the semiconductor device including:
a substrate 201;
an interlayer dielectric layer 202 on the substrate 201, the interlayer dielectric layer having a trench 203 extending to the substrate 201, the trench 203 having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on surfaces thereof; and
a gate 205 (e.g., a metal gate) filling the trench 203, the gate 205 including a first gate 215 over the first fin for an NMOS device and a second gate 225 over the second fin for a PMOS device;
an air spacer 701 between the first gate 215 and the sidewall of the trench 203, the first spacer 204 comprising a dielectric material having a dielectric constant less than 5; and
a second spacer 401 positioned between the second gate 215 and the sidewall of the trench 203, the second spacer 401 comprising a dielectric material having a dielectric constant greater than 10.
In one embodiment, the semiconductor device may further include an insulating cap layer 601, such as silicon nitride, on the gate 205, as shown in fig. 7A and 7B. The first spacer 204 is also located between the insulating cap layer 601 and the sidewall of the trench 203, and the second spacer 401 is also located between the insulating cap layer 601 and the sidewall of the trench 203.
Thus far, the semiconductor device and the manufacturing method thereof according to the embodiment of the present application have been described in detail. Some details which are well known in the art have not been described in order to avoid obscuring the concepts of the present application, and it will be fully apparent to those skilled in the art from the above description how the technical solutions disclosed herein may be implemented. In addition, the embodiments taught by the present disclosure can be freely combined. It will be appreciated by persons skilled in the art that numerous modifications may be made to the embodiments described above without departing from the spirit and scope of the present application as defined by the appended claims.
Claims (14)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate structure, the substrate structure comprising:
a substrate;
an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a trench extending to the substrate, the trench having first spacers on sidewalls thereof, the trench having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on surfaces thereof; and
a gate filling the trench, the gate comprising a first gate over the first fin for an NMOS device and a second gate over the second fin for a PMOS device, wherein the first spacer comprises a portion on a sidewall of the first gate and a portion on a sidewall of the second gate abutting each other;
removing a portion of the first spacer on a sidewall of the second gate;
forming a second spacer on a sidewall of the second gate between the second gate and a sidewall of the trench;
wherein the first spacer comprises a dielectric material having a dielectric constant less than 5 and the second spacer comprises a dielectric material having a dielectric constant greater than 10.
2. The method of claim 1, further comprising:
removing a part of the grid electrode through a back etching process to form a groove;
and filling an insulating cap layer in the groove.
3. The method of claim 2, further comprising:
the remaining portions of the first spacers are removed to form air spacers for the first gates.
4. The method of claim 2, wherein the insulating cap layer comprises a nitride of silicon.
5. The method of claim 1, wherein the second spacers are formed by spin coating.
6. The method of claim 1,
the gate comprises a metal gate.
7. A semiconductor device, comprising:
a substrate;
an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a trench extending to the substrate, the trench having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on a surface thereof; and
a gate filling the trench, the gate including a first gate for an NMOS device over the first fin and a second gate for a PMOS device over the second fin;
a first spacer on a sidewall of the first gate and between the first gate and a sidewall of the trench;
a second spacer on a sidewall of the second gate and between the second gate and a sidewall of the trench;
wherein the first spacer comprises a dielectric material having a dielectric constant less than 5 and the second spacer comprises a dielectric material having a dielectric constant greater than 10.
8. The apparatus of claim 7, further comprising an insulating cap layer on the gate;
the first spacer is also positioned between the insulating cap layer and the side wall of the groove, and the second spacer is also positioned between the insulating cap layer and the side wall of the groove.
9. The apparatus of claim 8, wherein the insulating cap layer comprises a nitride of silicon.
10. The apparatus of claim 7,
the gate comprises a metal gate.
11. A semiconductor device, comprising:
a substrate;
an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a trench extending to the substrate, the trench having first and second fins spaced apart from each other therein, the first and second fins having a gate dielectric layer on a surface thereof; and
a gate filling the trench, the gate including a first gate for an NMOS device over the first fin and a second gate for a PMOS device over the second fin;
an air spacer between the first gate and a sidewall of the trench;
a second spacer on a sidewall of the second gate and between the second gate and a sidewall of the trench;
wherein the second spacer comprises a dielectric material having a dielectric constant greater than 10.
12. The apparatus of claim 11, further comprising an insulating cap layer on the gate;
the air spacer is also positioned between the insulating cap layer and the side wall of the groove, and the second spacer is also positioned between the insulating cap layer and the side wall of the groove.
13. The apparatus of claim 12, wherein the insulating cap layer comprises a nitride of silicon.
14. The apparatus of claim 11,
the gate comprises a metal gate.
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| CN102110651A (en) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102214609A (en) * | 2010-04-07 | 2011-10-12 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102456691A (en) * | 2010-10-29 | 2012-05-16 | 索尼公司 | Semiconductor device and manufacturing method of semiconductor device |
| CN103456736A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN103996711A (en) * | 2013-01-24 | 2014-08-20 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
| CN106981485A (en) * | 2015-10-08 | 2017-07-25 | 三星电子株式会社 | Semiconductor devices and the phase inverter with the semiconductor devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4671614B2 (en) * | 2004-03-03 | 2011-04-20 | パナソニック株式会社 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110651A (en) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102214609A (en) * | 2010-04-07 | 2011-10-12 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102456691A (en) * | 2010-10-29 | 2012-05-16 | 索尼公司 | Semiconductor device and manufacturing method of semiconductor device |
| CN105448835A (en) * | 2010-10-29 | 2016-03-30 | 索尼公司 | Semiconductor device |
| CN103456736A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN103996711A (en) * | 2013-01-24 | 2014-08-20 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
| CN106981485A (en) * | 2015-10-08 | 2017-07-25 | 三星电子株式会社 | Semiconductor devices and the phase inverter with the semiconductor devices |
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