CN109889834B - CABAC arithmetic decoding method and device - Google Patents
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Abstract
The invention discloses a CABAC arithmetic decoding method and a device, wherein the method comprises a loading step of loading context information from a context storage medium; an updating step, namely analyzing the loaded context information by using a syntax element and caching a context information updating value in the syntax element analyzing process; a write-back step of writing back the context update value to a context storage medium; the three steps of loading, updating and writing back realize the complete CABAC arithmetic decoding process in a pipeline mode, so that the loading step, the updating step and the writing back step have no mutual dependence of calculation paths. The CABAC arithmetic decoding method provided by the invention divides the original closed loop of context information acquisition and updating into three parts of context information loading, context information updating and context information writing back, effectively cuts off the closed loop of context information acquisition and updating, can effectively reduce the calculation path in the CABAC arithmetic decoding process, and obviously improves the circuit performance of CABAC arithmetic decoding.
Description
Technical Field
The invention relates to a decoding technology, in particular to a CABAC arithmetic decoding method and a CABAC arithmetic decoding device.
Background
H.264 introduced Context-Adaptive Binary Arithmetic Coding (CABAC) technology. Compared with variable length coding, because of the full utilization of the correlation of the syntax elements, partial information of the syntax elements is hidden in the neighborhood information of the syntax elements and can be derived according to the correlation rule in the decoding process, CABAC has higher compression rate. However, the method has the disadvantages of complex algorithm, more calculation logic and complex hardware circuit implementation. The context index generation, the bin value analysis, the context information update and other calculation iteration levels are more, and frequent interaction with a storage medium exists in the CABAC arithmetic decoding process, as shown in fig. 1-2, a closed loop of context information acquisition and update is formed in the interaction process, and due to the factors, the performance of a hardware circuit is difficult to improve.
Disclosure of Invention
An aspect of the present invention is to provide a CABAC arithmetic decoding method to reduce a computation path in a CABAC arithmetic decoding process and improve a circuit performance of CABAC arithmetic decoding.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a CABAC arithmetic decoding method comprises
A loading step of loading context information from a context storage medium;
an updating step, namely analyzing the loaded context information by using a syntax element and caching a context information updating value in the syntax element analyzing process;
a write-back step of writing back the context update value to a context storage medium;
the three steps of loading, updating and writing back realize the complete CABAC arithmetic decoding process by using a pipeline mode, so that the loading step, the updating step and the writing back step have no mutual dependence of a calculation path.
Furthermore, the pipeline mode comprises two stages of pipelines, the first stage of pipeline is a loading step, and the second stage of pipeline comprises an updating step and a write-back step; the loading of the context information is independent of the updating and the writing back of the context information, and the context information exists in a pipeline stage independently and is a first-stage pipeline; the write back of the context information is interspersed in the process of updating the context information and is a second-level pipeline.
Further, the loading step comprises loading context information from a context storage medium according to requirements in the parsing process of the syntax elements and caching the context information in a first register set;
the updating step comprises the steps of using the context information of the first register group to analyze the syntax element, setting a context information updating value of a second register group cache syntax element analyzing process, and feeding back the context information updating value of the second register group to the first register group;
the write back step includes writing back to the context storage medium directly using the context information update value of the first register set.
Further, the loading context information includes predicting context information to be loaded at a next stage, and completing the transfer from the context storage medium to the first register set.
Further, the predicting the next stage includes predicting the syntax elements to be parsed in the next stage before the syntax element parsing starts and during the syntax element parsing.
Further, the first register set includes a first register subset of the first register set and a second register subset of the first register set, and the first register subset of the first register set and the second register subset of the first register set store the context information in a ping-pong manner.
Further, the second register set comprises a second register set first register subset and a second register set second register subset; the first register subset of the second register set is used for caching the context information from the first register set; the second register subset of the second register set is used for caching context information update values of the syntax element parsing process, and the cached context information update values are used as context information sources for the bin value parsing in the partial syntax elements.
Further, for some syntax elements with the current bin value possibly equal to the upper and lower indexes corresponding to the next adjacent second bin value, the parsing of the bin value is suspended for one period after the parsing of the current bin value, and the suspended one period is used for writing the context information update value of the second register subset of the second register set into the first register set.
Another aspect of the present invention is to provide a CABAC arithmetic decoding apparatus including a first register and a second register group; wherein the content of the first and second substances,
the first register group is used for caching the context information loaded from the context storage medium according to requirements in the parsing process of the syntax elements;
the second register group is used for caching context information updating values in a syntax element analysis process and feeding back the context information updating values to the first register group;
the first register set is further configured to write the context information update value back to the context storage medium.
Compared with the prior art, the invention has the beneficial effects that:
the CABAC arithmetic decoding method provided by the invention divides the original closed loop of context information acquisition and updating into three parts of context information loading, context information updating and context information writing back, effectively cuts off the closed loop of context information acquisition and updating, can effectively reduce the calculation path in the CABAC arithmetic decoding process, and obviously improves the circuit performance of CABAC arithmetic decoding.
Drawings
FIG. 1 is a CABAC entropy decoding framework;
FIG. 2 is a closed loop of context information acquisition and update in the prior art;
fig. 3 is a block diagram of a CABAC arithmetic decoding structure;
FIG. 4 is a CABAC arithmetic decoding pipeline structure;
FIG. 5 is a block diagram of a context information loading structure;
FIG. 6 is a block diagram of a context information update structure;
fig. 7 is a block diagram of a context information write-back structure.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Example 1:
the CABAC arithmetic decoding method provided by the embodiment comprises
A loading step of loading context information from a context storage medium;
an updating step, namely analyzing the loaded context information by using a syntax element and caching a context information updating value in the syntax element analyzing process;
a write-back step of writing back the context update value to a context storage medium;
the three steps of loading, updating and writing back realize the complete CABAC arithmetic decoding process by using a pipeline mode, so that the loading step, the updating step and the writing back step have no mutual dependence of a calculation path.
Therefore, the present embodiment provides a CABAC arithmetic decoding method, which cuts off a context information acquisition and update closed loop by performing parsing on context information loading, context information updating, and context information writing back in a pipeline manner, and through the parsing, a computation path involved in a CABAC arithmetic decoding process is effectively reduced, and compared with a hardware circuit of a conventional CABAC arithmetic decoding, the CABAC arithmetic decoding method has a higher comprehensive frequency when decoding a single bin value and a multi-bin value, and can obtain a higher decoding performance.
As a preferred embodiment of the present invention, the pipeline manner includes two stages of pipelines, the first stage of pipeline is a loading step, and the second stage of pipeline includes an updating step and a write-back step; that is, the loading of the context information is independent of the updating and writing back of the context information, and exists in a pipeline stage independently, and is a first-stage pipeline; the write back of the context information is interspersed in the process of updating the context information and is a second-level pipeline. The context information is updated to a main time consuming module of CABAC arithmetic decoding, the time for reading and writing the context is short by using a context storage medium with high bit width, the write-back of the updated value of the context information is carried out at the interval of the updating process of the context information, and even if a single-port SRAM is used as the context information storage medium, the avoidance of the read-write conflict of the single-port SRAM is simple.
Specifically, the loading step includes loading context information from a context storage medium according to requirements in a syntax element parsing process and caching the context information in a first register set; the updating step comprises the steps of using the context information of the first register group to analyze the syntax element, setting a context information updating value of a cache syntax element analyzing process of a second register group, and feeding back the context information updating value of the second register group to the first register group; the write back step includes writing back to the context storage medium directly using the context information update value of the first register set. That is to say, as another preferred embodiment of the present invention, the method caches the updated value of the context information by increasing the register set in the context information updating stage, so as to further shorten the calculation path during updating the context information.
As still another preferred embodiment, the loading context information includes context information predicted to be loaded in the next stage, and the transfer from the context storage medium to the first register set is completed. Therefore, the context information is loaded in advance in the CABAC arithmetic decoding process, and the continuous supply of the context information is ensured, so that the arithmetic decoding is carried out continuously. Specifically, the predicting the next stage includes predicting the syntax elements to be parsed in the next stage before the syntax element parsing starts and during the syntax element parsing.
As still another preferred embodiment of the present invention, the first register set includes a first register subset of the first register set and a second register subset of the first register set, and the first register subset of the first register set and the second register subset of the first register set store the context information in a ping-pong manner. Therefore, the ping-pong storage of the context information in the first register set avoids the conflict of loading, updating and writing back of the context information, and the ping-pong operation is the guarantee of the pipeline processing of the invention.
Further, the second register set includes a second register set first register subset and a second register set second register subset; the first register subset of the second register set is used for caching the context information from the first register set; the second register subset of the second register set is used for caching context information update values of the syntax element parsing process, and the cached context information update values are used as context information sources for the bin value parsing in the partial syntax elements. Thus, the second register subset of the second register set is used as a context information source for the bin value analysis in the partial syntax element, so that two consecutive bin values using the same context information index for the bin value analysis can be correctly decoded without affecting the delayed updating of the context
Furthermore, for some parts, there are special syntax elements such as coded _ block _ pattern, rem _ intraNxN _ pred _ mode, and significant _ coeff _ flag that the upper and lower indexes of the current bin value corresponding to the next adjacent second bin value may be equal, the parsing of the bin value is suspended for one period after the parsing of the current bin value, and the suspended one period is used for writing the context information update value of the second register subset of the second register set into the first register set.
That is to say, the special syntax elements such as coded _ block _ pattern, rem _ intraNxN _ pred _ mode, significant _ coeff _ flag, etc. have the possibility that two bin values may use the same context information to perform bin value analysis, and the pause time is an effective time period, so that the context information update value is correctly transmitted to the next adjacent second bin value for use, thereby ensuring the correct analysis of the bin value when the context information of the 1 st and 3 rd bin values in relative sequence is the same
Example 2:
referring to fig. 3, fig. 3 is a block diagram of the CABAC arithmetic decoding apparatus according to the present embodiment, and includes a first register set 102 and a second register set 103. In particular, the context information storage medium 101 stores context information and provides an information source for arithmetic decoding; the first register set 102 loads context information from a context storage medium in batches according to actual requirements, screens corresponding context information according to a syntax element analysis state and outputs the context information for analyzing a syntax element bin value, context information update values in a bin value update process are cached in the second register set 103, and in a context information update stage, the context information update values are fed back to the first register set 102 through the second register set 103 through time sequence adjustment of an internal circuit; when the currently screened context information is used up, the first register set 102 initiates a write-back operation to write back the context information update value to the context storage medium 101.
Referring to fig. 4, for the CABAC arithmetic decoding structure shown in fig. 3, a hardware architecture setting is performed in a two-stage pipeline manner. The first-level pipeline is a loading step, and in the CABAC arithmetic decoding process, context information to be loaded at the next stage is predicted according to the syntax element analysis state, and the transfer of the context information from the context storage medium to the first register set 102 is completed. The first-level pipeline also sequentially orders the context information corresponding to each syntax element in the context information loading process as described above, and transfers the ordered information to the second-level pipeline for use. The second-level pipeline executes the steps of updating and writing back the context information, analyzes the syntax element by obtaining the context information of the first register set 102, calculates the context information updating value and caches the context information updating value in the second register set 103, updates the context information updating value of the second register set 103 to the first register set 102 every time one syntax element is analyzed, and writes back the context information updating value from the first register set 102 to the context storage medium 101 if the current type syntax element is analyzed.
Referring to fig. 5, fig. 5 is a block diagram of a context information loading structure, which corresponds to the first stage pipeline shown in fig. 4, to implement loading from a context storage medium to the first register set 102. Before the syntax element parsing starts and during the syntax element parsing, context information to be loaded is predicted, and accordingly, a read data application is issued to the context storage medium, and the first register set 102 completes reception of the read context information. Predicting, i.e. predicting, syntax elements to be parsed in the next stage, for example, before parsing syntax elements starts, syntax element context information of slice data categories is loaded to the first register set 102, and macroblock level category syntax elements are loaded to the first register set 102 during parsing of slice data category syntax elements. For the syntax elements to be pre-determined and loaded, the present embodiment sequentially indexes and sorts the syntax elements according to the parsing order of the syntax elements in the region specified by the h.264, and transmits the sorting information to the context information updating stage. The context information is loaded to the first register set 102 for use, so that the retrieval range of the context information at the context information updating stage is reduced, and the overall calculation path of the context updating is greatly reduced.
To implement the pipeline hardware implementation manner described in this embodiment, the first register group 102 needs to be split into a first register subset of the first register group and a second register subset of the first register group, and context information is cached and written back in a ping-pong manner.
Referring to fig. 6, fig. 6 is a block diagram of a context information updating structure in the second level pipeline stage of the embodiment. The context information selection 301 indexes the corresponding context information in the first register set 102 according to the parsed syntax element in the syntax element parsing process, and the indexed context information is used for parsing after being registered. Since the context information loading stage reduces the index range of the context information, and the context information retrieved from the first register bank is cached in the first register subset of the second register bank 103 and then used for subsequent analysis, the calculation path of the context information update is further isolated from the context information write-back related to arithmetic decoding, and the circuit has higher comprehensive frequency and better performance. Context information updating 302, which is to use the context information cached in the first register subset of the second register set to perform syntax element bin value analysis, calculate an updated value of the context information in the analysis process, and immediately cache the updated value of the context information to the second register subset of the second register set after the context updated value is calculated;
for the analysis of two adjacent bin values with the same context index, the context information corresponding to the latter bin value is already stored in the second register subset of the second register set, at this time, the context information of the second register subset of the second register set is used for analyzing the bin value, and the context information updated in the process is also cached to the second register subset of the second register set.
For some special syntax elements, such as coded _ block _ pattern, rem _ intraNxN _ pred _ mode, significant _ coeff _ flag, etc., where the upper and lower indices corresponding to the current bin value and the next adjacent second bin value may be equal, since there is a delay of one cycle when the second register set 103 updates to the first register set 102, the context information is screened out from the first register set 102 according to the conventional process for analyzing the next adjacent second bin value, a situation that the updated context information cannot be obtained in time occurs, and thus the bin value analysis fails. For the syntax elements of this category, the analysis of the bin value is suspended for one period after the current bin value is analyzed, the suspended period is used for writing the context information update value of the second register subset of the second register set into the first register set 102, the analysis of the subsequent bin value is continuously started after the suspension period is ended, and the first register set 102 can be restarted to acquire correct context information when the analysis of the subsequent second bin value of the current bin value is ended, so that the correct analysis of the bin value is ensured. Because the coded _ block _ pattern and the rem _ intraNxN _ pred _ mode contain a small number of bin values, and the bin values related to the significant _ coeff _ flag are scattered, the influence of the strategy for pausing the arithmetic decoding on the CABAC arithmetic decoding performance is small and can be ignored. And the method is simple to realize and is beneficial to the realization of the whole hardware circuit.
From the above, the computation path of the context update is: starting point (second register set first register subset or second register set second register subset) -arithmetic decoding combinational logic-ending point (second register set second register subset), the calculation path does not involve interaction of the context storage medium 101, the calculation path is relatively short, in CABAC arithmetic decoding scheme supporting 1 or more bin value parsing per cycle, higher comprehensive frequency can be obtained, and the calculation performance can be higher.
The context update value cache 303 realizes that context update values of a second register subset of a second register set are written back to a first register set, the process is triggered once after a single bin value of each syntax element is analyzed, the calculation logic only relates to selection of a corresponding writing position of the first register set, and a selection mark signal is registered and output by a context information updating 302 stage, the calculation path is extremely short, and the overall performance of CABAC arithmetic decoding is not influenced.
Referring to fig. 7, fig. 7 is a block diagram of a context information write-back structure according to this embodiment, and the flow corresponds to the second-level pipeline stage shown in fig. 4. The updated context information 401 refers to a context updated value cached in the first register subset of the first register set or the second register subset of the first register set, a preparation signal for triggering the context information to be written back to the storage medium 402 is triggered every time all bin values of one syntax element are analyzed, the number of the context information currently written back to the storage medium is recorded and accumulated when the preparation signal arrives, a command for writing back the context information is issued when the number of the context information to be written back to the storage medium reaches a set threshold value, and a handshake module is arranged between the context information storage medium 101 and the first register set 102 to receive the command and complete the write back of the corresponding context information.
Of course, the invention is not limited to the implementation of the above examples, and any modifications introduced by the person skilled in the art to the proposed method shall also be within the scope of protection of the invention. Likewise, the present invention is not limited to the h.264 standard, and other standards for CABAC arithmetic decoding in the h.264 mode are also applicable to the present invention.
Claims (9)
1. A CABAC arithmetic decoding method, comprising
A loading step of loading context information from a context storage medium;
an updating step, namely analyzing the loaded context information by using a syntax element and caching a context information updating value in the syntax element analyzing process;
a write-back step of writing back the context update value to a context storage medium;
the three steps of loading, updating and writing back realize the complete CABAC arithmetic decoding process by using a pipeline mode, so that the loading step, the updating step and the writing back step have no mutual dependence of a calculation path;
the loading step comprises loading context information from a context storage medium according to requirements in the parsing process of the syntax elements and caching the context information in a first register group;
the updating step comprises the steps of using the context information of the first register group to analyze the syntax element, setting a context information updating value of a second register group cache syntax element analyzing process, and feeding back the context information updating value of the second register group to the first register group;
the write back step includes writing back to the context storage medium directly using the context information update value of the first register set.
2. The CABAC arithmetic decoding method of claim 1, wherein the pipeline includes two stages of pipeline, a first stage of pipeline being a load step, a second stage of pipeline including an update step and a write-back step; the loading of the context information is independent of the updating and the writing back of the context information, and the context information exists in a pipeline stage independently and is a first-stage pipeline; the write back of the context information is interspersed in the process of updating the context information and is a second-level pipeline.
3. The CABAC arithmetic decoding method of claim 1, wherein the loading the context information includes predicting context information to be loaded at a next stage and completing its transfer from the context storage medium to the first register group.
4. The CABAC arithmetic decoding method of claim 3, wherein the predicting the next stage comprises predicting syntax elements to be parsed by the corresponding next stage in the syntax element parsing process before the syntax element parsing starts.
5. The CABAC arithmetic decoding method of claim 1, wherein the first register set includes a first register set first register subset and a first register set second register subset, the first register set first register subset and the first register set second register subset storing the context information in a ping-pong manner.
6. The CABAC arithmetic decoding method of claim 1, wherein the second register group includes a second register group first register subset and a second register group second register subset; the first register subset of the second register set is used for caching the context information from the first register set; the second register subset of the second register set is used for caching context information update values of the syntax element parsing process, and the cached context information update values are used as context information sources for the bin value parsing in the partial syntax elements.
7. The CABAC arithmetic decoding method of claim 6, wherein for a portion of syntax elements for which there is a current bin value equal to an upper and lower index corresponding to a next immediately adjacent second bin value, the current bin value parsing is followed by a pause of one cycle of bin value parsing, the pause of one cycle being used to write context information update values of the second subset of registers of the second register set into the first register set.
8. A CABAC arithmetic decoding apparatus comprising a first register and a second register group; wherein the content of the first and second substances,
the first register group is used for caching the context information loaded from the context storage medium according to requirements in the parsing process of the syntax elements;
the second register group is used for caching context information updating values in a syntax element analysis process and feeding back the context information updating values to the first register group;
the first register set is further configured to write the context information update value back to the context storage medium.
9. The CABAC arithmetic decoding apparatus of claim 8, wherein the first register set includes a first register set first register subset and a first register set second register subset, the first register set first register subset and the first register set second register subset storing the context information in a ping-pong manner;
the second register bank comprises a second register bank first register subset and a second register bank second register subset; the first register subset of the second register set is used for caching the context information from the first register set; the second register subset of the second register set is used for caching context information update values of the syntax element parsing process, and the cached context information update values are used as context information sources for the bin value parsing in the partial syntax elements.
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