CN109874062B

CN109874062B - Intelligent ODF frame for efficiently collecting optical wiring and alarming states

Info

Publication number: CN109874062B
Application number: CN201910211424.5A
Authority: CN
Inventors: 缪爱林; 徐国庆; 郝亮; 汤俊勇; 李莉华
Original assignee: Zhongtian Broadband Technology Co Ltd
Current assignee: Zhongtian Broadband Technology Co Ltd
Priority date: 2019-03-20
Filing date: 2019-03-20
Publication date: 2023-10-27
Anticipated expiration: 2039-03-20
Also published as: CN109874062A

Abstract

The invention discloses an intelligent ODF (optical distribution frame) for efficiently collecting optical wires and alarm states, which comprises an intelligent MODF (optical distribution frame) disk manager, an intelligent MODF frame manager and an intelligent MODF frame manager, wherein the intelligent MODF disk manager is connected with the intelligent MODF frame manager, the intelligent MODF frame manager is connected with the intelligent MODF frame manager, and the intelligent MODF frame manager is connected with an intelligent ODF management system. The invention solves the problems of low speed of acquiring resource information and long delay of abnormal operation alarming of the existing intelligent ODF frame, and greatly improves the intelligent level and expandability.

Description

Intelligent ODF frame for efficiently collecting optical wiring and alarming states

Technical Field

The invention relates to an intelligent ODF frame, in particular to an intelligent ODF frame for efficiently collecting optical wiring and alarm states.

Background

As the demand for broadband services by users increases and the cost of FTTH (Fiber To The Home ) terminals decreases, FTTH has gradually moved into the daily lives of users. The development of FTTH will promote the on-line business to develop towards the exploration degree and the breadth, and will also change the life style of the user, and improve the communication quality of the user. The 0DN (0ptica1 Distribution Network, optical distribution network) is taken as an important link in the construction of the FTTH, and has data display that the proportion of the 0DN to the sum of the investment of the FTTH is 50-70%, so that the comprehensive construction cost of the FTTH can be directly influenced. Meanwhile, the 0DN belongs to an infrastructure pipeline and is a bearing channel for FTTH data transmission, so that the quality of the 0DN construction is also about the system performance, the reliability and the upgrading potential of the FTTH. However, the existing ODN system has different problems in construction, such as large management difficulty, disordered field fiber-skipping construction, difficult maintenance of tag information, high maintenance cost and the like, and the intelligent 0DN has been developed to solve the same problems.

At present, the intelligent ODN management system is still in a stage of artificial management for a large number of alarms generated by equipment, namely the intelligent 0DN equipment generates alarms, the equipment uploads the generated alarms to the intelligent 0DN management system through SNMP (Simple Network Management Protoco1, network management protocol), a manager discovers the alarms and searches for reasons, a processing scheme is formulated, and constructors are assigned to perform construction maintenance. The method for processing the alarms has low efficiency, long time consumption for fault restoration, more artificial influence factors and uncertain processing schemes, and can cause greater and greater difficulty and workload of network operation and maintenance and higher maintenance cost along with the continuous increase of the number and complexity of the alarms.

The intelligent ODF (optical distribution frame) realizes the detection of the fiber inserting state through integrating an electronic tag (eID), an intelligent frame manager and an intelligent disk manager on the basis of the traditional ODF, acquires whether the fiber inserting position is correct, and can realize the functions of site construction guidance, abnormal state warning and the like through interaction with an information system. However, in the existing intelligent ODF scheme, the disc managers only exist as an eID reading head mode with multiple ports, and all the disc managers of the ODF are connected with the rack manager through buses to realize interconnection and intercommunication. And a 0DF rack is usually large in fiber distribution quantity, taking 576 cores with fewer configurations as an example, 96 disk managers are needed by using 6 cores of disk managers, and the quantity of bus devices is large, so that the defects of communication efficiency reduction, untimely alarm and low operation speed are caused.

In summary, the prior art mainly has the following drawbacks:

1. bus type communication mode, and the node quantity is great, the communication efficiency is low, the speed is slow;

2. the intelligent degree of the disk manager is not high, if the eID and the position correspond correctly, the eID is issued after the frame management judgment, the reaction speed is low, and the site construction and the abnormal alarm are not facilitated;

3. the acquisition of the fiber distribution resources takes a long time and cannot realize the real-time update of the resource information.

Disclosure of Invention

The invention aims to solve the technical problem of providing an intelligent ODF frame for efficiently collecting optical wiring and alarm states and improving communication efficiency.

In order to solve the technical problems, the invention adopts the following technical scheme:

an intelligent ODF rack for efficiently collecting optical wiring and alarm states, which is characterized in that: the intelligent MODF disk management system comprises an intelligent MODF disk manager, an intelligent MODF frame manager and an intelligent MODF frame manager, wherein the intelligent MODF disk manager is connected with the intelligent MODF frame manager, the intelligent MODF frame manager is connected with the intelligent MODF frame manager, and the intelligent MODF frame manager is connected with an intelligent ODF management system;

the intelligent MODF disk manager collects, stores and uploads eID tag information, monitors port state change, issues instructions or configures corresponding LED states according to an intelligent ODF management system, and reads and rewrites port electronic tag information;

The intelligent MODF frame manager realizes the management and control of the intelligent MODF disk manager by taking a frame as a unit, the intelligent MODF frame manager communicates with the rack manager through a serial interface in the uplink direction, the corresponding disk manager port is intelligently gated according to the requirement of the rack manager, the intercommunication between the rack manager and the appointed disk manager is realized, when the downlink intelligent MODF disk manager has an alarm event, the uplink rack manager is informed to timely handle the alarm event of the downlink equipment by setting a specific hardware pin, an instruction of the uplink rack manager is received, and the specific alarm position is cleared;

the intelligent MODF frame manager collects, stores and forwards eID tag information, port information, disk information and frame information to the intelligent ODF management system, and forwards an instruction or configuration issued by the intelligent ODF management system to the disk manager.

Further, the intelligent MODF disk manager comprises a 6-way electronic tag interface circuit, a disk manager status light circuit, a disk manager master control circuit, a disk manager program burning port circuit, a disk manager data storage unit circuit and a disk manager program debugging serial port circuit, wherein the 6-way electronic tag interface circuit, the disk manager status light circuit, the disk manager program burning port circuit, the disk manager data storage unit circuit and the disk manager program debugging serial port circuit are respectively connected with the disk manager master control circuit.

Further, the master control circuit of the disc manager comprises an STM32F103CBT6 chip U1, pins 1, 9, 36 and 48 of the U1 are connected with a 3.3V power supply, pin 7 of the U1 is connected with one end of a resistor R3 and one end of a capacitor C7, the other end of the resistor R3 is connected with the 3.3V power supply, the other end of the capacitor C7 is grounded, pins 8, 23, 35, 44 and 47 of the U1 are grounded, pin 5 of the U1 is connected with one end of a crystal oscillator tube XTAL1 and one end of a capacitor C8, pin 6 of the U1 is connected with the other end of the crystal oscillator tube XTAL1 and one end of a capacitor C9, and the other end of the capacitor C8 and the other end of the capacitor C9 are grounded; the electronic tag interface circuit comprises an interface P_1, wherein pins 1 and 4 of the interface P_1 are grounded, pins 2 and 3 of the interface P_1 are connected with one end of a resistor R15 and the cathode of a diode D4, the other end of the resistor R15 is connected with a 3.3V power supply, and the anode of the diode D4 is grounded; the disk manager status light circuit comprises a resistor R4, one end of the resistor R4 is connected with a 3.3V power supply, the other end of the resistor R4 is connected with the anode of a light emitting diode LED1, the cathode of the light emitting diode LED1 is connected with a pin 45 of U1, the anodes of the light emitting diodes LED_1, LED_2, LED_3, LED_4, LED_5 and LED_6 are connected with the 3.3V power supply, the cathodes of the light emitting diodes LED_1, LED_2, LED_3, LED_4, LED_5 and LED_6 are respectively connected with one end of a resistor R17, one end of a resistor R21, one end of a resistor R25, one end of a resistor R27, one end of a resistor R31 and one end of a resistor R33, the other end of the resistor R17, the other end of the resistor R21, the other end of the resistor R25, the other end of the resistor R27, the other end of the resistor R31 and the other end of the resistor R33 are respectively connected with pins 33, 29, 27, 17, 19 and 21 of the pin 21 of U1.

Further, the programming interface circuit of the disc manager program comprises a programming interface P1, wherein a pin 1 of the programming interface P1 is connected with one end of a resistor R1 and is connected with a 3.3V power supply, a pin 2 of the programming interface P1 is connected with the other end of the resistor 1 and a pin 34 of U1, a pin 3 of the programming interface P1 is connected with one end of a resistor R2 and a pin 37 of U1, and the other end of the resistor R2 is grounded; the disk manager data storage unit circuit comprises a 24C04 chip U2, pins 1, 2, 3 and 4 of the U2 are grounded, pin 5 of the U2 is connected with one end of a resistor R6 and pin 43 of the U1, pin 6 of the U2 is connected with one end of a resistor R7 and pin 42 of the U1, the other end of the resistor R6 and the other end of the resistor R7 are connected with a 3.3V power supply, pin 7 of the U2 is connected with one end of a capacitor C10 and grounded, and pin 8 of the U2 is connected with the other end of the capacitor C10 and the 3.3V power supply; the serial port debugging circuit of the disk manager program comprises a serial port P2, a pin 1 of the serial port P2 is connected with a pin 31 of U1, a pin 2 of the serial port P2 is connected with a pin 30, and a pin 3 of the serial port P2 is grounded.

Further, the intelligent MODF frame manager comprises 12 RJ45 interface circuits, a frame manager main control circuit, a frame manager program burning port circuit, a frame manager data storage unit, a logic control switch circuit, a frame manager program debugging serial port circuit, a frame manager uplink communication port circuit and a frame manager power supply circuit, wherein the 12 RJ45 interface circuits, the frame manager program burning port circuit, the frame manager data storage unit, the logic control switch circuit, the frame manager program debugging serial port circuit, the frame manager uplink communication port circuit and the frame manager power supply circuit are respectively connected with the frame manager main control circuit.

Further, the master control circuit of the frame manager comprises an STM32F103 chip U3, pins 1, 64, 13, 19, 32 and 48 of the U3 are connected with a 3.3V power supply, pins 31, 47, 12, 63 and 60 of the U3 are grounded, pin 7 of the U3 is connected with one end of a resistor R5 and one end of a capacitor C17, the other end of the resistor R5 is connected with the 3.3V power supply, and the other end of the capacitor C17 is grounded; the RJ45 interface circuit comprises an RJ45 interface P_2, pins 7, 8, 11 and 12 of the RJ45 interface P_2 are grounded, pin 1 of the RJ45 interface P_2 is connected with one end of a resistor R33, pin 2 of the RJ45 interface P_2 is connected with one end of a resistor R31, the other end of the resistor R33 is connected with the cathode of a diode D7, the other end of the resistor R31 is connected with the cathode of a diode D6, the anode of the diode D7 and the anode of the diode D6 are grounded, pin 3 of the RJ45 interface P_2 is connected with one end of a resistor R25, pin 51 of U3 and the cathode of a diode D4, pins 4 and 5 of the RJ45 interface P_2 are connected with a 5V power supply, pin 6 of the RJ45 interface P_2 is connected with one end of a resistor R29, the other end of the resistor R29 is connected with one end of a resistor R21 and one end of a resistor R23, the other end of the resistor R21 is connected with pin 1 of a BC817 chip Q2, pin 2 of the other end of the resistor R23 is grounded, pin 3 of the chip Q2 is connected with one end of a resistor R24 and pin 35 of U3, and the other end of the resistor R25 is connected with 3.3V power supply; the frame manager program programming port circuit comprises a programming port P3, wherein a 1 pin of the programming port P3 is connected with one end of a resistor R13 and a 3.3V power supply, a 2 pin of the programming port P3 is connected with the other end of the resistor R13 and a 46 pin of U3, a 3 pin of the programming port P3 is connected with one end of a resistor R14 and a 49 pin of U3, and the other end of the resistor R14 is grounded; the frame manager data storage unit comprises a 24C08 chip U4, pins 1, 2, 3 and 4 of the U4 are grounded, pin 5 of the U4 is connected with one end of a resistor R16 and pin 59 of the U3, pin 6 of the U4 is connected with one end of a resistor R17 and pin 58 of the U3, the other end of the resistor R16 and the other end of the resistor R17 are connected with a 3.3V power supply, pin 7 of the U4 is connected with one end of a capacitor C18 and grounded, and pin 8 of the U4 is connected with the other end of the capacitor C18 and the 3.3V power supply; the logic control switch circuit comprises a CD74HC4067M chip U5 and U6, wherein the 1 pin of the U5 is connected with the 17 pin of the U3, the 17 pin of the U5 is connected with the other end of a resistor R31, the 17 pin of the U6 is connected with the other end of the resistor R33, the 18-22 pin and the 3-8 pin of the U5 and the U6 are respectively connected with the rest 11 paths of RJ45 interface circuits, the 10 pin, the 11 pin, the 14 pin and the 13 pin of the U5 and the U6 are respectively connected with the 20-23 pin of the U3, the 12 pin and the 15 pin of the U5 and the U6 are grounded, the 24 pin of the U5 is connected with one end of a capacitor C11 and a 3.3V power supply, the other end of the capacitor C11 is grounded, the 24 pin of the U6 is connected with one end of a capacitor C12 and the 3.3V power supply, the other end of the capacitor C12 is grounded, and the 9 pin of the U6 is connected with the 16 pin of the U3; the serial port circuit for debugging the frame manager program comprises a serial port P4, pins 1 and 2 of the serial port P4 are respectively connected with pins 43 and 42, and pin 3 of the serial port P4 is grounded.

Further, the frame manager uplink communication port circuit comprises an RJ45 interface P5, a 1 pin of P5 is connected with one end of a resistor R9, a 2 pin of P5 is connected with one end of a resistor R8, the other end of the resistor R9 is connected with a cathode of a diode D2 and a 1 pin of U6, the other end of the resistor R8 is connected with a cathode of a diode D3 and a 1 pin of U5, an anode of the diode D2 and an anode of the diode D3 are grounded, a 3 pin of P5 is connected with a cathode of the diode D1 and a 3 pin of a BC817 chip Q1, an anode of the diode D1 and a 2 pin of Q1 are grounded, a 1 pin of Q1 is connected with a 14 pin of U3, 4, 5 and 6 pins of P5 are connected with one end of a capacitor C13 and a 5V power supply, 7 pins of P5 are connected with the other end of the capacitor C13 and are grounded, and 11 pins 12 of P5 are grounded; the frame manager power supply circuit comprises an NI/TPS62160 chip U7, pins 1 and 4 of the U7 are grounded, pins 2 and 3 of the U7 are connected with TP1, one end of a capacitor C16, one end of a capacitor C15, one end of a resistor R13, 3 pins of an AP7361C-33DR chip U8, the other end of the capacitor C15 and the other end of the capacitor C16 are grounded, the other end of the resistor R13 is connected with a 5V power supply, one end of the resistor R18 and one end of the resistor R17 are connected with the other end of the resistor R18, the other end of the resistor R18 is grounded, the other end of the 6 pin of the U7 is connected with the other end of the resistor R17, one end of an inductor L1, one end of the resistor R14, one end of the capacitor C17, one end of the TP1, one end of the capacitor C18, one end of the resistor R15 and 2 pins of U8, the pin 7 of the pin of the U7 is connected with the other end of the resistor R14, the other end of the capacitor C17 and the other end of the capacitor C18 are connected with TP3 and grounded, the other end of the resistor R15 is connected with 3.3V power supply, and the pin 1 of U8 is grounded.

Further, the intelligent MODF rack manager comprises a rack manager main control circuit, a 12-way rack manager interface circuit, an Ethernet interface circuit, a reset circuit, an alarm circuit, a USB interface circuit, a latch circuit, a power supply conversion circuit and a TTL interface expansion application circuit.

Further, the rack manager main control circuit comprises an MC-A5D3X chip M1A, M B, wherein the 10 pin of the M1A is connected with one end of a resistor R21, the 12 pin of the M1A is connected with one end of a resistor R22, the 94, 96, 93, 95, 7 and 23 of the M1A are grounded, the 97-100 pin of the M1A is connected with one end of a capacitor C1, one end of a capacitor C2 and one end of a capacitor C37 and is connected with a 3.3V power supply, the other end of the capacitor C1, the other end of the capacitor C2 and the other end of the capacitor C37 are grounded, and the 33, 34, 67 and 68 pins of the M1B are grounded; the shelf manager interface circuit comprises RJ45 interface P4A, 1 pin of P4A is connected with one end of a resistor R36, 2 pin of P4A is connected with one end of a resistor R34, the other end of the resistor R36 is connected with a cathode of a diode D6, the other end of the resistor R34 is connected with a cathode of a diode D5, an anode of the diode D6 and an anode of the diode D5 are grounded, 3 pin of P4A is connected with one end of a resistor R28, a cathode of the diode D3 and a pin of M1B, an anode of the diode D3 is grounded, 6 pin of P4A is connected with one end of a resistor R32, the other end of the resistor R32 is connected with one end of a resistor R24 and one end of a resistor R26, the other end of the resistor R24 is connected with 1 pin of a BC817 chip Q4, the other end of the resistor R26 and the 2 pin of Q4 are grounded, the 3 pin of Q4 is connected with the 66 pin of M1B and one end of a resistor R27, the other end of the resistor R27 and the other end of the resistor R28 are connected with a 3.3V power supply, the 3 pin of a DMP2130L field effect transistor Q11 is connected with one end of a resistor R67 and a 5V power supply, the 2 pin of Q11 is connected with one end of a fuse F2, the other end of the fuse F2 is connected with V_OUT1, the 1 pin of Q11 is connected with the other end of the resistor R67 and one end of the resistor R69, the other end of the resistor R69 is connected with the 3 pin of a BC817 chip Q13, the 2 pin of Q13 is grounded, the 1 pin of Q13 is connected with one end of a resistor R73, the other end of the resistor R73 is connected with one end of the resistor R71 and the 98 pin of M1B, and the other end of the resistor R71 is connected with the 3.3V power supply; the ethernet interface circuit comprises a HR911105a chip U9, pin 1 of U9 is connected to pin 2 of M1A, resistor R168 is connected to pin 2 of U9, pin 1 of M1A is connected to resistor R169, resistor R168 is connected to the other end of resistor R169 to one end of capacitor C27, the other end of capacitor C27 is grounded, pins 4 and 5 of U9 are connected to one end of capacitor C44, one end of capacitor C45 and one end of inductor L3, the other end of capacitor C44 and the other end of capacitor C45 are grounded, pin 8 of M1A is connected to the other end of inductor L3, pin 3 of U9 is connected to pin 4 of M1A, one end of resistor R170, pin 6 of U9 is connected to pin 3 of M1A, one end of resistor R171 is connected to the other end of resistor R170 and one end of resistor R171, pin 9 is connected to one end of resistor C28, pin 9 of resistor C172 is grounded, pin 12 of U9 is connected to one end of resistor R173, and pin 10 and 11 of U9 are connected to pins 3.3v, 6 and 5 of M1A, respectively.

Further, the reset circuit comprises an SP706SEN chip U10, pins 1 and 8 of the U10 are connected with one end of a resistor R174, one end of a capacitor C29 and pin 1 of a contact switch K1, the other end of the resistor R174 is connected with a 3.3V power supply, pins 2, 3 and 4 of the capacitor C29 and K1 are grounded, pin 2 of the U10 is connected with one end of a capacitor C30 and a 3.3V power supply, and pins 3 and 4 of the U10 are connected with the other end of the capacitor C30 and grounded; the alarm circuit comprises a buzzer P9, wherein a pin 1 of the P9 is connected with a cathode of a diode D41 and one end of a resistor R178, the other end of the resistor R178 is connected with one end of a capacitor C3 and a 3.3V power supply, the other end of the capacitor C3 is grounded, a pin 2 of the P9 is connected with an anode of the diode D41 and a pin 3 of a BC817 triode Q40, a pin 2 of the Q40 is grounded, a pin 1 of the Q40 is connected with one end of a resistor R181, the other end of the resistor R181 is connected with a pin 35 of a M1B, a pin 1 of a contact switch K2 is connected with one end of a capacitor R177, one end of the capacitor C31 and a pin 39 of the M1B, the other end of the resistor R177 is connected with a 3.3V power supply, and the other ends of the capacitor C31 are grounded; the USB interface circuit comprises a USB interface P10, wherein a pin 1 of the P10 is connected with one end of a fuse F17, one end of a capacitor C32, a cathode of a diode D44, one end of a capacitor C33 and a 5V power supply, the other end of the fuse F17 is connected with 5VD, the other end of the capacitor C32 and the other end of the capacitor C33 are grounded, a pin 2 of the P10 is connected with a cathode of a diode D43 and one end of a resistor R179, the other end of the resistor R179 is connected with a pin 28 of an M1A, a pin 3 of the P10 is connected with a cathode of the diode D42 and one end of a resistor R180, the other end of the resistor R180 is connected with a pin 27 of the M1A, anodes of the diodes D42, D43 and D44 are grounded, and pins 5-9 of the P10 are grounded; the latch circuit comprises an SN74HCT125D chip U11, wherein a pin 1 of the U11 is connected with one end of a resistor R12 and a pin 74 of an M1A, the other end of the resistor R12 is connected with a 3.3V power supply, a pin 2 of the U11 is connected with a pin 72 of the M1A, pins 4, 10 and 13 of the U11 are connected with one end of a resistor R13, the other end of the resistor R13 is connected with a 3.3V power supply, pins 7, 5, 9 and 12 of the U11 are grounded, a pin 14 of the U11 is connected with one end of a capacitor C48 and the 3.3V power supply, and the other end of the capacitor C48 is grounded; the power conversion circuit comprises a WR-MPC4 chip P7, a pin 1 and a pin 2 are connected with a pin 4 of a rectifier bridge D39, a pin 3 and a pin 4 of P7 are connected with a pin 2 of the rectifier bridge D39, a pin 1 of the rectifier bridge D39 is connected with one end of a resistor R132, one end of a capacitor C17, one end of a capacitor C18 and a pin 1 of a WD30-48S05 chip PM1, a pin 3 of the rectifier bridge D39 is connected with the other end of the resistor R132, the other end of the capacitor C17, the other end of the capacitor C18, one end of a capacitor CY2 and a pin 2 of PM1, the other end of the capacitor CY2 is grounded, a pin 5 of PM1 is connected with one end of a capacitor C19 and is grounded, a pin 6 of PM1 is connected with the other end of the capacitor C19, the other end of the diode D46 and the anode of D49 are connected with the cathode of the diode D46, the cathode of the diode D49 is connected with the cathode of the diode D47, the cathode of the D50, one end of the fuse F8 and 5VCCIN, the anode of the diode D47 and the anode of the diode D50 are connected with the 3, 4 AO of the chip P8 of NI/WR-MPC4 chip P8, the pin 1 is grounded, the other end of the fuse F8 is connected with the pin 5, the anode of the diode P21 is grounded, the negative electrode of the capacitor C21 is grounded, the other end of the fuse F10 is connected with the 2 pin of the power chip U12, one end of the resistor R135, one end of the capacitor C24 and +5VD, the 8 pin of the U12 is connected with the other end of the resistor R135, the other end of the capacitor C24 is grounded, the 1, 4 and 6 pins of the U12 are grounded, the 3 pin of the U12 is connected with one end of the inductor L2, the other end of the inductor L2 is connected with the 5 pin of the U12, one end of the resistor R136, one end of the capacitor C25, one end of the capacitor C26 and 3.3V power supply, the other ends of the capacitors C25 and C26 are grounded, the 7 pin of the U12 is connected with the other end of the resistor R136 and one end of the resistor R138, the other end of the resistor R138 is grounded, the other end of the fuse F9 is connected with the 2 pin of the NI/ACT4070BYH chip U13, the 1 pin of the U13 is connected with one end of the capacitor C20, the other end of the capacitor C20 is connected with the 3 pin of the U13, one end of the inductor L1 and the cathode of the diode D40, the other end of the inductor L1, the other end of the capacitor 47 and the capacitor, one end of the capacitor C22 and +5VD, the other end of the resistor R133 and the other end of the capacitor C47 are connected with one end of the resistor R134 and the 5 pin of the U13, and the other end of the resistor R134, the anode of the diode D40 and the other end of the capacitor C22 are grounded; the TTL interface expansion application circuit comprises a CH438Q chip U14, a 1 pin of the U14 is connected with one end of a resistor R188, the other end of the resistor R188 is connected with an 80 pin of an M1A, a 2 pin of the U14 is connected with one end of a capacitor C39 and one end of a capacitor C40 and is connected with a 3.3V power supply, a 3 pin of the U14 is connected with the other end of the capacitor C39 and the other end of the capacitor C40 and is grounded, 4-10 of the U14 is respectively connected with 48, 50, 52, 54, 56, 58 and 60 pins of the M1A, a 32 pin of the U14 is connected with one end of a resistor R187 and 21 pin of the M1A, the other end of the resistor R187 is connected with a 3.3V power supply, a 33 pin of the U14 is connected with one end of a resistor R183, one end of a resistor C36 is connected with the other end of the resistor R183, the other end of the resistor C36 is grounded, the other end of the resistor R184 is connected with 9 pin of the M1A, 34-41 pins of the U14 are respectively connected with 79, 77, 75, 73, 71, 69, 67 and 65 pins of the U14 are respectively connected with the other end of the resistor C1A, the U14 is grounded at 42 pins, the U14 is connected with one end of a resistor R186, the other end of the resistor R186 is connected with the pin 76 of M1A, the U14 is connected with one end of a resistor R185, the other end of the resistor R185 is connected with the pin 81 of M1A, the U15 is connected with one ends of 1, 4, 10 and 13 pins of a SN74HCT125D chip U15, the U15 is connected with the pin 68 of M1A, the U15 is connected with the pin 9 of M1A, the U15 is connected with the pin 11 of M1A, the U15 is connected with one end 59 of M1A, the resistor R163, the U15 is connected with the pin 8 of R164, the U15 is connected with the pin 62 of M1A and the resistor R165, the U15 is connected with the pin 3 of R166, the U15 is connected with the pins 14 of R163, R164, R165, the R166 of R166 and 3.3V power supply, and the other end of the capacitor C46 is grounded.

Compared with the prior art, the invention has the following advantages and effects: the invention realizes the communication efficiency between the rack manager and the disk manager by the instruction gating of the designated disk manager channel and then the instruction implementation without depending on buses; the problem that the existing intelligent ODF frame is low in resource information acquisition speed and long in abnormal operation alarming delay is solved; the intelligent level and the expandability are greatly improved; the real-time abnormal alarm and dynamic resource state updating functions are optimized.

Drawings

Fig. 1 is a block diagram of an intelligent ODF rack for efficiently collecting optical wiring and alarm states according to the present invention.

Fig. 2 is a circuit diagram of a disk manager master circuit of the present invention.

Fig. 3 is a circuit diagram of an electronic label interface circuit, a disk manager status light circuit, and a disk manager program burn-in circuit of the present invention.

Fig. 4 is a circuit diagram of a disk manager data storage unit circuit and a disk manager program debug serial circuit of the present invention.

Fig. 5 is a circuit diagram of a block manager master circuit of the present invention.

Fig. 6 is a circuit diagram of an RJ45 interface circuit, a box manager program burn-in circuit, and a box manager data storage unit of the present invention.

Fig. 7 is a circuit diagram of a logic controlled switching circuit of the present invention.

Fig. 8 is a circuit diagram of a box manager program debug serial port circuit, a box manager upstream communication port circuit, and a box manager power supply circuit of the present invention.

Fig. 9 is a circuit diagram of a shelf manager master circuit of the present invention.

Fig. 10 is a circuit diagram of a shelf manager interface circuit and an ethernet interface circuit of the present invention.

Fig. 11 is a circuit diagram of a reset circuit, an alarm circuit, a USB interface circuit, and a latch circuit of the present invention.

Fig. 12 is a circuit diagram of the power conversion circuit of the present invention.

Fig. 13 is a circuit diagram of a TTL interface extension application circuit of the present invention.

Detailed Description

The present invention will be described in further detail by way of examples, which are illustrative of the present invention and are not intended to limit the present invention thereto.

As shown in the figure, the intelligent ODF frame for efficiently collecting optical wiring and alarm states comprises an intelligent MODF disk manager, an intelligent MODF frame manager and an intelligent MODF frame manager, wherein the intelligent MODF disk manager is connected with the intelligent MODF frame manager, the intelligent MODF frame manager is connected with the intelligent MODF frame manager, and the intelligent MODF frame manager is connected with an intelligent ODF management system;

the intelligent MODF disk manager mainly collects, stores and uploads eID tag information, monitors port state change, and sends instructions or configuration instructions according to an intelligent ODF management system to correspond to the LED state, and the disk manager reads and rewrites port electronic tag information (downlink I1 interfaces, total 12 paths of ports; uplink adopts serial ports to aggregate through a frame manager).

The functions include:

1. acquiring tag information and monitoring port states through a single bus interface (I1), and reading eID data by 1-wire;

2. writing tag information on the electronic tag carrier in a controlled state, and writing eID data in 1-wire;

3. analyzing the issued work order data (port configuration data);

4. positioning or guiding the port position in a LED lighting mode, and enabling the LED to be in the following states: normally bright, normally off, slow flashing, fast flashing;

5. the tag information is cached.

The intelligent MODF frame manager mainly realizes the management and control of the disk manager by taking the frame as a unit, the frame manager is communicated with the rack manager through a serial interface in the uplink, and the corresponding port of the disk manager is intelligently gated according to the requirement of the rack manager, so that the intercommunication between the rack manager and the appointed disk manager is realized. When the downlink disc manager has an alarm event, the uplink frame manager is informed of timely disposing the alarm event of the downlink equipment by setting a specific hardware pin, an instruction of the uplink frame manager is received, and a specific alarm position bit is cleared.

The frame manager has two versions, corresponding to 12 discs/frames (12-mouth frame manager) and 16 discs/frames (16-mouth frame manager), respectively, and the structural design is adjusted according to the requirements of the middle-day structure.

The functions include:

1. communicate with the shelf manager through a serial interface;

2. realizing the management of the on-line state and frame basic information of the disk manager;

3. selecting serial port passages of a rack manager and a disk manager;

4. the gating frame manager itself realizes the on-line state and basic information management of the frame manager;

5. the notification shelf manager processes the alert event.

The intelligent MODF frame manager mainly collects, stores and forwards eID tag information, port information, disk information and frame information to the intelligent ODF management system, and forwards an instruction or configuration issued by the intelligent ODF management system to the disk manager; for the offline rack manager, the collected and cached data can be sent to the intelligent ODN management terminal (I2 interface) through communication between the RS485 port and the intelligent ODN management terminal.

The functions include:

1. the intelligent management terminal is communicated with the intelligent management terminal through an RS-485 interface (I2);

2. communicating (on-line) with the intelligent ODN management system via an ethernet interface (I3);

3. the serial interface is communicated with the frame/disk manager, and 6/12 ports are totally arranged, and each port is connected with one frame manager;

4. the support adopts a power socket terminal, and a single DC48V power supply is used for supplying power (in an on-line mode);

5. The PoE-like power supply mode (RJ 45 supplies DC12V and realizes serial communication) is supported;

6. buzzer+LED alarms, can press keys to intercept bell;

7. the serial port alarm information is output and communicated with other alarm devices of the rack;

8. and the external alarm control port controls the on-off of one path of external alarm equipment through a relay (dry node).

The intelligent MODF disk manager comprises a 6-way electronic tag interface circuit, a disk manager status light circuit, a disk manager master control circuit, a disk manager program burning port circuit, a disk manager data storage unit circuit and a disk manager program debugging serial port circuit, wherein the 6-way electronic tag interface circuit, the disk manager status light circuit, the disk manager program burning port circuit, the disk manager data storage unit circuit and the disk manager program debugging serial port circuit are respectively connected with the disk manager master control circuit.

The disk manager main control circuit comprises STM32F103CBT6 chips U1, 9, 36 and 48 pins of U1 are connected with a 3.3V power supply, 7 pins of U1 are connected with one end of a resistor R3 and one end of a capacitor C7, the other end of the resistor R3 is connected with the 3.3V power supply, the other end of the capacitor C7 is grounded, 8, 23, 35, 44 and 47 pins of U1 are grounded, 5 pins of U1 are connected with one end of a crystal oscillator tube XTAL1 and one end of a capacitor C8, 6 pins of U1 are connected with the other end of the crystal oscillator tube XTAL1 and one end of a capacitor C9, and the other end of the capacitor C8 and the other end of the capacitor C9 are grounded; the electronic tag interface circuit comprises an interface P_1, wherein pins 1 and 4 of the interface P_1 are grounded, pins 2 and 3 of the interface P_1 are connected with one end of a resistor R15 and the cathode of a diode D4, the other end of the resistor R15 is connected with a 3.3V power supply, and the anode of the diode D4 is grounded; the disk manager status light circuit comprises a resistor R4, one end of the resistor R4 is connected with a 3.3V power supply, the other end of the resistor R4 is connected with the anode of a light emitting diode LED1, the cathode of the light emitting diode LED1 is connected with a pin 45 of U1, the anodes of the light emitting diodes LED_1, LED_2, LED_3, LED_4, LED_5 and LED_6 are connected with the 3.3V power supply, the cathodes of the light emitting diodes LED_1, LED_2, LED_3, LED_4, LED_5 and LED_6 are respectively connected with one end of a resistor R17, one end of a resistor R21, one end of a resistor R25, one end of a resistor R27, one end of a resistor R31 and one end of a resistor R33, the other end of the resistor R17, the other end of the resistor R21, the other end of the resistor R25, the other end of the resistor R27, the other end of the resistor R31 and the other end of the resistor R33 are respectively connected with pins 33, 29, 27, 17, 19 and 21 of the pin 21 of U1.

The programming interface circuit of the disk manager comprises a programming interface P1, wherein a pin 1 of the programming interface P1 is connected with one end of a resistor R1 and is connected with a 3.3V power supply, a pin 2 of the programming interface P1 is connected with the other end of the resistor 1 and a pin 34 of U1, a pin 3 of the programming interface P1 is connected with one end of a resistor R2 and a pin 37 of U1, and the other end of the resistor R2 is grounded; the disk manager data storage unit circuit comprises a 24C04 chip U2, pins 1, 2, 3 and 4 of the U2 are grounded, pin 5 of the U2 is connected with one end of a resistor R6 and pin 43 of the U1, pin 6 of the U2 is connected with one end of a resistor R7 and pin 42 of the U1, the other end of the resistor R6 and the other end of the resistor R7 are connected with a 3.3V power supply, pin 7 of the U2 is connected with one end of a capacitor C10 and grounded, and pin 8 of the U2 is connected with the other end of the capacitor C10 and the 3.3V power supply; the serial port debugging circuit of the disk manager program comprises a serial port P2, a pin 1 of the serial port P2 is connected with a pin 31 of U1, a pin 2 of the serial port P2 is connected with a pin 30, and a pin 3 of the serial port P2 is grounded.

The intelligent MODF frame manager comprises 12 RJ45 interface circuits, a frame manager main control circuit, a frame manager program burning port circuit, a frame manager data storage unit, a logic control switch circuit, a frame manager program debugging serial port circuit, a frame manager uplink communication port circuit and a frame manager power supply circuit, wherein the 12 RJ45 interface circuits, the frame manager program burning port circuit, the frame manager data storage unit, the logic control switch circuit, the frame manager program debugging serial port circuit, the frame manager uplink communication port circuit and the frame manager power supply circuit are respectively connected with the frame manager main control circuit.

The main control circuit of the frame manager comprises an STM32F103 chip U3, pins 1, 64, 13, 19, 32 and 48 of the U3 are connected with a 3.3V power supply, pins 31, 47, 12, 63 and 60 of the U3 are grounded, pin 7 of the U3 is connected with one end of a resistor R5 and one end of a capacitor C17, the other end of the resistor R5 is connected with the 3.3V power supply, and the other end of the capacitor C17 is grounded; the 12-path RJ45 interface circuit supports electrical functions such as downstream power supply, TTL serial port, alarm (Alarm), connection Confirmation (CC) and the like, taking one path as an example, the RJ45 interface circuit comprises an RJ45 interface P_2, pins 7, 8, 11 and 12 of the RJ45 interface P_2 are grounded, pin 1 of the RJ45 interface P_2 is connected with one end of a resistor R33, pin 2 of the RJ45 interface P_2 is connected with one end of a resistor R31, the other end of the resistor R33 is connected with a cathode of a diode D7, the other end of the resistor R31 is connected with a cathode of a diode D6, an anode of the diode D7 is grounded, pin 3 of the RJ45 interface P_2 is connected with one end of a resistor R25, pin 51 of a diode D4, pins 4 and 5 of the RJ45 interface P_2 are connected with a 5V power supply, pin 6 of the RJ45 interface P_2 is connected with one end of a resistor R29, the other end of the resistor R29 is connected with one end of a resistor R21 and one end of a resistor R23, the other end of the resistor R21 is connected with pin 1 of a chip Q2 of a BC817, pin 2 of the other end of the chip Q2 is connected with the other end of the resistor R23, and the other end of the chip Q2 is connected with the other end of the resistor R3 and the resistor R3 is connected with the other end of the resistor 3; the frame manager program programming port circuit comprises a programming port P3, wherein a 1-pin of the programming port P3 is connected with one end of a resistor R13 and a 3.3V power supply, a 2-pin of the programming port P3 is connected with the other end of the resistor R13 and a 46 pin of U3, a 3-pin of the programming port P3 is connected with one end of a resistor R14 and a 49 pin of U3, the other end of the resistor R14 is grounded, and a 12-channel downlink output port power supply output enabling circuit can respectively control whether each port supplies power to a downlink disk manager. The frame manager data storage unit comprises a 24C08 chip U4, pins 1, 2, 3 and 4 of the U4 are grounded, pin 5 of the U4 is connected with one end of a resistor R16 and pin 59 of the U3, pin 6 of the U4 is connected with one end of a resistor R17 and pin 58 of the U3, the other end of the resistor R16 and the other end of the resistor R17 are connected with a 3.3V power supply, pin 7 of the U4 is connected with one end of a capacitor C18 and grounded, and pin 8 of the U4 is connected with the other end of the capacitor C18 and the 3.3V power supply; the logic control switch circuit comprises a CD74HC4067M chip U5 and U6, wherein the 1 pin of the U5 is connected with the 17 pin of the U3, the 17 pin of the U5 is connected with the other end of a resistor R31, the 17 pin of the U6 is connected with the other end of the resistor R33, the 18-22 pin and the 3-8 pin of the U5 and the U6 are respectively connected with the rest 11 paths of RJ45 interface circuits, the 10 pin, the 11 pin, the 14 pin and the 13 pin of the U5 and the U6 are respectively connected with the 20-23 pin of the U3, the 12 pin and the 15 pin of the U5 and the U6 are grounded, the 24 pin of the U5 is connected with one end of a capacitor C11 and a 3.3V power supply, the other end of the capacitor C11 is grounded, the 24 pin of the U6 is connected with one end of a capacitor C12 and the 3.3V power supply, the other end of the capacitor C12 is grounded, and the 9 pin of the U6 is connected with the 16 pin of the U3; the serial port circuit for debugging the frame manager program comprises a serial port P4, pins 1 and 2 of the serial port P4 are respectively connected with pins 43 and 42, and pin 3 of the serial port P4 is grounded.

The frame manager uplink communication port circuit comprises RJ45 interfaces P5, 1 pin of P5 is connected with one end of a resistor R9, 2 pins of P5 are connected with one end of a resistor R8, the other end of the resistor R9 is connected with the cathode of a diode D2 and 1 pin of U6, the other end of the resistor R8 is connected with the cathode of a diode D3 and 1 pin of U5, the anode of the diode D2 and the anode of the diode D3 are grounded, 3 pins of P5 are connected with the cathode of the diode D1 and 3 pin of a BC817 chip Q1, the anode of the diode D1 and 2 pin of Q1 are grounded, 1 pin of Q1 is connected with 14 pin of U3, 4, 5 and 6 pins of P5 are connected with one end of a capacitor C13 and 5V power supply, 7 and 8 pins of P5 are connected with the other end of the capacitor C13 and are grounded, and 11 and 12 pins of P5 are grounded; the frame manager power supply circuit comprises an NI/TPS62160 chip U7, pins 1 and 4 of the U7 are grounded, pins 2 and 3 of the U7 are connected with TP1, one end of a capacitor C16, one end of a capacitor C15, one end of a resistor R13, 3 pins of an AP7361C-33DR chip U8, the other end of the capacitor C15 and the other end of the capacitor C16 are grounded, the other end of the resistor R13 is connected with a 5V power supply, one end of the resistor R18 and one end of the resistor R17 are connected with the other end of the resistor R18, the other end of the resistor R18 is grounded, the other end of the 6 pin of the U7 is connected with the other end of the resistor R17, one end of an inductor L1, one end of the resistor R14, one end of the capacitor C17, one end of the TP1, one end of the capacitor C18, one end of the resistor R15 and 2 pins of U8, the pin 7 of the pin of the U7 is connected with the other end of the resistor R14, the other end of the capacitor C17 and the other end of the capacitor C18 are connected with TP3 and grounded, the other end of the resistor R15 is connected with 3.3V power supply, and the pin 1 of U8 is grounded.

The intelligent MODF rack manager comprises a rack manager main control circuit, a 12-channel rack manager interface circuit, an Ethernet interface circuit, a reset circuit, an alarm circuit, a USB interface circuit, a latch circuit, a power conversion circuit and a TTL interface expansion application circuit. The 12-path rack manager interface circuit, the Ethernet interface circuit, the reset circuit, the alarm circuit, the USB interface circuit, the latch circuit, the power conversion circuit and the TTL interface expansion application circuit are respectively connected with the rack manager main control circuit. The 12-path rack manager interface circuit has the functions of 5V power supply output, TTL serial port, frame access level detection (CC) and frame alarm signal detection (alarm). The reset circuit is used for resetting the master control unit of the rack manager, the alarm circuit generates alarm sound when an alarm event occurs, and K2 is used for clearing the alarm sound by touching the switch. The USB interface circuit is used for debugging and burning the MPU module program; the latch circuit prevents the influence of the signal initialization process on the control signal at power-up. The power supply conversion circuit converts external DC48V voltage into 5V voltage and 3.3V voltage required by the system, and the TTL interface expansion application circuit expands 8 paths of serial ports to make up for the deficiency of serial ports of the MPU module.

The master control circuit of the rack manager comprises an MC-A5D3X chip M1A, M B, wherein the 10 pin of the M1A is connected with one end of a resistor R21, the 12 pin of the M1A is connected with one end of a resistor R22, the 94, 96, 93, 95, 7 and 23 pins of the M1A are grounded, the 97-100 pin of the M1A is connected with one end of a capacitor C1, one end of a capacitor C2 and one end of a capacitor C37 and is connected with a 3.3V power supply, the other end of the capacitor C1, the other end of the capacitor C2 and the other end of the capacitor C37 are grounded, and the 33, 34, 67 and 68 pins of the M1B are grounded; the shelf manager interface circuit comprises RJ45 interface P4A, 1 pin of P4A is connected with one end of a resistor R36, 2 pin of P4A is connected with one end of a resistor R34, the other end of the resistor R36 is connected with a cathode of a diode D6, the other end of the resistor R34 is connected with a cathode of a diode D5, an anode of the diode D6 and an anode of the diode D5 are grounded, 3 pin of P4A is connected with one end of a resistor R28, a cathode of the diode D3 and a pin of M1B, an anode of the diode D3 is grounded, 6 pin of P4A is connected with one end of a resistor R32, the other end of the resistor R32 is connected with one end of a resistor R24 and one end of a resistor R26, the other end of the resistor R24 is connected with 1 pin of a BC817 chip Q4, the other end of the resistor R26 and the 2 pin of Q4 are grounded, the 3 pin of Q4 is connected with the 66 pin of M1B and one end of a resistor R27, the other end of the resistor R27 and the other end of the resistor R28 are connected with a 3.3V power supply, the 3 pin of a DMP2130L field effect transistor Q11 is connected with one end of a resistor R67 and a 5V power supply, the 2 pin of Q11 is connected with one end of a fuse F2, the other end of the fuse F2 is connected with V_OUT1, the 1 pin of Q11 is connected with the other end of the resistor R67 and one end of the resistor R69, the other end of the resistor R69 is connected with the 3 pin of a BC817 chip Q13, the 2 pin of Q13 is grounded, the 1 pin of Q13 is connected with one end of a resistor R73, the other end of the resistor R73 is connected with one end of the resistor R71 and the 98 pin of M1B, and the other end of the resistor R71 is connected with the 3.3V power supply; the ethernet interface circuit comprises a HR911105a chip U9, pin 1 of U9 is connected to pin 2 of M1A, resistor R168 is connected to pin 2 of U9, pin 1 of M1A is connected to resistor R169, resistor R168 is connected to the other end of resistor R169 to one end of capacitor C27, the other end of capacitor C27 is grounded, pins 4 and 5 of U9 are connected to one end of capacitor C44, one end of capacitor C45 and one end of inductor L3, the other end of capacitor C44 and the other end of capacitor C45 are grounded, pin 8 of M1A is connected to the other end of inductor L3, pin 3 of U9 is connected to pin 4 of M1A, one end of resistor R170, pin 6 of U9 is connected to pin 3 of M1A, one end of resistor R171 is connected to the other end of resistor R170 and one end of resistor R171, pin 9 is connected to one end of resistor C28, pin 9 of resistor C172 is grounded, pin 12 of U9 is connected to one end of resistor R173, and pin 10 and 11 of U9 are connected to pins 3.3v, 6 and 5 of M1A, respectively.

The reset circuit comprises an SP706SEN chip U10, wherein pins 1 and 8 of the U10 are connected with one end of a resistor R174, one end of a capacitor C29 and a pin 1 of a contact switch K1, the other end of the resistor R174 is connected with a 3.3V power supply, the other end of the capacitor C29 is grounded with pins 2, 3 and 4 of the K1, the pin 2 of the U10 is connected with one end of a capacitor C30 and a 3.3V power supply, and the pins 3 and 4 of the U10 are connected with the other end of the capacitor C30 and grounded; the alarm circuit comprises a buzzer P9, wherein a pin 1 of the P9 is connected with a cathode of a diode D41 and one end of a resistor R178, the other end of the resistor R178 is connected with one end of a capacitor C3 and a 3.3V power supply, the other end of the capacitor C3 is grounded, a pin 2 of the P9 is connected with an anode of the diode D41 and a pin 3 of a BC817 triode Q40, a pin 2 of the Q40 is grounded, a pin 1 of the Q40 is connected with one end of a resistor R181, the other end of the resistor R181 is connected with a pin 35 of a M1B, a pin 1 of a contact switch K2 is connected with one end of a capacitor R177, one end of the capacitor C31 and a pin 39 of the M1B, the other end of the resistor R177 is connected with a 3.3V power supply, and the other ends of the capacitor C31 are grounded; the USB interface circuit comprises a USB interface P10, wherein a pin 1 of the P10 is connected with one end of a fuse F17, one end of a capacitor C32, a cathode of a diode D44, one end of a capacitor C33 and a 5V power supply, the other end of the fuse F17 is connected with 5VD, the other end of the capacitor C32 and the other end of the capacitor C33 are grounded, a pin 2 of the P10 is connected with a cathode of a diode D43 and one end of a resistor R179, the other end of the resistor R179 is connected with a pin 28 of an M1A, a pin 3 of the P10 is connected with a cathode of the diode D42 and one end of a resistor R180, the other end of the resistor R180 is connected with a pin 27 of the M1A, anodes of the diodes D42, D43 and D44 are grounded, and pins 5-9 of the P10 are grounded; the latch circuit comprises an SN74HCT125D chip U11, wherein a pin 1 of the U11 is connected with one end of a resistor R12 and a pin 74 of an M1A, the other end of the resistor R12 is connected with a 3.3V power supply, a pin 2 of the U11 is connected with a pin 72 of the M1A, pins 4, 10 and 13 of the U11 are connected with one end of a resistor R13, the other end of the resistor R13 is connected with a 3.3V power supply, pins 7, 5, 9 and 12 of the U11 are grounded, a pin 14 of the U11 is connected with one end of a capacitor C48 and the 3.3V power supply, and the other end of the capacitor C48 is grounded; the power conversion circuit comprises a WR-MPC4 chip P7, a pin 1 and a pin 2 are connected with a pin 4 of a rectifier bridge D39, a pin 3 and a pin 4 of P7 are connected with a pin 2 of the rectifier bridge D39, a pin 1 of the rectifier bridge D39 is connected with one end of a resistor R132, one end of a capacitor C17, one end of a capacitor C18 and a pin 1 of a WD30-48S05 chip PM1, a pin 3 of the rectifier bridge D39 is connected with the other end of the resistor R132, the other end of the capacitor C17, the other end of the capacitor C18, one end of a capacitor CY2 and a pin 2 of PM1, the other end of the capacitor CY2 is grounded, a pin 5 of PM1 is connected with one end of a capacitor C19 and is grounded, a pin 6 of PM1 is connected with the other end of the capacitor C19, the other end of the diode D46 and the anode of D49 are connected with the cathode of the diode D46, the cathode of the diode D49 is connected with the cathode of the diode D47, the cathode of the D50, one end of the fuse F8 and 5VCCIN, the anode of the diode D47 and the anode of the diode D50 are connected with the 3, 4 AO of the chip P8 of NI/WR-MPC4 chip P8, the pin 1 is grounded, the other end of the fuse F8 is connected with the pin 5, the anode of the diode P21 is grounded, the negative electrode of the capacitor C21 is grounded, the other end of the fuse F10 is connected with the 2 pin of the power chip U12, one end of the resistor R135, one end of the capacitor C24 and +5VD, the 8 pin of the U12 is connected with the other end of the resistor R135, the other end of the capacitor C24 is grounded, the 1, 4 and 6 pins of the U12 are grounded, the 3 pin of the U12 is connected with one end of the inductor L2, the other end of the inductor L2 is connected with the 5 pin of the U12, one end of the resistor R136, one end of the capacitor C25, one end of the capacitor C26 and 3.3V power supply, the other ends of the capacitors C25 and C26 are grounded, the 7 pin of the U12 is connected with the other end of the resistor R136 and one end of the resistor R138, the other end of the resistor R138 is grounded, the other end of the fuse F9 is connected with the 2 pin of the NI/ACT4070BYH chip U13, the 1 pin of the U13 is connected with one end of the capacitor C20, the other end of the capacitor C20 is connected with the 3 pin of the U13, one end of the inductor L1 and the cathode of the diode D40, the other end of the inductor L1, the other end of the capacitor 47 and the capacitor, one end of the capacitor C22 and +5VD, the other end of the resistor R133 and the other end of the capacitor C47 are connected with one end of the resistor R134 and the 5 pin of the U13, and the other end of the resistor R134, the anode of the diode D40 and the other end of the capacitor C22 are grounded; the TTL interface expansion application circuit comprises a CH438Q chip U14, a 1 pin of the U14 is connected with one end of a resistor R188, the other end of the resistor R188 is connected with an 80 pin of an M1A, a 2 pin of the U14 is connected with one end of a capacitor C39 and one end of a capacitor C40 and is connected with a 3.3V power supply, a 3 pin of the U14 is connected with the other end of the capacitor C39 and the other end of the capacitor C40 and is grounded, 4-10 of the U14 is respectively connected with 48, 50, 52, 54, 56, 58 and 60 pins of the M1A, a 32 pin of the U14 is connected with one end of a resistor R187 and 21 pin of the M1A, the other end of the resistor R187 is connected with a 3.3V power supply, a 33 pin of the U14 is connected with one end of a resistor R183, one end of a resistor C36 is connected with the other end of the resistor R183, the other end of the resistor C36 is grounded, the other end of the resistor R184 is connected with 9 pin of the M1A, 34-41 pins of the U14 are respectively connected with 79, 77, 75, 73, 71, 69, 67 and 65 pins of the U14 are respectively connected with the other end of the resistor C1A, the U14 is grounded at 42 pins, the U14 is connected with one end of a resistor R186, the other end of the resistor R186 is connected with the pin 76 of M1A, the U14 is connected with one end of a resistor R185, the other end of the resistor R185 is connected with the pin 81 of M1A, the U15 is connected with one ends of 1, 4, 10 and 13 pins of a SN74HCT125D chip U15, the U15 is connected with the pin 68 of M1A, the U15 is connected with the pin 9 of M1A, the U15 is connected with the pin 11 of M1A, the U15 is connected with one end 59 of M1A, the resistor R163, the U15 is connected with the pin 8 of R164, the U15 is connected with the pin 62 of M1A and the resistor R165, the U15 is connected with the pin 3 of R166, the U15 is connected with the pins 14 of R163, R164, R165, the R166 of R166 and 3.3V power supply, and the other end of the capacitor C46 is grounded.

The foregoing description of the invention is merely exemplary of the invention. Various modifications or additions to the described embodiments may be made by those skilled in the art to which the invention pertains or in a similar manner, without departing from the spirit of the invention or beyond the scope of the invention as defined in the appended claims.

Claims

1. An intelligent ODF rack for efficiently collecting optical wiring and alarm states, which is characterized in that: the intelligent MODF disk management system comprises an intelligent MODF disk manager, an intelligent MODF frame manager and an intelligent MODF frame manager, wherein the intelligent MODF disk manager is connected with the intelligent MODF frame manager, the intelligent MODF frame manager is connected with the intelligent MODF frame manager, and the intelligent MODF frame manager is connected with an intelligent ODF management system;

The intelligent MODF frame manager collects, stores and forwards eID tag information, port information, disk information and frame information to the intelligent ODF management system, and forwards an instruction or configuration issued by the intelligent ODF management system to the disk manager;

the intelligent MODF disk manager comprises a 6-path electronic tag interface circuit, a disk manager status light circuit, a disk manager main control circuit, a disk manager program burning port circuit, a disk manager data storage unit circuit and a disk manager program debugging serial port circuit, wherein the 6-path electronic tag interface circuit, the disk manager status light circuit, the disk manager program burning port circuit, the disk manager data storage unit circuit and the disk manager program debugging serial port circuit are respectively connected with the disk manager main control circuit;

the master control circuit of the disc manager comprises STM32F103CBT6 chips U1, 9, 36 and 48 pins of U1 are connected with a 3.3V power supply, 7 pins of U1 are connected with one end of a resistor R3 and one end of a capacitor C7, the other end of the resistor R3 is connected with the 3.3V power supply, the other end of the capacitor C7 is grounded, 8, 23, 35, 44 and 47 pins of U1 are grounded, 5 pins of U1 are connected with one end of a crystal oscillator tube XTAL1 and one end of a capacitor C8, 6 pins of U1 are connected with the other end of the crystal oscillator tube XTAL1 and one end of a capacitor C9, and the other end of the capacitor C8 and the other end of the capacitor C9 are grounded; the electronic tag interface circuit comprises an interface P_1, wherein pins 1 and 4 of the interface P_1 are grounded, pins 2 and 3 of the interface P_1 are connected with one end of a resistor R15 and the cathode of a diode D4, the other end of the resistor R15 is connected with a 3.3V power supply, and the anode of the diode D4 is grounded; the disk manager status light circuit comprises a resistor R4, one end of the resistor R4 is connected with a 3.3V power supply, the other end of the resistor R4 is connected with the anode of a light emitting diode LED1, the cathode of the light emitting diode LED1 is connected with a pin 45 of U1, the anodes of the light emitting diodes LED_1, LED_2, LED_3, LED_4, LED_5 and LED_6 are connected with the 3.3V power supply, the cathodes of the light emitting diodes LED_1, LED_2, LED_3, LED_4, LED_5 and LED_6 are respectively connected with one end of a resistor R17, one end of a resistor R21, one end of a resistor R25, one end of a resistor R27, one end of a resistor R31 and one end of a resistor R33, the other end of the resistor R17, the other end of the resistor R21, the other end of the resistor R25, the other end of the resistor R27, the other end of the resistor R31 and the other end of the resistor R33 are respectively connected with pins 33, 29, 27, 17, 19 and 21 of the pin 21 of U1;

The programming interface circuit of the disc manager program comprises a programming interface P1, wherein a pin 1 of the programming interface P1 is connected with one end of a resistor R1 and is connected with a 3.3V power supply, a pin 2 of the programming interface P1 is connected with the other end of the resistor 1 and a pin 34 of U1, a pin 3 of the programming interface P1 is connected with one end of a resistor R2 and a pin 37 of U1, and the other end of the resistor R2 is grounded; the disk manager data storage unit circuit comprises a 24C04 chip U2, pins 1, 2, 3 and 4 of the U2 are grounded, pin 5 of the U2 is connected with one end of a resistor R6 and pin 43 of the U1, pin 6 of the U2 is connected with one end of a resistor R7 and pin 42 of the U1, the other end of the resistor R6 and the other end of the resistor R7 are connected with a 3.3V power supply, pin 7 of the U2 is connected with one end of a capacitor C10 and grounded, and pin 8 of the U2 is connected with the other end of the capacitor C10 and the 3.3V power supply; the serial port debugging circuit of the disk manager program comprises a serial port P2, a pin 1 of the serial port P2 is connected with a pin 31 of U1, a pin 2 of the serial port P2 is connected with a pin 30, and a pin 3 of the serial port P2 is grounded.

2. The intelligent ODF rack for efficiently collecting optical wiring and alarm conditions as in claim 1, wherein: the intelligent MODF frame manager comprises 12 RJ45 interface circuits, a frame manager main control circuit, a frame manager program burning port circuit, a frame manager data storage unit, a logic control switch circuit, a frame manager program debugging serial port circuit, a frame manager uplink communication port circuit and a frame manager power supply circuit, wherein the 12 RJ45 interface circuits, the frame manager program burning port circuit, the frame manager data storage unit, the logic control switch circuit, the frame manager program debugging serial port circuit, the frame manager uplink communication port circuit and the frame manager power supply circuit are respectively connected with the frame manager main control circuit.

3. An intelligent ODF rack for efficiently collecting optical wiring and alarm conditions as in claim 2, wherein: the main control circuit of the frame manager comprises an STM32F103 chip U3, pins 1, 64, 13, 19, 32 and 48 of the U3 are connected with a 3.3V power supply, pins 31, 47, 12, 63 and 60 of the U3 are grounded, pin 7 of the U3 is connected with one end of a resistor R5 and one end of a capacitor C17, the other end of the resistor R5 is connected with the 3.3V power supply, and the other end of the capacitor C17 is grounded; the RJ45 interface circuit comprises an RJ45 interface P_2, pins 7, 8, 11 and 12 of the RJ45 interface P_2 are grounded, pin 1 of the RJ45 interface P_2 is connected with one end of a resistor R33, pin 2 of the RJ45 interface P_2 is connected with one end of a resistor R31, the other end of the resistor R33 is connected with the cathode of a diode D7, the other end of the resistor R31 is connected with the cathode of a diode D6, the anode of the diode D7 and the anode of the diode D6 are grounded, pin 3 of the RJ45 interface P_2 is connected with one end of a resistor R25, pin 51 of U3 and the cathode of a diode D4, pins 4 and 5 of the RJ45 interface P_2 are connected with a 5V power supply, pin 6 of the RJ45 interface P_2 is connected with one end of a resistor R29, the other end of the resistor R29 is connected with one end of a resistor R21 and one end of a resistor R23, the other end of the resistor R21 is connected with pin 1 of a BC817 chip Q2, pin 2 of the other end of the resistor R23 is grounded, pin 3 of the chip Q2 is connected with one end of a resistor R24 and pin 35 of U3, and the other end of the resistor R25 is connected with 3.3V power supply; the frame manager program programming port circuit comprises a programming port P3, wherein a 1 pin of the programming port P3 is connected with one end of a resistor R13 and a 3.3V power supply, a 2 pin of the programming port P3 is connected with the other end of the resistor R13 and a 46 pin of U3, a 3 pin of the programming port P3 is connected with one end of a resistor R14 and a 49 pin of U3, and the other end of the resistor R14 is grounded; the frame manager data storage unit comprises a 24C08 chip U4, pins 1, 2, 3 and 4 of the U4 are grounded, pin 5 of the U4 is connected with one end of a resistor R16 and pin 59 of the U3, pin 6 of the U4 is connected with one end of a resistor R17 and pin 58 of the U3, the other end of the resistor R16 and the other end of the resistor R17 are connected with a 3.3V power supply, pin 7 of the U4 is connected with one end of a capacitor C18 and grounded, and pin 8 of the U4 is connected with the other end of the capacitor C18 and the 3.3V power supply; the logic control switch circuit comprises a CD74HC4067M chip U5 and U6, wherein the 1 pin of the U5 is connected with the 17 pin of the U3, the 17 pin of the U5 is connected with the other end of a resistor R31, the 17 pin of the U6 is connected with the other end of the resistor R33, the 18-22 pin and the 3-8 pin of the U5 and the U6 are respectively connected with the rest 11 paths of RJ45 interface circuits, the 10 pin, the 11 pin, the 14 pin and the 13 pin of the U5 and the U6 are respectively connected with the 20-23 pin of the U3, the 12 pin and the 15 pin of the U5 and the U6 are grounded, the 24 pin of the U5 is connected with one end of a capacitor C11 and a 3.3V power supply, the other end of the capacitor C11 is grounded, the 24 pin of the U6 is connected with one end of a capacitor C12 and the 3.3V power supply, the other end of the capacitor C12 is grounded, and the 9 pin of the U6 is connected with the 16 pin of the U3; the serial port circuit for debugging the frame manager program comprises a serial port P4, pins 1 and 2 of the serial port P4 are respectively connected with pins 43 and 42, and pin 3 of the serial port P4 is grounded.

4. An intelligent ODF rack for efficiently collecting optical wiring and alarm conditions as in claim 3, wherein: the frame manager uplink communication port circuit comprises RJ45 interfaces P5 and P5, wherein a 1 pin of the P5 is connected with one end of a resistor R9, a 2 pin of the P5 is connected with one end of a resistor R8, the other end of the resistor R9 is connected with a cathode of a diode D2 and a 1 pin of a U6, the other end of the resistor R8 is connected with a cathode of a diode D3 and the 1 pin of the U5, an anode of the diode D2 is grounded, a 3 pin of the P5 is connected with a cathode of the diode D1 and a 3 pin of a BC817 chip Q1, an anode of the diode D1 and a 2 pin of the Q1 are grounded, a 1 pin of the Q1 is connected with a 14 pin of the U3, 4, 5 and 6 pins of the P5 are connected with one end of a capacitor C13 and a 5V power supply, 7 pins of the P5 and 8 pins of the P5 are connected with the other end of the capacitor C13 and are grounded, and 11 pins of the P5 are grounded; the frame manager power supply circuit comprises an NI/TPS62160 chip U7, pins 1 and 4 of the U7 are grounded, pins 2 and 3 of the U7 are connected with TP1, one end of a capacitor C16, one end of a capacitor C15, one end of a resistor R13, 3 pins of an AP7361C-33DR chip U8, the other end of the capacitor C15 and the other end of the capacitor C16 are grounded, the other end of the resistor R13 is connected with a 5V power supply, one end of the resistor R18 and one end of the resistor R17 are connected with the other end of the resistor R18, the other end of the resistor R18 is grounded, the other end of the 6 pin of the U7 is connected with the other end of the resistor R17, one end of an inductor L1, one end of the resistor R14, one end of the capacitor C17, one end of the TP1, one end of the capacitor C18, one end of the resistor R15 and 2 pins of U8, the pin 7 of the pin of the U7 is connected with the other end of the resistor R14, the other end of the capacitor C17 and the other end of the capacitor C18 are connected with TP3 and grounded, the other end of the resistor R15 is connected with 3.3V power supply, and the pin 1 of U8 is grounded.

5. The intelligent ODF rack for efficiently collecting optical wiring and alarm conditions as in claim 1, wherein: the intelligent MODF rack manager comprises a rack manager main control circuit, a 12-channel rack manager interface circuit, an Ethernet interface circuit, a reset circuit, an alarm circuit, a USB interface circuit, a latch circuit, a power conversion circuit and a TTL interface expansion application circuit.

6. The intelligent ODF rack for efficiently collecting optical wiring and alarm conditions as in claim 5, wherein: the master control circuit of the rack manager comprises an MC-A5D3X chip M1A, M B, wherein the 10 pin of the M1A is connected with one end of a resistor R21, the 12 pin of the M1A is connected with one end of a resistor R22, the 94, 96, 93, 95, 7 and 23 of the M1A are grounded, the 97-100 pin of the M1A is connected with one end of a capacitor C1, one end of a capacitor C2, one end of a capacitor C37 and is connected with a 3.3V power supply, the other end of the capacitor C1, the other end of the capacitor C2 and the other end of the capacitor C37 are grounded, and the 33, 34, 67 and 68 pins of the M1B are grounded; the shelf manager interface circuit comprises RJ45 interface P4A, 1 pin of P4A is connected with one end of a resistor R36, 2 pin of P4A is connected with one end of a resistor R34, the other end of the resistor R36 is connected with a cathode of a diode D6, the other end of the resistor R34 is connected with a cathode of a diode D5, an anode of the diode D6 and an anode of the diode D5 are grounded, 3 pin of P4A is connected with one end of a resistor R28, a cathode of the diode D3 and a pin of M1B, an anode of the diode D3 is grounded, 6 pin of P4A is connected with one end of a resistor R32, the other end of the resistor R32 is connected with one end of a resistor R24 and one end of a resistor R26, the other end of the resistor R24 is connected with 1 pin of a BC817 chip Q4, the other end of the resistor R26 and the 2 pin of Q4 are grounded, the 3 pin of Q4 is connected with the 66 pin of M1B and one end of a resistor R27, the other end of the resistor R27 and the other end of the resistor R28 are connected with a 3.3V power supply, the 3 pin of a DMP2130L field effect transistor Q11 is connected with one end of a resistor R67 and a 5V power supply, the 2 pin of Q11 is connected with one end of a fuse F2, the other end of the fuse F2 is connected with V_OUT1, the 1 pin of Q11 is connected with the other end of the resistor R67 and one end of the resistor R69, the other end of the resistor R69 is connected with the 3 pin of a BC817 chip Q13, the 2 pin of Q13 is grounded, the 1 pin of Q13 is connected with one end of a resistor R73, the other end of the resistor R73 is connected with one end of the resistor R71 and the 98 pin of M1B, and the other end of the resistor R71 is connected with the 3.3V power supply; the ethernet interface circuit comprises a HR911105a chip U9, pin 1 of U9 is connected to pin 2 of M1A, resistor R168 is connected to pin 2 of U9, pin 1 of M1A is connected to resistor R169, resistor R168 is connected to the other end of resistor R169 to one end of capacitor C27, the other end of capacitor C27 is grounded, pins 4 and 5 of U9 are connected to one end of capacitor C44, one end of capacitor C45 and one end of inductor L3, the other end of capacitor C44 and the other end of capacitor C45 are grounded, pin 8 of M1A is connected to the other end of inductor L3, pin 3 of U9 is connected to pin 4 of M1A, one end of resistor R170, pin 6 of U9 is connected to pin 3 of M1A, one end of resistor R171 is connected to the other end of resistor R170 and one end of resistor R171, pin 9 is connected to one end of resistor C28, pin 9 of resistor C172 is grounded, pin 12 of U9 is connected to one end of resistor R173, and pin 10 and 11 of U9 are connected to pins 3.3v, 6 and 5 of M1A, respectively.

7. The intelligent ODF rack for efficiently collecting optical wiring and alarm conditions as in claim 5, wherein: the reset circuit comprises an SP706SEN chip U10, wherein pins 1 and 8 of the U10 are connected with one end of a resistor R174, one end of a capacitor C29 and the pin 1 of a contact switch K1, the other end of the resistor R174 is connected with a 3.3V power supply, the other end of the capacitor C29 and pins 2, 3 and 4 of the K1 are grounded, the pin 2 of the U10 is connected with one end of a capacitor C30 and the power supply of 3.3V, and the pins 3 and 4 of the U10 are connected with the other end of the capacitor C30 and are grounded; the alarm circuit comprises a buzzer P9, wherein a pin 1 of the P9 is connected with a cathode of a diode D41 and one end of a resistor R178, the other end of the resistor R178 is connected with one end of a capacitor C3 and a 3.3V power supply, the other end of the capacitor C3 is grounded, a pin 2 of the P9 is connected with an anode of the diode D41 and a pin 3 of a BC817 triode Q40, a pin 2 of the Q40 is grounded, a pin 1 of the Q40 is connected with one end of a resistor R181, the other end of the resistor R181 is connected with a pin 35 of a M1B, a pin 1 of a contact switch K2 is connected with one end of a capacitor R177, one end of the capacitor C31 and a pin 39 of the M1B, the other end of the resistor R177 is connected with a 3.3V power supply, and the other ends of the capacitor C31 are grounded; the USB interface circuit comprises a USB interface P10, wherein a pin 1 of the P10 is connected with one end of a fuse F17, one end of a capacitor C32, a cathode of a diode D44, one end of a capacitor C33 and a 5V power supply, the other end of the fuse F17 is connected with 5VD, the other end of the capacitor C32 and the other end of the capacitor C33 are grounded, a pin 2 of the P10 is connected with a cathode of a diode D43 and one end of a resistor R179, the other end of the resistor R179 is connected with a pin 28 of an M1A, a pin 3 of the P10 is connected with a cathode of the diode D42 and one end of a resistor R180, the other end of the resistor R180 is connected with a pin 27 of the M1A, anodes of the diodes D42, D43 and D44 are grounded, and pins 5-9 of the P10 are grounded; the latch circuit comprises an SN74HCT125D chip U11, wherein a pin 1 of the U11 is connected with one end of a resistor R12 and a pin 74 of an M1A, the other end of the resistor R12 is connected with a 3.3V power supply, a pin 2 of the U11 is connected with a pin 72 of the M1A, pins 4, 10 and 13 of the U11 are connected with one end of a resistor R13, the other end of the resistor R13 is connected with a 3.3V power supply, pins 7, 5, 9 and 12 of the U11 are grounded, a pin 14 of the U11 is connected with one end of a capacitor C48 and the 3.3V power supply, and the other end of the capacitor C48 is grounded; the power conversion circuit comprises a WR-MPC4 chip P7, a pin 1 and a pin 2 are connected with a pin 4 of a rectifier bridge D39, a pin 3 and a pin 4 of P7 are connected with a pin 2 of the rectifier bridge D39, a pin 1 of the rectifier bridge D39 is connected with one end of a resistor R132, one end of a capacitor C17, one end of a capacitor C18 and a pin 1 of a WD30-48S05 chip PM1, a pin 3 of the rectifier bridge D39 is connected with the other end of the resistor R132, the other end of the capacitor C17, the other end of the capacitor C18, one end of a capacitor CY2 and a pin 2 of PM1, the other end of the capacitor CY2 is grounded, a pin 5 of PM1 is connected with one end of a capacitor C19 and is grounded, a pin 6 of PM1 is connected with the other end of the capacitor C19, the other end of the diode D46 and the anode of D49 are connected with the cathode of the diode D46, the cathode of the diode D49 is connected with the cathode of the diode D47, the cathode of the D50, one end of the fuse F8 and 5VCCIN, the anode of the diode D47 and the anode of the diode D50 are connected with the 3, 4 AO of the chip P8 of NI/WR-MPC4 chip P8, the pin 1 is grounded, the other end of the fuse F8 is connected with the pin 5, the anode of the diode P21 is grounded, the negative electrode of the capacitor C21 is grounded, the other end of the fuse F10 is connected with the 2 pin of the power chip U12, one end of the resistor R135, one end of the capacitor C24 and +5VD, the 8 pin of the U12 is connected with the other end of the resistor R135, the other end of the capacitor C24 is grounded, the 1, 4 and 6 pins of the U12 are grounded, the 3 pin of the U12 is connected with one end of the inductor L2, the other end of the inductor L2 is connected with the 5 pin of the U12, one end of the resistor R136, one end of the capacitor C25, one end of the capacitor C26 and 3.3V power supply, the other ends of the capacitors C25 and C26 are grounded, the 7 pin of the U12 is connected with the other end of the resistor R136 and one end of the resistor R138, the other end of the resistor R138 is grounded, the other end of the fuse F9 is connected with the 2 pin of the NI/ACT4070BYH chip U13, the 1 pin of the U13 is connected with one end of the capacitor C20, the other end of the capacitor C20 is connected with the 3 pin of the U13, one end of the inductor L1 and the cathode of the diode D40, the other end of the inductor L1, the other end of the capacitor 47 and the capacitor, one end of the capacitor C22 and +5VD, the other end of the resistor R133 and the other end of the capacitor C47 are connected with one end of the resistor R134 and the 5 pin of the U13, and the other end of the resistor R134, the anode of the diode D40 and the other end of the capacitor C22 are grounded; the TTL interface expansion application circuit comprises a CH438Q chip U14, a 1 pin of the U14 is connected with one end of a resistor R188, the other end of the resistor R188 is connected with an 80 pin of an M1A, a 2 pin of the U14 is connected with one end of a capacitor C39 and one end of a capacitor C40 and is connected with a 3.3V power supply, a 3 pin of the U14 is connected with the other end of the capacitor C39 and the other end of the capacitor C40 and is grounded, 4-10 of the U14 is respectively connected with 48, 50, 52, 54, 56, 58 and 60 pins of the M1A, a 32 pin of the U14 is connected with one end of a resistor R187 and 21 pin of the M1A, the other end of the resistor R187 is connected with a 3.3V power supply, a 33 pin of the U14 is connected with one end of a resistor R183, one end of a resistor C36 is connected with the other end of the resistor R183, the other end of the resistor C36 is grounded, the other end of the resistor R184 is connected with 9 pin of the M1A, 34-41 pins of the U14 are respectively connected with 79, 77, 75, 73, 71, 69, 67 and 65 pins of the U14 are respectively connected with the other end of the resistor C1A, the U14 is grounded at 42 pins, the U14 is connected with one end of a resistor R186, the other end of the resistor R186 is connected with the pin 76 of M1A, the U14 is connected with one end of a resistor R185, the other end of the resistor R185 is connected with the pin 81 of M1A, the U15 is connected with one ends of 1, 4, 10 and 13 pins of a SN74HCT125D chip U15, the U15 is connected with the pin 68 of M1A, the U15 is connected with the pin 9 of M1A, the U15 is connected with the pin 11 of M1A, the U15 is connected with one end 59 of M1A, the resistor R163, the U15 is connected with the pin 8 of R164, the U15 is connected with the pin 62 of M1A and the resistor R165, the U15 is connected with the pin 3 of R166, the U15 is connected with the pins 14 of R163, R164, R165, the R166 of R166 and 3.3V power supply, and the other end of the capacitor C46 is grounded.