CN109872743A - A kind of fundamental technology memory - Google Patents
A kind of fundamental technology memory Download PDFInfo
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- CN109872743A CN109872743A CN201910205600.4A CN201910205600A CN109872743A CN 109872743 A CN109872743 A CN 109872743A CN 201910205600 A CN201910205600 A CN 201910205600A CN 109872743 A CN109872743 A CN 109872743A
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Abstract
The present invention provides a kind of fundamental technology memories, comprising: a logic chip and one or more memory chips, and interconnection terminal is set for connecting logic chip and memory chip, conduct electric signal between the two；At least one of described memory chip is cell memory CMEM；Internet in encapsulation is set, multiple conductive paths are provided, the electrical communication path of command signal/RAS ,/CAS between the electrical communication path of electrical communication path, CMEM including DQ and/or DQS signal between CMEM and the address signal Ax between logic chip, CMEM and logic chip；The signal is difference or single-ended, active low level or active high level.The present invention solves the problems, such as that design cost existing for memory chip in the prior art, test development be at high cost and low yield rate, and realizing reduces production cost.
Description
Technical field
The present invention relates to memory technology field, especially a kind of fundamental technology memory.
Background technique
DRAM technology has had the history of many years, and with time change, fundamental technology is held essentially constant, such as quick page
Surface model (FPM), growth data output (EDO), synchronous dram (SDRAM), double data rate 1-4 (DDR1, DDR2, DDR3,
DDR4) etc..
The basic framework of DRAM is shown in Fig. 1, and the row address that outside provides is decoded and causes to activate wordline WL,
Such as it is connected to the door of 8192 single storage units, and start sensing process, it is stored in sensor amplifier SA for amplifying
8192 single storage units weak signal.After row address, column address will be by identical external address bus by by suitable
Sequence provides.The column address is provided by column address decoder, and the column address decoder is the subset of wordline WL, such as 8192
The subset of a selected bits.In this example, 64 in 8192 sensing positions of 1:128 decoding selection, are put with being transmitted to secondary sensing
Big device.Current state-of-the-art DRAM technology usually execute it is so-called prefetch, i.e. the data ratio of inter access is forwarded to outside and draws
The data of foot are more.In the example of display, 64 are prefetched by sequencer and are sequentially forwarded to exterior I/O driver.
Fig. 2, the example that a typical DRAM framework is realized is shown in 3.In order to realize lowest power consumption and least cost,
This DRAM usually with low cost and executes slow CMOS or similar techniques and realizes.If physical memory location is subdivided into
It is dry, such as 4 individual memory blocks.DRAM is accessed by the pad rows for external connection.In most standard
In design, as shown in Fig. 2, center pad row is realized, it is also possible to being located at chip perimeter, for from internal memory unit to outer
The logic circuitry portions of the signal processing of portion's pad are located at the outside of memory array.But it is all due to influencing on the same chip
Such as the performance parameter of speed and power consumption etc, so the signal processing circuit must be realized in identical CMOS technology.
The exploitation and test of DRAM is extremely complex and expensive, since it is desired that expensive mask costs, design cost,
Test development cost and low yield rate, but also the yield of chip factory is needed to learn, project cost usually ten million dollar with
On.Therefore, dram chip is generally used only for the JEDEC application of high capacity standard, often due to relevant high development cost, usually
It is in economy and infeasible.
Summary of the invention
The object of the present invention is to provide a kind of fundamental technology memories, it is intended to solve memory chip in the prior art and exist
Design cost, the problem of test development is at high cost and low yield rate, realizing reduces production cost.
To reach above-mentioned technical purpose, the present invention provides a kind of fundamental technology memory, the memory includes:
One logic chip and one or more memory chip, and be arranged interconnection terminal for connect logic chip with
And memory chip, conduct electric signal between the two；At least one of described memory chip is cell memory CMEM；
Internet in encapsulation is set, multiple conductive paths are provided, including the DQ and/or DQS signal between CMEM
Life between the electrical communication path of address signal Ax between electrical communication path, CMEM and logic chip, CMEM and logic chip
Enable the electrical communication path of signal/RAS ,/CAS；The signal is difference or single-ended, active low level or active high level.
Preferably, the cell memory CMEM has the connector for being connected to one or more supply voltages, and voltage is
Any one in VDD, VSS, VSSQ, VDDQ, VBGR, VNWLL, VPP；Internet in encapsulation is set, is deposited for unit
It is electrically connected supply voltage between reservoir CMEM and logic chip, at least one conductive path is provided.
Preferably, the internet in encapsulation is set, is electrically connected word between cell memory CMEM and logic chip
Line boost voltage VPP provide at least one conductive path；
It is electrically connected negative word line low pressure VNWLL between cell memory CMEM and logic chip, at least one conductive path is provided
Diameter；
It is electrically connected bandgap voltage reference VBGR between cell memory CMEM and logic chip, at least one conduction is provided
Path；
VSS is electrically connected between cell memory CMEM and logic chip and VSSQ provides at least one conductive path；
VDD is electrically connected between cell memory CMEM and logic chip and VDDQ provides at least one conductive path.
Preferably, the internet in encapsulation is set, master is electrically connected between cell memory CMEM and logic chip
Active electrical source voltage VDD provides at least one conductive path, and in the logic chip of external main power source VDDEXT and external envelope
The internet being arranged between dress provides a circuit on logic chip, for improving the virtual voltage electricity of VDD > VDDEXT
It is flat.
Preferably, the memory further includes active secondary amplifier SSA, the quantity of the active secondary amplifier SSA
It can set the parameters to be configured by the register of cell memory CMEM, or parameter is arranged by the programmable fuse on CMEM
It is configured, or static electric signal by configuring the offer of internet between logic chip and CMEM is configured.
Preferably, the quantity of the active secondary amplifier SSA can be one of following number:
4,8,16,32,64,128,256,512,1024,2048 or 4096；
Or one of following number:
9、17、33、65、129、257、513、1025、2049、4097、11、20、37、70、135、263、521、1034、
2060、4109。
Preferably, the number and the received DQ number of signals of logic chip of the active secondary amplifier SSA on the CMEM
It is identical, it will be in the active secondary amplifier SSA output signal and logic chip on CMEM by single-electrical signal or differential signal
The electrical connection of DQ input signal.
Preferably, one or more internet of the configuration between logic chip and CMEM are locked for providing DQS signal
Deposit DQ data.
Preferably, the memory provides the individual unit or length of redundant word line or redundant bit line or redundancy in 1-256
Redundancy word between position, word are the subsets or sum of active secondary amplifier SSA, and molten by laser blown device or electrically programmable
The redundant word line and bit line of disconnected device activation replaces defective line.
Preferably, the memory provides the logic chip of redundant storage unit, to replace active time that is stored in CMEM
The subset or logic chip of defective cell in grade amplifier SSA are with can replacing row associated with CMEM defect row
Location, and can be replaced with the address of the non-defective row of CMEM or logic chip can replace it is related to CMEM defect row
The column address of connection, and can be replaced with the address of the non-defective column of CMEM.
The effect provided in summary of the invention is only the effect of embodiment, rather than invents all whole effects, above-mentioned
A technical solution in technical solution have the following advantages that or the utility model has the advantages that
Compared with prior art, the invention proposes a kind of fundamental technology memories, by logic chip and one or more
A memory chip is combined encapsulation, and interconnection terminal is arranged for connecting logic chip and memory chip, conduction two
Electric signal between person.At least one of described memory chip is cell memory CMEM.The present invention by logic chip with
One or more memory array chips are combined, and a component packet is formed, and propose several key features of CMEM,
Different from existing DRAM product, and focus on the secondary sensing amplification, voltage supply and redundancy concept of CMEM.It solves existing
The problem of having in technology design cost, test development existing for memory chip at high cost and low yield rate, realizing reduces life
Produce cost.
Detailed description of the invention
Fig. 1 is a kind of DRAM basic framework schematic diagram provided in the embodiment of the present invention；
Fig. 2 is a kind of DRAM framework realization schematic diagram provided in the embodiment of the present invention；
Fig. 3 is a kind of encapsulation schematic diagram that storage chip is separated with logic chip provided in the embodiment of the present invention.
Specific embodiment
In order to clearly illustrate the technical characterstic of this programme, below by specific embodiment, and its attached drawing is combined, to this
Invention is described in detail.Following disclosure provides many different embodiments or example is used to realize different knots of the invention
Structure.In order to simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relationship between various embodiments and/or setting is discussed.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
It draws.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
A kind of fundamental technology memory is provided for the embodiments of the invention with reference to the accompanying drawing to be described in detail.
The embodiment of the invention discloses a kind of fundamental technology memory, the memory includes:
One logic chip and one or more memory chip, and be arranged interconnection terminal for connect logic chip with
And memory chip, conduct electric signal between the two；At least one of described memory chip is cell memory CMEM.
The embodiment of the present invention combines logic chip and one or more memory array chips, forms a group
Part packet, and several key features of CMEM are proposed, it is different from existing DRAM product, and focus on that the secondary sensing of CMEM is put
Greatly, voltage supply and redundancy concept.
Logic chip and one or more memory chips are combined encapsulation, and interconnection terminal is set for connecting
Logic chip and memory chip conduct electric signal between the two.At least one of described memory chip is unit
Memory CMEM.Internet in encapsulation is set, multiple conductive paths are provided, including the DQ and/or DQS signal between CMEM
Electrical communication path, the electrical communication path of address signal Ax between CMEM and logic chip, between CMEM and logic chip
The electrical communication path of command signal/RAS ,/CAS.Above-mentioned several signals can be difference or single-ended, active low level or active height
Level.
The cell memory CMEM, which has, is connected to the connectors of one or more supply voltages, such as VDD, VSS,
VSSQ, VDDQ, VBGR, VNWLL, VPP etc..Internet in encapsulation is set, is cell memory CMEM and logic chip
Between electrical connection supply voltage at least one conductive path is provided.
In addition, the internet in encapsulation is arranged in, wordline is electrically connected between cell memory CMEM and logic chip
Boost voltage VPP provides at least one conductive path；
It is electrically connected negative word line low pressure VNWLL between cell memory CMEM and logic chip, at least one conductive path is provided
Diameter；
It is electrically connected bandgap voltage reference VBGR between cell memory CMEM and logic chip, at least one conduction is provided
Path；
VSS is electrically connected between cell memory CMEM and logic chip and VSSQ provides at least one conductive path；
VDD is electrically connected between cell memory CMEM and logic chip and VDDQ provides at least one conductive path.
Internet in encapsulation is set, main active electrical source is electrically connected between cell memory CMEM and logic chip
Voltage VDD provides at least one conductive path, and sets between the logic chip and outer enclosure of external main power source VDDEXT
The internet set provides a circuit, for improving the actual voltage level of VDD > VDDEXT on logic chip.
The memory further includes active secondary amplifier SSA, and number is configurable, to allow various outputs parallel
Configuration.
The quantity of the active secondary amplifier SSA can be set the parameters to be matched by the register of cell memory CMEM
It sets, or sets the parameters to be configured by the programmable fuse on CMEM, or by configuring between logic chip and CMEM
The static electric signal that internet provides is configured.
The quantity of active secondary amplifier SSA can be one of following number:
4,8,16,32,64,128,256,512,1024,2048 or 4096；
One of or can be following number:
9、17、33、65、129、257、513、1025、2049、4097、11、20、37、70、135、263、521、1034、
2060、4109。
The number of active secondary amplifier SSA on the CMEM is identical as the received DQ number of signals of logic chip, leads to
Single-electrical signal or differential signal is crossed to believe the active secondary amplifier SSA output signal on CMEM and the DQ input on logic chip
Number electrical connection.
One or more internet between logic chip and CMEM are configured for providing DQS signal, latch DQ number
According to independently of provided DQ number of signals, there is only single DQS signals.The DQS signal is differential signal or mono signal.
The redundancy word of offer redundant word line or the individual unit or length of redundant bit line or redundancy between 1-256, word
It is the subset or sum of active secondary amplifier SSA, and passes through laser blown device or the redundancy word of electrically programmable fuse activation
Line and bit line replace defective line.
The logic chip of redundant storage unit is provided, to replace having in the active secondary amplifier SSA for being stored in CMEM
The subset or logic chip of defective unit can replace row address associated with CMEM defect row, and can use CMEM
The address of non-defective row replace or logic chip can replace column address associated with CMEM defect row, and can
To be replaced with the address of the non-defective column of CMEM.
Programmable flash memory or other persistent memory units are provided on logic chip, for storing on replacement CMEM
The address information of defect memory unit.
Memory CMEM provides following function: being provided by automatically traversing all available row and column addresses for surveying
The function of memory CMEM is tried, and/or is generated during wafer sort or final systems test about memory to be stored in
The data of signal DQ in CMEM, and/or the number compared during chip or element test from the CMEM DQ signal read is provided
It verifies whether stored data are still correctly stored in the function on CMEM accordingly, and/or provides for above-mentioned function in crystalline substance
The subset of the test probe used during built-in testing, especially each CMEM chip are less than 15 probes.
The embodiment of the present invention proposes a kind of fundamental technology memory, by logic chip and one or more storage cores
Piece is combined encapsulation, and interconnection terminal is arranged for connecting logic chip and memory chip, conducts electricity between the two
Signal.At least one of described memory chip is cell memory CMEM.The present invention is by logic chip and one or more
Memory array chip is combined, and a component packet is formed, and proposes several key features of CMEM, is different from existing
DRAM product, and focus on CMEM secondary sensing amplification, voltage supply and redundancy concept.It solves and deposits in the prior art
The problem of design cost, test development existing for memory chip be at high cost and low yield rate, realizing reduces production cost.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (10)
1. a kind of fundamental technology memory, which is characterized in that the memory includes:
One logic chip and one or more memory chips, and interconnection terminal is set for connecting logic chip and depositing
Memory chip conducts electric signal between the two；At least one of described memory chip is cell memory CMEM；
Internet in encapsulation is set, multiple conductive paths are provided, including between CMEM DQ and/or DQS signal be electrically connected
Connect the order letter between the electrical communication path, CMEM and logic chip of the address signal Ax between path, CMEM and logic chip
Number/RAS ,/CAS electrical communication path；The signal is difference or single-ended, active low level or active high level.
2. a kind of fundamental technology memory according to claim 1, which is characterized in that the cell memory CMEM has
It is connected to the connector of one or more supply voltages, appointing in voltage VDD, VSS, VSSQ, VDDQ, VBGR, VNWLL, VPP
It anticipates one kind；Internet in encapsulation is set, supply voltage is electrically connected between cell memory CMEM and logic chip and is mentioned
For at least one conductive path.
3. a kind of fundamental technology memory according to claim 2, which is characterized in that the internet in encapsulation is arranged in
Network is electrically connected boosting word line voltage VPP between cell memory CMEM and logic chip and provides at least one conductive path；
It is electrically connected negative word line low pressure VNWLL between cell memory CMEM and logic chip, at least one conductive path is provided；
It is electrically connected bandgap voltage reference VBGR between cell memory CMEM and logic chip, at least one conductive path is provided；
VSS is electrically connected between cell memory CMEM and logic chip and VSSQ provides at least one conductive path；
VDD is electrically connected between cell memory CMEM and logic chip and VDDQ provides at least one conductive path.
4. a kind of fundamental technology memory according to claim 2, which is characterized in that the internet in encapsulation is arranged in
Network is electrically connected main active electrical source voltage VDD between cell memory CMEM and logic chip and provides at least one conductive path,
And the internet being arranged between the logic chip and outer enclosure of external main power source VDDEXT, it is provided on logic chip
One circuit, for improving the actual voltage level of VDD > VDDEXT.
5. a kind of fundamental technology memory according to claim 1, which is characterized in that the memory further includes active time
Grade amplifier SSA, the quantity of the active secondary amplifier SSA can be set the parameters to by the register of cell memory CMEM into
Row configuration, or is set the parameters to be configured by the programmable fuse on CMEM, or by configure logic chip and CMEM it
Between the static electric signal that provides of internet configured.
6. a kind of fundamental technology memory according to claim 5, which is characterized in that the active secondary amplifier SSA
Quantity can be one of for following number:
4,8,16,32,64,128,256,512,1024,2048 or 4096；
Or one of following number:
9、17、33、65、129、257、513、1025、2049、4097、11、20、37、70、135、263、521、1034、2060、
4109。
7. a kind of fundamental technology memory according to claim 1, which is characterized in that the active secondary on the CMEM is put
The number of big device SSA is identical as the received DQ number of signals of logic chip, will be on CMEM by single-electrical signal or differential signal
Active secondary amplifier SSA output signal is electrically connected with the DQ input signal on logic chip.
8. a kind of fundamental technology memory according to claim 7, which is characterized in that configuration logic chip and CMEM it
Between one or more internet for providing DQS signal, latch DQ data.
9. a kind of fundamental technology memory according to claim 1, which is characterized in that the memory provides redundant word line
Or redundancy word of the individual unit or length of redundant bit line or redundancy between 1-256, word are active secondary amplifier SSA
Subset or sum, and it is defective to replace by the redundant word line and bit line of laser blown device or the activation of electrically programmable fuse
Line.
10. a kind of fundamental technology memory according to claim 1, which is characterized in that the memory provides redundancy and deposits
The logic chip of storage unit, to replace the subset of the defective cell in the active secondary amplifier SSA for being stored in CMEM, or
Logic chip can replace row address associated with CMEM defect row, and can be replaced with the address of the non-defective row of CMEM
It changes or logic chip can replace column address associated with CMEM defect row, and the non-defective column of CMEM can be used
Address is replaced.
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Application publication date: 20190611 |