CN109871275A - Multicomputer system and its processor management method - Google Patents
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Abstract
The present invention provides a multicomputer system and its processor management method.Record has a par-ticular processor for the acceptance of a shared peripheral interrupt requests in one buffer.One Thread generation circuit receives multiple requests, generates multiple Threads accordingly.Whenever Thread generation circuit receives multiple request for the moment, a label determines that the attribute of the circuit root Thread is that the Thread determines that an instantaneity marks.One scheduler selects the par-ticular processor by the one of execution preferential Thread.One adjustment circuit is marked according to the instantaneity of preferential Thread, until buffer sets the par-ticular processor when executing preferential Thread for the acceptance of the shared peripheral interrupt requests.The acceptance that one interrupt control unit is recorded the buffer when assigning interrupt requests accounts for.
Description
Technical field
The present invention is related to multicomputer system.
Background technique
In order to improve efficiency, in addition to PC and notebook computer, there are more and more consumer electrical products in recent years
Using the circuit framework comprising multiple separate central processing units.These processors are usually designed to by single homework system control
System, and can support multiple application programs while operate.The schematic diagram of this type multicomputer system is presented in Fig. 1.It is more
Processor system 100 includes that N number of processor (is denoted as 1101、1102、…、110N, it is referred to as processor 110, N is whole greater than one
Number), a Thread (thread) generation circuit 120, a total scheduler 130, N number of scheduler (be denoted as 1401、1402、…、
140N, it is referred to as scheduler 140) and an interrupt control unit (interrupt controller) 150.
Thread generation circuit 120 is responsible for receiving the request from application program 191~194, and each application program must be handed over
Corresponding multiple Threads are packaged as by the task that processor 110 executes.Total scheduler 130 can be current according to each processor
Workload, determine how the Thread that Thread generation circuit 120 generates should be distributed to the respective queue of these processors
(queue).The scheduler 140 that each processor 110 is respectively arranged in pairs or groups is highest to pick out degree of priority from its queue
Thread comes, and processor 110 is enabled to execute.
Interrupt control unit 150 is responsible for receiving the interruption that the circuits (not being painted) such as memory, timer, image processor issue
It requests (interrupt request, IRQ), and is communicated to processor 110.In a multicomputer system, usually have in several
Disconnected request is asked comprising specific aim (per-processor) interrupt requests and shared peripheral (shared peripheral) interruption
It asks.Specific aim interrupt requests mean the interrupt requests issued for a par-ticular processor, can only be handled by the par-ticular processor,
It is interrupted caused by communication e.g. between interrupt requests either two two processors of the timer sending of processor itself
It requests (inter-processor interrupt).Relatively, shared peripheral interrupt requests are then any in N number of processor 110
What a processor can be handled.
In the operational logic of general job system, the priority of interrupt requests is higher than all Threads.Whenever out
An existing specific aim interrupt requests, corresponding par-ticular processor can suspend Thread originally in progress, start to process
This specific aim interrupt requests.On the other hand, whenever there are a shared peripheral interrupt requests, then be any one at that time not
The processor 110 for handling other interrupt requests, can all be added the ranks of competition, strive for this shared peripheral interrupt requests
Disposal right.Then, the processor 110 for winning disposal right will start to process this shared peripheral interrupt requests；Originally by this
Reason device 110 Thread in progress can be suspended (even if this duty cycle not yet terminates), put back into its queue and wait, directly
To being chosen by the scheduler 140 of the processor 110 next time, can just be merely re-executed.
The shortcomings that above-mentioned way, is, if certain Threads were suspended because of the relationship that interrupt requests intervene by processor midway
Long, it will cause problem.One classical situation is betided when certain processor is handling the Thread of some high instantaneity, and is connect
An interrupt requests have been received, so that the dead time length of the Thread is more than a predetermined time period, have caused the data of Thread
Leakage or other mistakes.It is former if Thread in progress is abandoned halfway by taking the Thread of music playing process as an example
Originally the melody in broadcasting is it is possible that discontinuous interruption situation, leads to undesirable user's experience.
Summary of the invention
To solve the above problems, the present invention proposes a kind of new multicomputer system and its processor management method.
Specific embodiment is a kind of multicomputer system one of according to the present invention, wherein including multiple processors, one temporary
Device, a Thread generation circuit, a label determine circuit, a scheduler, an adjustment circuit and an interrupt control unit.This is temporary
Record has in multiple processor a par-ticular processor for the acceptance of a shared peripheral interrupt requests in device.The Thread produces
Raw circuit generates the multiple Threads that multiple processor will be transferred to execute, wherein multiple to receive multiple requests accordingly
Thread corresponds to multiple application programs.Whenever the Thread generation circuit receives multiple request for the moment, which determines
Determine circuit and determines that an instantaneity of the Thread is marked to be supplied to the execution according at least to an attribute of the corresponding Thread
Thread generation circuit.The scheduler selects the par-ticular processor that will hold to be dispatched to certainly in multiple Threads of the par-ticular processor
The preferential Thread of capable one.The adjustment circuit is marked according to the instantaneity of the preferential Thread, until the buffer sets the spy
Processor is determined when executing the preferential Thread for the acceptance of the shared peripheral interrupt requests.The interrupt control unit is to incite somebody to action
Multiple interrupt requests are dispatched to multiple processor, and are somebody's turn to do when assigning multiple interrupt requests by what the buffer was recorded
Acceptance accounts for.
It is according to another embodiment of the present invention a kind of processor management method, to unification multicomputer system
In a processor.The management method includes: (a) receiving the multiple requests for corresponding to multiple application programs, generates accordingly multiple
Thread, and be that the Thread determines that an instantaneity marks for an attribute of each Thread；(b) it is dispatched to the specific place certainly
It manages and selects a preferential Thread in multiple Threads of device, and marked according to the instantaneity of the preferential Thread, set the spy
Processor is determined when executing the preferential Thread for the acceptance of a shared peripheral interrupt requests；And it is (c) specific according to this
Processor decides whether the shared peripheral interrupt requests being dispatched to this specific for the acceptance of the shared peripheral interrupt requests
Processor.
Still another embodiment according to the present invention is a kind of non-transient computer-readable storage medium, is applied to a many places
Device system is managed, wherein storing the procedure code that can be read and be executed by a processor.The procedure code is to manage the multiprocessing
A processor in device system.In the procedure code, one first procedure code corresponds to the multiple of multiple application programs to receive
Request generates multiple Threads accordingly, and is that the Thread determines that an instantaneity marks for an attribute of each Thread.One
Second procedure code selects a preferential Thread to be dispatched to certainly in multiple Threads of the par-ticular processor, and preferential according to this
The instantaneity of Thread marks, and sets the par-ticular processor and the interruption of one shared peripheral is asked when executing the preferential Thread
The acceptance asked.One third procedure code is to the acceptance according to the par-ticular processor for the shared peripheral interrupt requests, certainly
It is fixed whether the shared peripheral interrupt requests to be dispatched to the par-ticular processor.
It can be further understood by following detailed description and accompanying drawings about the advantages and spirit of the present invention.
Detailed description of the invention
Fig. 1 is the schematic diagram of an existing multicomputer system.
Fig. 2 is the schematic diagram according to the multicomputer system in one embodiment of the invention.
Fig. 3 (A) and Fig. 3 (B) are the schematic diagram of the interruption mask buffer corresponding to a processor.
Fig. 4 is the flow chart according to the processor management method in one embodiment of the invention.
Symbol description
100,200: multicomputer system
110,210: processor
120,220: Thread generation circuit
130,230: total scheduler
140,240: scheduler
150,250: interrupt control unit
2521: buffer
260: label determines circuit
270: adjustment circuit
191~194,291~294: application program
S41~S43: process step
It should be noted that attached drawing of the invention includes the functional block diagram that a variety of functional mould groups associated with each other are presented.
These attached drawings are not thin portion circuit diagram, and connecting line therein is only to indicate signal stream.Between functional element and/or program
A variety of interactive relationship are not necessarily intended to reach through the direct electrical connection beginning.In addition, the function of individual component be not necessarily intended to as
The mode being painted in attached drawing is distributed, and distributed block is not necessarily intended to the realization of distributed electronic component.
Specific embodiment
A specific embodiment according to the present invention is a kind of multicomputer system, and schematic diagram is illustrated in Fig. 2.Multiprocessor
System 200 includes that N number of processor (is denoted as 2101、2102、…、210N, be referred to as processor 210, N is integer greater than one), one
Thread generation circuit 220, a total scheduler 230, N number of scheduler (are denoted as 2401、2402、…、240N, it is referred to as scheduler
240), an interrupt control unit 250, one label determines circuit 260 and an adjustment circuit 270.
The function that label determines circuit 260 can be described in detail below.Thread generation circuit 220, which is responsible for receiving, comes from multiple applications
The Thread of program 291~294 is requested, and generates the Thread that processor 210 will be transferred to execute accordingly.In multicomputer system
In 200, when Thread generation circuit 220, which receives, generates the request of Thread for some application program, it will receive
The relevent informations such as attribute or the Thread itself attribute of application program are stated, and this information is supplied to label and determines circuit
260.Label determines that circuit 260 determines that an instantaneity marks according to above-mentioned attribute at least one for this Thread, to mark
This new Thread is needed after starting to be performed by the instant urgent degree completed, should not interrupted.In practice, instantaneity label
It can be a binary flags.For example, label determines that circuit 260 can be set: the content of the flag is one table of binary system
Show that this Thread indicates that this Thread has low instantaneity with high instantaneity, the content of the flag for binary zero.For example, with
Application attribute collocation Thread attribute itself and generate instantaneity label can using a range between 0 to 1
Number, numerical value is bigger to indicate higher instantaneity.
In one embodiment, it is main that the application attribute that label decision circuit 260 judges accordingly can be application program
The data type of processing, and mark and determine that circuit 260 is designed to: as long as the application for continuously playing multi-medium data
Program (such as film playing program, song vocal accompaniment program ...), just assigns the label that its Thread corresponds to high instantaneity.Or
Person, author and the label of application program 291~294 determine that the circuit designers of circuit 260 can reach common understanding in advance, by applying
The Thread that programming person actively states clearly this application program in the basic information of an application program is after starting to be performed
It is no to need by instant completion, interrupt, allow label to determine that circuit 260 can obtain after the basic information of one application program of interpretation
Know any instantaneity label of the Thread that should assign this application program.In another embodiment, since same application is not
With time point, the data type of processing may be not quite similar, then mark and determine that circuit 260 can be answered according to Thread attribute same
It is marked with individual Threads of program.
The instantaneity label that label determines that circuit 260 is determined can be transmitted to Thread generation circuit 220.Receiving mark
After note determines the instantaneity label that circuit 260 provides, Thread generation circuit 220 will be generated and be sent out comprising this instantaneity mark
The new Thread (such as specific field that instantaneity label is written to new Thread) of note, transfers to total scheduler 230 to carry out
Distribution.Total scheduler 230 according in the queue of each processor 210 workload, the characteristic of processor etc. is determine should be as
What distribution Thread, operational logic are to have known to usually intellectual in application field belonging to the present invention, are not repeated in this, also
Scope of the invention is not construed as limiting.The respective scheduler 240 of each processor 210 can timing selection one from its queue
Thread (hereinafter referred to as preferential Thread) transfers to the processor to execute, such as unit of the fixed duty cycle, every one
Duty cycle reselects a preferential Thread.In the case where not needing to handle any interrupt requests, each processor 210 is
The arrangement for accepting its scheduler 240, in each section of duty cycle, execution scheduler 240 is selected preferential for the duty cycle
Thread.
Interrupt control unit 250 is responsible for receiving the interruption that the circuits (not being painted) such as memory, timer, image processor issue
Request, and it is communicated to processor 210.As it was earlier mentioned, specific aim interrupt requests are directed to the interrupt requests that par-ticular processor issues,
It can only be handled by the par-ticular processor, and shared peripheral interrupt requests are then that any of N number of processor 210 processor is ok
Processing.Different from the interrupt control unit 150 of Fig. 1, a buffer 252 is equipped in interrupt control unit 2501, to record place
Manage device 2101For the acceptance of shared peripheral interrupt requests.When assigning the disposal right of interrupt requests, 250 meeting of interrupt control unit
With reference to buffer 2521Content.More specifically, when buffer 2521The content video-stream processor 210 of storage1Be not suitable at present
Receive shared peripheral interrupt requests, the disposal right of shared peripheral interrupt requests just will not be dispatched to handle by interrupt control unit 250
Device 2101。
Referring to Fig. 2, adjustment circuit 270 is coupled to scheduler 2401Between interrupt control unit 250.Whenever scheduler
2401For processor 2101Select a preferential Thread, adjustment circuit 270 just according to the instantaneity of the preferential Thread mark come
Set buffer 2521Content, that is, setting processing device 2101Shared peripheral is interrupted during executing the preferential Thread
The acceptance of request.For example, circuit designers can enable buffer 2521Content be binary system one indicate processor 2101Nothing
Method receives shared peripheral interrupt requests, binary zero indicates processor 2101It can receive shared peripheral interrupt requests.If label
Determine that circuit 260 equally indicates high instantaneity, binary zero using binary system one to indicate low instantaneity, then adjustment circuit
270 instantaneities that can directly adopt preferential Thread mark to set buffer 2521Content.This means, handling has height
The processor of the preferential Thread of instantaneity label can not receive mutual circumferences interrupt requests, handle with low instantaneity mark
The processor of the preferential Thread of note can receive shared peripheral interrupt requests.In an embodiment, adjustment circuit 270 considers this
Instantaneity marks whether to point out that the instantaneity of preferential Thread is higher than a predetermined threshold level.For example, if label determines circuit
260 are marked using number of the ranges between 0 to 1 as instantaneity, and numerical value is bigger indicates higher instantaneity, then
Adjustment circuit 270, which can mark instantaneity, be considered as higher than 0.5 preferential Thread with high instantaneity, therefore by buffer 2521
Content setting be binary system one.Conversely, preferential Thread of the instantaneity label less than or equal to 0.5 can be adjusted circuit 270
It is considered as with low instantaneity, therefore by buffer 2521Content setting be binary zero.
Circuit 260, adjustment circuit 270 and buffer 252 are determined by label1Cooperation, processor 2101Handled tool
There is the Thread of high instantaneity just will not meet with the problem of being suspended because of the intervention of shared peripheral interrupt requests.In other words, when
Buffer 2521The content video-stream processor 210 of storage1Be not suitable for receiving shared peripheral interrupt requests, interrupt control unit 250 at present
It will be to processor 2101Shared peripheral interrupt requests are covered, directional processors 210 are only allowed1Specific aim interrupt requests interrupt
Processor 2101The Thread handled.
In practice, interrupt control unit 250 can be remembered using mask buffer (interrupt mask register) is interrupted
Processor 210 is recorded for the acceptance of various interrupt requests, and buffer 2521Function can be incorporated into corresponding to processor
2101Interruption mask buffer in.For example, it is assumed that processor 2101The interrupt requests being likely to be received share 15 kinds,
Wherein there are three types of be specific aim interrupt requests, 12 kinds be shared peripheral interrupt requests.Corresponding to processor 2101Interruption hide
Cover buffer may include the storage space of 15 bits (hereinafter referred to as mask bit), be for recording this 15 kinds of interrupt requests
It is no can be by processor 2101It responds.When processor 2101When can receive a certain interrupt requests, the mask corresponding to the interrupt requests
Bit is set to binary zero.Conversely, working as processor 2101When cannot receive a certain interrupt requests, asked corresponding to the interruption
The mask bit asked is set to binary system one.
Adjustment circuit 270 can be endowed modification and correspond to processor 2101Interruption mask buffer content ability.
Fig. 3 (A) and Fig. 3 (B) are corresponding to processor 2101Interruption mask buffer schematic diagram.When adjustment circuit 270 determines to arrange
Journey device 2401The preferential Thread selected has high instantaneity, and adjustment circuit 270 can will correspond to 12 kinds of shared peripherals and interrupt
The content of the mask bit of request is all set as binary system one, as shown in Fig. 3 (A), covers these interrupt requests whereby.Until place
Manage device 2101The duty cycle of this preferential Thread is terminated, scheduler 2401When will reselect preferential Thread, adjustment circuit
This 12 mask bits are reset to binary zero by 270.Conversely, when adjustment circuit 270 determines scheduler 2401Choosing
Preferential Thread out has low instantaneity, and adjustment circuit 270 can be failure to actuate, and the content of this 12 mask bits is enabled to keep
In binary zero, as shown in Fig. 3 (B).In that case, when there are any shared peripheral interrupt requests, processor 2101
It will go to strive for the disposal right of this interrupt requests.
In an embodiment, different types of shared peripheral interrupt requests can be endowed the different priority of height.It is certain
The priority of the shared peripheral interrupt requests of type could possibly be higher than the Thread of above-mentioned high instantaneity.For example, it is assumed that known
There are four types of priorities with higher in above-mentioned 12 kinds of shared peripheral interrupt requests, then adjustment circuit 270 is determining scheduler
2401It, can be only by the masking bit of other eight kinds of shared peripheral interrupt requests after the preferential Thread selected has high instantaneity
Content setting be binary system one, rather than the content of the masking bit of all shared peripheral interrupt requests is all set as binary system
One.In that case, circuit 260, adjustment circuit 270 and buffer 252 are determined by label1Cooperation, processor 2101Institute
The probability that the Thread with high instantaneity of processing is suspended because shared peripheral interrupt requests intervene can be lowered, rather than complete
It totally disappeared and remove.
In practice, interrupt control unit 250 itself, also may modification interruption mask during handling various interrupt requests
The content of buffer, such as in processor 2101It is handling corresponding masking bit during a certain interrupt requests
Content setting be binary system one, Detailed Operation mode be persond having ordinary knowledge in the technical field of the present invention known to,
It is not repeated in this.
It should be noted that adjust the way of interrupt requests acceptance using adjustment circuit 270, can quilt cover be used in not only one
On a processor.For example, circuit designers also can be processor 2102Another setting one is coupled to scheduler 2402With interruption
Adjustment circuit 270 between controller 250, reduce has the Thread of high instantaneity by processor 210 whereby2The machine of pause
Rate.Ideally, in the case where multicomputer system 200 includes N number of processor 210, settable N number of adjustment circuit 270 is allowed every
A processor 210 is all collocated with an adjustment circuit 270.In order to retain at least one processor 210 in processing shared peripheral
Disconnected request, scheduler 240 are designed to the mechanism with communication and coordination each other, by preferential Thread is suitably selected, enable same
The preferential Thread that one time point at most had (N-1) a processor to have high instantaneity in processing.Alternatively, total scheduler 230 can quilt
It is designed as that the state of each queue can be referred to when assigning Thread, not allowing N number of queue all to be arranged in the same time has the high instantaneity of tool
Thread.In practice, circuit designers can rule of thumb rule and practical application, determine the quantity of adjustment circuit 270.
In practical applications, label determines that circuit 260 and adjustment circuit 270 can be implemented as fixed and/or can program
Change numerical digit logic circuit, includes programmable logic gate array, application-specific integrated circuit, microcontroller, microprocessor, numerical digit
Signal processor, with other necessary circuitries.
In addition, scope of the invention is not limited to control multicomputer system with the operating system of certain specific kenel
200。
It is according to another embodiment of the present invention a kind of processor management method, to unification multicomputer system
In a processor, flow chart is illustrated in Fig. 4.Firstly, step S41 is to receive to ask corresponding to the multiple of multiple application programs
It asks, generates multiple Threads accordingly, and be that the Thread determines that an instantaneity marks for an attribute of each Thread.Step
S42 is then from being dispatched to select a preferential Thread in multiple Threads of the par-ticular processor, and according to the preferential Thread
The instantaneity label, set the par-ticular processor connecing for shared peripheral interrupt requests when executing the preferential Thread
It is spent.Then, according to step S43 the par-ticular processor for the acceptance of the shared peripheral interrupt requests, decide whether by
The shared peripheral interrupt requests are dispatched to the par-ticular processor.
Persond having ordinary knowledge in the technical field of the present invention was it is understood that previously when introducing multicomputer system 200
The various operation changes of description can also be applied to the processor management method in Fig. 4, and details repeats no more.
Still another embodiment according to the present invention is a kind of non-transient computer-readable storage medium, is applied to a many places
Device system is managed, wherein storing the procedure code that can be read and be executed by a processor.The procedure code system is to manage many places
Manage the processor in device system.In the procedure code, one first procedure code corresponds to the more of multiple application programs to receive
A request generates multiple Threads accordingly, and is that the Thread determines that an instantaneity marks for an attribute of each Thread.
One second procedure code selects a preferential Thread to be dispatched to certainly in multiple Threads of the par-ticular processor, and excellent according to this
The instantaneity label for first carrying out thread, sets the par-ticular processor and one shared peripheral is interrupted when executing the preferential Thread
The acceptance of request.One third procedure code to the acceptance according to the par-ticular processor for the shared peripheral interrupt requests,
Decide whether the shared peripheral interrupt requests being dispatched to the par-ticular processor.
In practice, above-mentioned non-transient computer readable media can be electronics, magnetism and optical disc drive, such as read-only deposit
Reservoir (ROM), random access memory (RAM), CD-ROM, DVD, tape, soft dish, hard disc.For example, above procedure code can
To be written as some of the procedure code of an operating system.In addition, the procedure code can be realized using various program languages.
Persond having ordinary knowledge in the technical field of the present invention was it is understood that previously when introducing multicomputer system 200
The various operation changes of description can also be applied to above-mentioned non-transient computer readable media, and details repeats no more.
By the detailed description of embodiments above, it would be desirable to more clearly describe feature and spirit of the invention, and not be
Scope of the invention is limited with above-mentioned revealed specific embodiment.On the contrary, each the purpose is to wish to cover
Kind change and tool equality is arranged in the scope of the scope of the patents to be applied of the invention.
Claims (9)
1. a kind of multicomputer system, includes:
Multiple processors；
One buffer, wherein record has receiving of the par-ticular processor for a shared peripheral interrupt requests in multiple processor
Degree；
One Thread generation circuit, to receive multiple requests, multiple the holding of multiple processor execution will be transferred to accordingly by generating
Row thread, multiple Thread correspond to multiple application programs；
One label determines circuit, the Thread generation circuit is coupled to, whenever the Thread generation circuit receives multiple ask
Ask for the moment, the label determine circuit according at least to an attribute of the corresponding Thread determine by include in the Thread one
Instantaneity label；
One scheduler selects the par-ticular processor by the one of execution to be dispatched to certainly in multiple Threads of the par-ticular processor
Preferential Thread；
One adjustment circuit is coupled between the scheduler and the interrupt control unit, to instant according to this of the preferential Thread
Property label, until the buffer sets the par-ticular processor when executing the preferential Thread for the shared peripheral interrupt requests
Acceptance；And
One interrupt control unit multiple interrupt requests are dispatched to multiple processor, and is asked assigning multiple interruption
The acceptance for being recorded the buffer when asking accounts for.
2. multicomputer system as described in claim 1, which is characterized in that if instantaneity label points out the preferential Thread
Instantaneity be higher than a predetermined threshold level, the adjustment circuit to the buffer by the par-ticular processor for the shared peripheral interrupt
The acceptance of request adjusts are as follows: the par-ticular processor does not receive any shared peripheral interruption when executing the preferential Thread asks
It asks.
3. multicomputer system as described in claim 1, which is characterized in that if instantaneity label points out the preferential Thread
Instantaneity be lower than a predetermined threshold level, the adjustment circuit to the buffer is by the par-ticular processor for the acceptance of interruption
Adjustment are as follows: the par-ticular processor is subjected to the shared peripheral interrupt requests when executing the preferential Thread.
4. a kind of processor management method, to the par-ticular processor in unification multicomputer system, the management method packet
Contain:
(a) the multiple requests for corresponding to multiple application programs are received, generate multiple Threads accordingly, and for each Thread
One attribute is that the Thread determines that an instantaneity marks；
(b) it is dispatched to select a preferential Thread in multiple Threads of the par-ticular processor certainly, and according to the preferential Thread
The instantaneity label, set the par-ticular processor connecing for shared peripheral interrupt requests when executing the preferential Thread
It is spent；And
(c) according to the par-ticular processor for the acceptance of the shared peripheral interrupt requests, deciding whether will be in the shared peripheral
Disconnected request is dispatched to the par-ticular processor.
5. management method as claimed in claim 4, which is characterized in that step (c) includes:
If the instantaneity label point out the preferential Thread instantaneity be higher than a predetermined threshold level, by the par-ticular processor for
The acceptance of the shared peripheral interrupt requests adjusts are as follows: the par-ticular processor does not receive any total when executing the preferential Thread
With periphery interrupt requests.
6. management method as claimed in claim 4, which is characterized in that step (c) includes:
If instantaneity label point out the instantaneity of the preferential Thread lower than a predetermined threshold level, by the par-ticular processor for
The acceptance of the shared peripheral interrupt requests adjusts are as follows: the par-ticular processor receives all kinds when executing the preferential Thread
Shared peripheral interrupt requests.
It, can be by a processing wherein storing 7. a kind of non-transient computer-readable storage medium is applied to a multicomputer system
The procedure code that device reads and executes, the procedure code is to manage the par-ticular processor in the multicomputer system and include:
One first procedure code generates multiple Threads, and needle to receive the multiple requests for corresponding to multiple application programs accordingly
An attribute to each Thread is that the Thread determines that an instantaneity marks；
One second procedure code selects a preferential Thread to be dispatched to certainly in multiple Threads of the par-ticular processor, and root
It is marked according to the instantaneity of the preferential Thread, sets the par-ticular processor and share week for one when executing the preferential Thread
The acceptance of side interrupt requests；And
One third procedure code decides whether to the acceptance according to the par-ticular processor for the shared peripheral interrupt requests
The shared peripheral interrupt requests are dispatched to the par-ticular processor.
8. non-transient computer-readable storage medium as claimed in claim 7, which is characterized in that the third procedure code is encoded
Are as follows:
If the instantaneity label point out the preferential Thread instantaneity be higher than a predetermined threshold level, by the par-ticular processor for
The acceptance of the shared peripheral interrupt requests adjusts are as follows: the par-ticular processor does not receive any total when executing the preferential Thread
With periphery interrupt requests.
9. non-transient computer-readable storage medium as claimed in claim 7, which is characterized in that the third procedure code is encoded
Are as follows:
If instantaneity label point out the instantaneity of the preferential Thread lower than a predetermined threshold level, by the par-ticular processor for
The acceptance of the shared peripheral interrupt requests adjusts are as follows: the par-ticular processor receives all kinds when executing the preferential Thread
Shared peripheral interrupt requests.
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| US11327690B2 (en) | 2019-11-13 | 2022-05-10 | Google Llc | Enhanced input of machine-learning accelerator activations |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1720503A (en) * | 2002-10-15 | 2006-01-11 | 沙桥技术有限公司 | Method and apparatus for high speed cross-thread interrupts in a multithreaded processor |
| CN101002176A (en) * | 2004-07-23 | 2007-07-18 | 松下电器产业株式会社 | Real time processing software control device and method |
| US20100242041A1 (en) * | 2009-03-17 | 2010-09-23 | Qualcomm Incorporated | Real Time Multithreaded Scheduler and Scheduling Method |
| CN101911019A (en) * | 2008-01-18 | 2010-12-08 | 库卡罗伯特有限公司 | Computer system, control apparatus for a machine, in particular for an industrial robot, and industrial robot |
| CN103677997A (en) * | 2012-09-21 | 2014-03-26 | 宏达国际电子股份有限公司 | Multi-core device and multi-thread scheduling method thereof |
| CN106371894A (en) * | 2016-08-31 | 2017-02-01 | 华为技术有限公司 | Collocation method, collocation device and data processing server |
| US9830187B1 (en) * | 2015-06-05 | 2017-11-28 | Apple Inc. | Scheduler and CPU performance controller cooperation |
-
2017
- 2017-12-01 CN CN201711250217.8A patent/CN109871275A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1720503A (en) * | 2002-10-15 | 2006-01-11 | 沙桥技术有限公司 | Method and apparatus for high speed cross-thread interrupts in a multithreaded processor |
| CN101002176A (en) * | 2004-07-23 | 2007-07-18 | 松下电器产业株式会社 | Real time processing software control device and method |
| CN101911019A (en) * | 2008-01-18 | 2010-12-08 | 库卡罗伯特有限公司 | Computer system, control apparatus for a machine, in particular for an industrial robot, and industrial robot |
| US20100242041A1 (en) * | 2009-03-17 | 2010-09-23 | Qualcomm Incorporated | Real Time Multithreaded Scheduler and Scheduling Method |
| CN102341780A (en) * | 2009-03-17 | 2012-02-01 | 高通股份有限公司 | Real-time multithreaded scheduler and scheduling method |
| CN103677997A (en) * | 2012-09-21 | 2014-03-26 | 宏达国际电子股份有限公司 | Multi-core device and multi-thread scheduling method thereof |
| US9830187B1 (en) * | 2015-06-05 | 2017-11-28 | Apple Inc. | Scheduler and CPU performance controller cooperation |
| CN106371894A (en) * | 2016-08-31 | 2017-02-01 | 华为技术有限公司 | Collocation method, collocation device and data processing server |
Non-Patent Citations (1)
| Title |
|---|
| 周密等: "基于Windows NT开放式数控系统实时扩展技术研究", 《计算机工程与应用》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11327690B2 (en) | 2019-11-13 | 2022-05-10 | Google Llc | Enhanced input of machine-learning accelerator activations |
| TWI767310B (en) * | 2019-11-13 | 2022-06-11 | 美商谷歌有限責任公司 | Processor, computing method, and computer program product |
| US11762602B2 (en) | 2019-11-13 | 2023-09-19 | Google Llc | Enhanced input of machine-learning accelerator activations |
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