CN109859121A - A kind of image block bearing calibration and device based on FPGA platform - Google Patents
A kind of image block bearing calibration and device based on FPGA platform Download PDFInfo
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- CN109859121A CN109859121A CN201910019356.2A CN201910019356A CN109859121A CN 109859121 A CN109859121 A CN 109859121A CN 201910019356 A CN201910019356 A CN 201910019356A CN 109859121 A CN109859121 A CN 109859121A
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Abstract
The invention belongs to industrial detection technical fields, disclose a kind of image block bearing calibration based on FPGA platform and device, target image is divided into multiple rectangular blocks, rectangular block is as region of interest ROI, then each rectangular block is divided into two right angled triangles up and down according to leading diagonal, each right angled triangle constitutes a block image, is arranged according to serial number multiple block images, and carry out mapping processing to each block image；Device includes the AXI4 bus for being integrated in FPGA, AXI4-lite bus, stream generation module, data loading module, mapping block, data processing module.The present invention is able to solve image rectification in the prior art and is difficult to speed and effect dual the problem of taking into account, and can preferably meet industrial requirements.
Description
Technical field
The present invention relates to industrial detection technical field more particularly to a kind of image block bearing calibrations based on FPGA platform
And device.
Background technique
In industrial vision application, Image Acquisition is carried out by image shot by camera, the original image that acquires at present or
It is more or it is few there is distortion, distortion be by the reason of camera itself and the reasons such as camera shooting angle cause, the shooting of this situation
Picture needs to do correction process in subsequent detection, can meet testing requirements below.
More for image rectification project plan comparison at present, the geometric correction of imagery includes distortion correction, perspective transform and affine
Transformation, these algorithms comparative maturity itself are all based on primal algorithm under many applications and are developed, and based on PC platform into
Row exploitation, in the case where requirement of real-time is relatively high, cannot meet the requirements.In addition, there are also be based on FPGA platform at present
The correcting algorithm case of design, relative to PC algorithm, some improve and accelerate, but generally speaking, are carried out for algorithm itself
Certain approximate processing is realized or done, cannot accomplish speed mostly and effect is dual takes into account, field of industry detection application is come
It says, is far from being optimal effect, in current panel detection field, application effect is not very good.
Summary of the invention
The embodiment of the present application solves existing by providing a kind of image block bearing calibration based on FPGA platform and device
There is in technology image rectification be difficult to speed and effect dual the problem of taking into account.
The embodiment of the present application provides a kind of image block bearing calibration based on FPGA platform, target image is divided into more
Then each rectangular block is divided into up and down by a rectangular block, the rectangular block as region of interest ROI according to leading diagonal
Two right angled triangles, each right angled triangle constitutes a block image, to multiple block images according to serial number
It is arranged, and mapping processing is carried out to each block image.
Preferably, mapping normalized is carried out to the right angled triangle, obtains isosceles right triangle, the isosceles
Right angled triangle is as the block image.
Preferably, the point in the block image is subjected to matrix operation with correction parameter, obtained in target image ROI
The coordinate of corresponding points of the point in original image ROI, the grey scale pixel value of corresponding points is obtained by bilinear interpolation, by what is obtained
The grey scale pixel value is filled at the target image respective coordinates before mapping, the block image after being corrected.
Preferably, arrangement processing is carried out according to serial number to the block image after multiple corrections, the target figure after being corrected
Picture.
On the other hand, the embodiment of the present application provides a kind of image block means for correcting based on FPGA platform, including integrated
In the AXI4 bus of FPGA, AXI4-lite bus, stream generation module, data loading module, mapping block, data processing module；
The AXI4 bus is for load bus parameter, reading original image, write-in target image；
The AXI4-lite bus is for accessing register parameters；
The bus parameter that the stream generation module is used to read in DDR is divided into three data flows, three data stream difference
For original image piecemeal ROI data stream, correction parameter data flow, target image piecemeal ROI data stream, and by the original image
Piecemeal ROI data, which is spread, is handed to the data loading module, and the correction parameter data flow is transferred to the mapping block, will
The target image piecemeal ROI data, which is spread, is handed to the data processing module；
The data loading module is used to read ROI information from DDR according to the original image piecemeal RIO data flow,
And the ROI information is transferred to the mapping block in pipelined fashion；
The mapping block obtains correction parameter, root for receiving the ROI information, according to the correction parameter data flow
According to the ROI information, the point in target image ROI is subjected to matrix operation with the correction parameter, is obtained in target image ROI
Corresponding points of the point in original image ROI coordinate, the grey scale pixel value of corresponding points is obtained by bilinear interpolation, will be obtained
The grey scale pixel value be filled at the target image respective coordinates before mapping, and pass data in pipelined fashion
The data processing module；
The data processing module is for receiving the data flow from the mapping block, according to the target image piecemeal
RIO data flow reads image block information from DDR, is arrived the Data Integration of mapping block according to described image blocking information
In the region corresponding target image RIO, target image is obtained, and the target image is written in DDR.
Preferably, the register parameters include: the resolution ratio of original image, the resolution ratio of target image, image block
Size, the offset of block initial address.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
In the embodiment of the present application, image block is right angled triangle by the advantage for making full use of FPGA, and by piecemeal
Data accomplish full stream treatment, and every a line can accomplish Burst accessing in each piece, and access DDR is high-efficient.The present invention
It realizes that the mode of local triangle affine transformation carries out image rectification based on FPGA platform, can preferably meet industrial requirements.
Detailed description of the invention
It, below will be to needed in embodiment description in order to illustrate more clearly of the technical solution in the present embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is one embodiment of the present of invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is that a kind of module connection of image block means for correcting based on FPGA platform provided in an embodiment of the present invention is shown
It is intended to；
Fig. 2 is target image point in a kind of image block bearing calibration based on FPGA platform provided in an embodiment of the present invention
The schematic diagram of block；
Fig. 3 is piecemeal mapping in a kind of image block bearing calibration based on FPGA platform provided in an embodiment of the present invention
Schematic diagram；
Fig. 4 is to map normalization in a kind of image block bearing calibration based on FPGA platform provided in an embodiment of the present invention
For the schematic diagram of isosceles right triangle.
Specific embodiment
In order to better understand the above technical scheme, in conjunction with appended figures and specific embodiments to upper
Technical solution is stated to be described in detail.
A kind of image block means for correcting based on FPGA platform is present embodiments provided, as shown in Figure 1, including three
AXI4 bus is respectively used to bus parameter load, original image is read and target image write-in；Including an AXI4-lite
Bus, for accessing register parameters.
Image block means for correcting based on FPGA platform is handled data by four modules, including stream generates mould
Block, data loading module, mapping block, data processing module.
The bus parameter that the stream generation module is used to read in DDR is divided into three data flows, is original image respectively
Piecemeal ROI data stream, correction parameter data flow, target image piecemeal ROI data stream.
The data loading module is used for according to the original image piecemeal RIO data flow, by AXI4 bus, from DDR
Middle reading ROI information (width and height that ROI information mainly includes ROI (Regionofinterest, area-of-interest)), so
The ROI information is transmitted to Subordinate module in pipelined fashion afterwards.
The mapping block is used for through correction parameter (coming from the correction parameter data flow) and institute in target image ROI
Operation is a little carried out, corresponding points coordinate of all the points in target image ROI in original image ROI is found, is then carried out double
Linear interpolation finds the grey scale pixel value of corresponding points, is subsequently filled in the corresponding point of target image, then side of the data to flow
Formula flows into Subordinate module.
The data processing module is used to receive the number calculated after the target image piecemeal ROI data stream and mapping
According to stream, and by the Data Integration of mapping block to corresponding target image RIO, be then written in DDR.I.e. according to target image
Piecemeal ROI data stream obtains ROI relevant information, is then successively loaded into the data of previous stage module in ROI region, owns
ROI while filling while DDR is written, finally obtain target image.Generally speaking, the function of the data processing module is will to handle
Image is arranged according to sequencing afterwards, is formed a data flow, is endlessly transmitted to post-module.
The correction of image block involved in above-mentioned data processing is as follows:
It when image is distorted, is handled by partitioned mode, target image is divided into rectangle one by one first
Then each rectangle is divided into two right angled triangles according to leading diagonal by block, be divided into two right angled triangles up and down.Target figure
Picture resolution ratio is M*N, and wherein M indicates that row, N indicate to arrange, and the image of M*N is carried out piecemeal, gridX table according to gridY and gridX
That shows is horizontally oriented rectangle block length, and gridY indicates the length of vertically oriented rectangle block, then by gridX*gridY size
Rectangular block is divided into two right angled triangles up and down.As shown in Fig. 2, being target image partitioned organization figure, a part is only provided here
Data block, and block image is arranged according to serial number, mapping processing is carried out to each gore respectively.
Piecemeal correction is that target image is divided into two right angle trigonometries up and down and is handled according to coordinate relationship, right angle three
Corresponding coordinate and correction matrix parameter carry out matrix operation in angular, find the coordinate of its corresponding original image, then will
Original image corresponding points coordinate carries out bilinear interpolation, and the gray value of the coordinate points after interpolation is filled into the target figure before mapping
As obtaining the gray value of right angled triangle respective coordinates at coordinate, whole picture correction image is finally obtained.As indicated at 3, the left side in figure
It is original image piecemeal situation, the right is target image piecemeal situation.
Carrying out practically process is as follows:
(1) register parameters handled by register loading module (register loading module, that is, AXI4_LITE interface),
Resolution ratio including original image and target image, image block size, block initial address offset etc..Resolution parameter is for matching
Different size of image is set, the offset of block initial address is used for operation, and rectangular block upper left fixed point is offset address.
(2) judgment module whether ready, after ready, starting module reads bus parameter from DDR, generates through overcurrent
After module, it is divided into three data flows, respectively original image piecemeal ROI data stream, correction parameter data flow, target image piecemeal
ROI data stream；
(3) data loading module takes corresponding data according to original image piecemeal ROI data stream from DDR, passes to down
Grade module；
(4) mapping block is for carrying out coordinate mapping, and it is right in corresponding points and original image ROI in target image ROI to find
The relationship that should be put carries out bilinear interpolation, then obtains the gray value of respective coordinates；
(5) data processing module carries out load to the data of higher level's module and arrangement is handled, and is written in DDR；
(6) drive whether the done signal of logic judgment module is drawn high, drawing high indicates that data write-in is completed.
The present invention proposes that the method for correcting image based on FPGA platform is to divide the image into local triangle, and it is imitative to carry out triangle
Transformation is penetrated, the method can correct any fault image, including different distortion degrees and different distortion types, also be no longer limited to
The distortion for considering camera is barrel distortion, pincushion distortion or perspective distortion etc., and the invention can be corrected well
Effect, and speed is fast, and the time of requirements of process can be greatly reduced in industrial camera detection.
Distortion correction and perspective transform algorithm, which exist, carries out out-of-order access to image data, this compares consumption on PC
When, and access data cannot accomplish stream treatment, and the present invention makes full use of the advantage of FPGA, divides the image into fritter to locate
It manages, flowing water completely is handled between each fritter, moreover, the effective district of out-of-order access images becomes smaller after being divided into fritter, is visited
The speed asked becomes faster.
For affine transformation, relative to rectangular block, transformation parameter number can be effectively reduced using corner block, when point
The advantages of when block is excessive, each piece has parameter, at this time just better reflects corner block.
The present invention emphasizes for target image to be divided into right angled triangle, is preferably also normalized to right angled triangle mapping
Isosceles right triangle, it is specific as shown in figure 4, what wherein the figure on the left side indicated is original image situation, what intermediate figure indicated
It is the normalized isosceles right triangle of mapping, two right angle edge lengths are all 1, and the right indicates target image piecemeal situation.On
Stating processing can simplify calculating, make to calculate more convenient.
To sum up, the present invention makes full use of the advantage of FPGA, accomplishes at full flowing water by image block, and by the data of piecemeal
Reason, and every a line can accomplish that Burst accessing, access DDR are high-efficient in each piece.In addition, being right angle by target image piecemeal
Then right angled triangle is mapped on a normalization isosceles right triangle and handles, advanced optimizes meter by triangle
Calculation process makes to calculate simpler convenience, and handles on FPGA more convenient, and can save resource, therefore the present invention
It can accomplish that speed and the dual of effect are taken into account.
A kind of image block bearing calibration and device based on FPGA platform provided in an embodiment of the present invention includes at least such as
Lower technical effect:
1) recoverable distortion of the present invention and perspective, do not need to do two sets of algorithms of distortion correction and perspective transform；
2) for the correcting algorithm of the opposite PC platform of the present invention, correction course can be efficiently quickly finished, is met real-time
Property require；
3) the opposite existing case of FPGA of the present invention, calibration result is more preferable, and less using logical resource, speed is more excellent；
4) image block bearing calibration favorable expandability provided by the invention has versatility.
It should be noted last that the above specific embodiment is only used to illustrate the technical scheme of the present invention and not to limit it,
Although being described the invention in detail referring to example, those skilled in the art should understand that, it can be to the present invention
Technical solution be modified or replaced equivalently, without departing from the spirit and scope of the technical solution of the present invention, should all cover
In the scope of the claims of the present invention.
Claims (6)
1. a kind of image block bearing calibration based on FPGA platform, which is characterized in that target image is divided into multiple rectangles
Then each rectangular block is divided into upper and lower two directly according to leading diagonal as region of interest ROI by block, the rectangular block
Angle triangle, each right angled triangle constitute a block image, are arranged according to serial number multiple block images
Column, and mapping processing is carried out to each block image.
2. the image block bearing calibration according to claim 1 based on FPGA platform, which is characterized in that the right angle
Triangle carries out mapping normalized, obtains isosceles right triangle, the isosceles right triangle is as the block diagram
Picture.
3. the image block bearing calibration according to claim 1 or 2 based on FPGA platform, which is characterized in that will be described
Point and correction parameter in block image carry out matrix operation, obtain pair of the point in target image ROI in original image ROI
The coordinate that should be put is obtained the grey scale pixel value of corresponding points by bilinear interpolation, the obtained grey scale pixel value is filled into
At target image respective coordinates before mapping, the block image after being corrected.
4. the image block bearing calibration according to claim 3 based on FPGA platform, which is characterized in that multiple corrections
Block image afterwards carries out arrangement processing according to serial number, the target image after being corrected.
5. a kind of image block means for correcting based on FPGA platform, which is characterized in that appoint for realizing in such as claim 1-4
Image block bearing calibration described in one based on FPGA platform, device include the AXI4 bus for being integrated in FPGA, AXI4-lite
Bus, stream generation module, data loading module, mapping block, data processing module；
The AXI4 bus is for load bus parameter, reading original image, write-in target image；
The AXI4-lite bus is for accessing register parameters；
The bus parameter that the stream generation module is used to read in DDR is divided into three data flows, and three data streams are former respectively
Beginning image block ROI data stream, correction parameter data flow, target image piecemeal ROI data stream, and by the original image piecemeal
ROI data, which is spread, is handed to the data loading module, and the correction parameter data flow is transferred to the mapping block, will be described
Target image piecemeal ROI data, which is spread, is handed to the data processing module；
The data loading module is used for according to the original image piecemeal RIO data flow, the reading ROI information from DDR, and with
The ROI information is transferred to the mapping block by the mode of assembly line；
The mapping block obtains correction parameter for receiving the ROI information, according to the correction parameter data flow, according to institute
ROI information is stated, the point in target image ROI is subjected to matrix operation with the correction parameter, obtains the point in target image ROI
The coordinate of corresponding points in original image ROI obtains the grey scale pixel value of corresponding points, the institute that will be obtained by bilinear interpolation
It states at the target image respective coordinates before grey scale pixel value is filled into mapping, and passes data in pipelined fashion described
Data processing module；
The data processing module is for receiving the data flow from the mapping block, according to the target image piecemeal RIO
Data flow, from DDR read image block information, according to described image blocking information by the Data Integration of mapping block to correspondence
The region target image RIO in, obtain target image, and will the target image be written DDR in.
6. the image block means for correcting according to claim 5 based on FPGA platform, which is characterized in that the register
Parameter includes: the resolution ratio of original image, the resolution ratio of target image, image block size, the offset of block initial address.
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Application publication date: 20190607 |