CN109842410B - Frequency divider and transceiver including the same - Google Patents
Frequency divider and transceiver including the same Download PDFInfo
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- CN109842410B CN109842410B CN201811424661.1A CN201811424661A CN109842410B CN 109842410 B CN109842410 B CN 109842410B CN 201811424661 A CN201811424661 A CN 201811424661A CN 109842410 B CN109842410 B CN 109842410B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
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Abstract
A frequency divider may include: a core circuit comprising a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop frequency divides a frequency of a clock signal received through a control terminal of the flip-flop, wherein the core circuit is configured to: outputting a divided signal based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first signal and the second signal having the same division ratio and different phases, and feeding back the divided signal through an input of each of the first flip-flop loop and the second flip-flop loop; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal generated by correcting a duty of the frequency-divided signal; and an output circuit outputting a first output signal which is a signal amplified from the differential output signal and a second output signal which is a quadrature signal of the first output signal.
Description
Cross Reference to Related Applications
The present application claims priority from korean patent application No. 10-2017-0161007, filed on the south of the Korean Intellectual Property Office (KIPO) at 11.28 of 2017, and korean patent application No. 10-2018-0078149, filed on the south of the 2018.7, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
The present inventive concept relates to a frequency divider and a transceiver including the same, and more particularly, to a frequency divider correcting a duty ratio, and a transceiver including the same.
Background
The frequency divider divides the frequency of the input signal and generates an output signal having a frequency lower than the frequency of the input signal. For example, a frequency divider is a circuit that receives an input signal, divides it and generates an output signal. The frequency divider may be used in clock generation circuits such as local oscillators, phase Locked Loops (PLLs), frequency synthesizers, and the like, as well as various integrated circuits including clock generation circuits. The frequency divider may be classified as an integer divider dividing the frequency by an integer N or a fractional divider dividing the frequency by, for example, n.5. In an integer divider, a pulling effect (pull effect) may occur in a Radio Frequency (RF) transceiver to which a signal source having a large output is applied. In the fractional divider, when a signal source having a large output is applied thereto, a pull effect may not occur. However, fractional dividers delay the periodic signal and frequency spurs that occur during the dividing process, which is an unintended frequency.
In addition, fractional dividers typically output a duty cycle of 40% or 60%, and may not be readily applicable to systems requiring a 50% duty cycle.
Disclosure of Invention
According to an exemplary embodiment of the inventive concept, there is provided a frequency divider including: a core circuit comprising a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop frequency divides a frequency of a clock signal received through a control terminal of the flip-flop, wherein the core circuit is configured to: outputting a divided signal based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first signal and the second signal having the same division ratio and different phases, and feeding back the divided signal through an input of each of the first flip-flop loop and the second flip-flop loop; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal generated by correcting a duty of the frequency-divided signal; and an output circuit outputting a first output signal which is a signal amplified from the differential output signal and a second output signal which is a quadrature signal of the first output signal.
According to an exemplary embodiment of the inventive concept, there is provided a frequency divider including: a core circuit that receives a clock signal and outputs a frequency-divided signal generated by dividing the frequency of the clock signal; and a duty ratio correction circuit receiving the frequency-divided signal and outputting a differential output signal having a new duty ratio according to the decision level, wherein the duty ratio correction circuit adjusts the original duty ratio so that the differential output signal has the new duty ratio by performing feedback on the differential output signal and adjusting an edge slope of the frequency-divided signal based on the fed-back differential output signal.
According to an exemplary embodiment of the inventive concept, there is provided a transceiver including: a core circuit that receives a clock signal, outputs a frequency-divided signal generated by dividing a frequency of the clock signal, and includes a first flip-flop loop and a second flip-flop loop, each of the first flip-flop loop and the second flip-flop loop including a plurality of flip-flops; and a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal generated by correcting the duty of the frequency-divided signal.
Drawings
The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
Fig. 1 is a block diagram of a frequency divider according to an exemplary embodiment of the inventive concept;
Fig. 2 is a waveform diagram of signals of a frequency divider according to an exemplary embodiment of the inventive concept;
fig. 3A and 3B are circuit diagrams of a frequency division core circuit according to an exemplary embodiment of the inventive concept;
Fig. 4 is a timing diagram of signals input or output by a frequency division core circuit according to an exemplary embodiment of the inventive concept;
fig. 5 is a circuit diagram of a duty cycle correction circuit according to an exemplary embodiment of the inventive concept;
fig. 6 is a timing diagram of signals generated by a duty cycle correction circuit according to an exemplary embodiment of the inventive concept;
fig. 7A is a circuit diagram of an output circuit according to an exemplary embodiment of the inventive concept;
fig. 7B is a diagram of a logic circuit included in an output circuit according to an exemplary embodiment of the inventive concept;
Fig. 8 is a timing diagram of signals generated by an output circuit according to an exemplary embodiment of the inventive concept;
Fig. 9 is a circuit diagram of an output circuit according to an exemplary embodiment of the inventive concept;
Fig. 10 is a circuit diagram of a driving voltage control circuit according to an exemplary embodiment of the inventive concept;
Fig. 11 is a graph of delay time when a driving voltage control circuit is operated according to an exemplary embodiment of the inventive concept; and
Fig. 12 is a block diagram of a transceiver according to an exemplary embodiment of the inventive concept.
Detailed Description
Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram of a frequency divider according to an exemplary embodiment of the inventive concept. Fig. 2 is a waveform diagram of signals of a frequency divider according to an exemplary embodiment of the inventive concept.
Referring to fig. 1, a frequency divider (frequency divider) 1000 may include a frequency division (divide) core circuit 100, a duty cycle correction circuit (duty correction circuit) 200, and an output circuit 300. The frequency division core circuit 100 may receive the clock signal CLK and output a frequency division signal s_div having a frequency division. The duty ratio correction circuit 200 receives the frequency-divided signal s_div and outputs differential output signals s_dp and s_dn each having a corrected duty ratio. The output circuit 300 receives the differential output signals s_dp and s_dn and outputs output signals s_i, s_ib, s_q, s_qb that are orthogonal to each other.
Referring to fig. 2, the clock signal CLK may be generated based on a signal output from the voltage controlled oscillator VCO. The frequency-divided signal s_div is calculated by dividing the frequency of the clock signal CLK by a specific value, and the duty ratio may be, for example, 40% or 60%. The differential output signals s_dp and s_dn may include a first differential output signal s_dp and a second differential output signal s_dn, and the differential output signals s_dp and s_dn may be signals inverted with respect to each other. The differential output signals s_dp and s_dn may correct the duty ratio of the frequency-divided signal s_div by using the duty ratio correction circuit 200. For example, the duty ratio correction circuit 200 may correct the frequency-divided signal s_div having a duty ratio of 40% to have a duty ratio of 50%. The quadrature signals may include first output signals s_i and s_ib and second output signals s_q and s_qb. The first output signals s_i and s_ib each have an in-phase component. For example, the first output signals s_i and s_ib have a phase similar to that of the first differential output signal s_dp. The second output signals s_q and s_qb each have a quadrature component. The second output signals s_q and s_qb each have a phase that is orthogonal to the first differential output signal s_dp. The first output signals s_i and s_ib may include I signals s_i and IB signals s_ib with a half-period gap (gap) therebetween. In other words, the I signal s_i and the IB signal s_ib are signals that are inverted with respect to each other. The second output signals s_q and s_qb may further include Q signals s_q and QB signals s_qb with a half-period gap therebetween.
Referring again to fig. 1, the frequency division core circuit 100 may include a plurality of flip-flops. The plurality of flip-flops may include a first flip-flop loop and a second flip-flop loop. Each flip-flop loop may receive a clock signal CLK. For example, the first flip-flop loop and the second flip-flop loop may output frequency modulated signals of the clock signal CLK. The frequency modulated signals output by the first and second trigger loops may have the same amplitude and different phases. In other words, the frequency modulated signal may be output in a phase shifted form. The frequency-divided signal s_div generated by dividing the frequency of the clock signal CLK may be output by summing the frequency-modulated signals output by the first flip-flop loop and the second flip-flop loop.
The duty ratio correction circuit 200 may correct the duty ratio of the frequency-divided signal s_div to have a specific value. According to an exemplary embodiment of the inventive concept, the duty ratio correction circuit 200 may apply the frequency-divided signal s_div to a primary circuit (e.g., a resistor-capacitor (RC) filter) including a resistor and a capacitor. The frequency-divided signal s_div passing through the primary circuit has a primary response with a rising time, and the primary response may be a signal having a certain duty cycle (for example, a duty cycle of 50%) due to the decision levels of the plurality of inverters. In this case, the resistor included in the primary circuit may be a variable resistor, which is adjusted by an output voltage of an operational amplifier that feeds back the differential output signals s_dp and s_dn and receives the differential output signals s_dp and s_dn.
The output circuit 300 may receive the differential output signals s_dp and s_dn and output first output signals s_i and s_ib and second output signals s_q and s_qb that are orthogonal to each other. The first output signals s_i and s_ib are output signals orthogonal to the second output signals s_q and s_qb.
According to an exemplary embodiment of the inventive concept, the output circuit 300 receives differential output signals s_dp and s_dn and outputs first output signals s_i and s_ib by using a buffer that causes only an amplitude change. The output circuit 300 receives the differential output signals s_dp and s_dn and outputs second output signals s_q and s_qb having a phase delay of 90 degrees, respectively, by using a buffer and a phase delay circuit.
In this case, the output circuit 300 may delay the phase based on the first output signals s_i and s_ib and the second output signals s_q and s_qb. In other words, the output circuit 300 may control the delay phases of the second output signals s_q and s_qb by performing feedback on the output signals. According to an exemplary embodiment of the inventive concept, an operational amplifier receiving the first output signals s_i and s_ib and the second output signals s_q and s_qb may provide a delay control signal delaying a phase to a delay circuit in the output circuit 300. In other words, the output circuit 300 may delay the phase by performing feedback on the first output signals s_1 and s_ib and the second output signals s_q and s_qb.
As described below with reference to fig. 9 and 10, the phase delay in the output circuit 300 may be sensitive to temperature and voltage variations. For this reason, the driving voltage supplied to the buffer and delay circuits included in the output circuit 300 may be controlled by using a voltage control circuit including a current source that varies according to a temperature change.
The above-described frequency divider 1000 may perform frequency division at a CMOS level based on the clock signal CLK, and may output a quadrature signal having a duty ratio corrected once. Thus, divider 1000 may provide output signals s_i, s_ib, s_q, and s_qb, each having a 50% duty cycle, small frequency spurs, and being orthogonal to each other.
Fig. 3A and 3B are circuit diagrams of a frequency division core circuit according to an exemplary embodiment of the inventive concept.
Referring to fig. 3A, the frequency dividing core circuit 100a may include a first flip-flop loop 110a, a second flip-flop loop 120a, a plurality of flip-flops 111a,112a,113A,121a,122a and 123A, a nand gate 130, and an inverter 140.
According to an exemplary embodiment of the inventive concept, the first and second flip-flop loops 110a and 120a include a plurality of flip-flops 111a to 113a and 121a to 123a, respectively. For example, the flip-flop may be a D flip-flop. Each of the flip-flops 111a to 113a and 121a to 123a includes a control terminal for receiving a clock signal CLK, a D input terminal for inputting a logic value, and a Q output terminal for outputting the logic valueAnd (3) an end. The lines formed at the input and output terminals are called data lines.
According to the truth table of the flip-flop, when the control signal (e.g., CLK to the control terminal is 0), the control signal remains the previous Q or regardless of the logic value to the D input terminalFurthermore, when the control signal is 1 and the logic value input to the D input terminal is 0, Q outputs a logic value of 0, and/>A logical value of 1 is output. On the other hand, when the control signal is 1 and the logic value input to the D input terminal is 1, Q outputs a logic value of 1, and/>A logic value 0 is output. According to an exemplary embodiment of the inventive concept, the first and second flip-flop loops 110a and 120a include a plurality of flip-flops 111a to 113a and 121a to 123a, respectively, and each of the plurality of flip-flops 111a to 113a and 121a to 123a receives a clock signal CLK or a signal inverted from the clock signal CLK. For example, the first flip-flop loop 110a includes a flip-flop 112a for receiving the clock signal CLK, and flip-flops 111a and 113a respectively receiving signals inverted from the clock signal CLK. The second flip-flop loop 120a includes flip-flops 121a and 123a each receiving a clock signal CLK and a flip-flop 122a for receiving a signal inverted from the clock signal CLK. In other words, the frequency dividing core circuit 100a may perform frequency division by directly or inversely receiving the clock signal CLK, or by shifting the clock signal CLK stepwise at each flip-flop.
In this case, as shown in fig. 3A, the clock signal CLK may be inverted and received by the flip-flops 111a,113A, and 122 a. However, according to another exemplary embodiment of the inventive concept, as shown in FIG. 3B, a clock signal CLK and a clock inversion signalMay be applied to the frequency dividing core circuit 100b.
Referring to FIG. 3B, a clock signal CLK and a clock inversion signalMay be provided by an external signal source. Clock inversion signal/>Has a phase gap (phase gap) of half a period with the clock signal CLK. In other words, the clock signal is invertedInverted with respect to the clock signal CLK. For example, two signal input lines may be provided from an external signal source located outside the frequency-dividing core circuit 100b, and the signal input lines may respectively divide the clock signal CLK and the clock inversion signal/>Is provided to frequency division core circuit 100b. In this case, unlike fig. 3A, the control terminals of the plurality of flip-flops included in the core circuit 100b receive the control signal without inversion. For example, referring to FIG. 3B, flip-flops 112B,121B, and 123B may receive a clock signal CLK, and flip-flops 111B,113B, and 122B may receive a clock inversion signal/>In the following, the embodiments of fig. 3A and 3B are substantially identical to each other in terms of the operation of the flip-flop loops 110a,110B,120a, and 120B, and therefore, for convenience of explanation, the flip-flop will be described with reference to the frequency dividing core circuit 100a of fig. 3A.
Referring again to fig. 3A, the first and second trigger loops 110a and 120a each include the same number of triggers. According to an exemplary embodiment of the inventive concept, each of the first and second trigger loops 110a and 120a may include three triggers. The flip-flop 113a of the first flip-flop loop 110a, to which the frequency-divided signal s_div is fed back and input through the D terminal, may receive a signal inverted from the clock signal CLK through the control terminal. The flip-flop 123a of the second flip-flop loop 120a, to which the frequency-divided signal s_div is fed back and input through the D terminal, may receive the clock signal CLK through the control terminal. Among the plurality of flip-flops 111a to 113a and 121a to 123a included in the first flip-flop loop 110a and the second flip-flop loop 120a, a flip-flop receiving the clock signal CLK and a flip-flop receiving a signal inverted from the clock signal CLK may be connected to the D terminal or the Q terminal in an alternating order. The relationship between signal inputs and outputs in the flip-flop loops (e.g., 110a and 120 a) will be described in detail in fig. 4.
Fig. 4 is a timing diagram of signals input or output by a frequency division core circuit according to an exemplary embodiment of the inventive concept. For ease of illustration, fig. 4 will be described with reference to the identifiers used in fig. 3A.
Referring to fig. 4, the clock signal CLK is a voltage that repeats a logic low voltage and a logic high voltage in a period T, and may be input to control terminals of the plurality of flip-flops 111a to 113a and 121a to 123a included in the first flip-flop loop 110a and the second flip-flop loop 120 a. The first and second flip-flop loops 110a and 120a may receive the frequency division signal s_div through D-terminal and output QA and QB signals, respectively. In this case, as shown in fig. 4, each of the QA signal and the QB signal has a period of 5T, and thus, the QA signal and the QB signal have the same frequency division ratio.
The flip-flop 113a may receive a signal inverted from the clock signal CLK through a control terminal and a frequency division signal s_div through a D input terminal. The QA1 signal may be output through the Q output according to the truth table of the flip-flop 113 a. In other words, the first flip-flop loop 110a may generate a QA1 signal having a period of 5T, e.g., 2T+3T as shown in FIG. 4.
The flip-flop 112a may receive the clock signal CLK through a control terminal and the QA1 signal (from the flip-flop 113 a) through a D input terminal, thereby outputting the QA2 signal through a Q output terminal. In other words, the flip-flop 112a receives a signal inverted from the clock signal CLK through the control terminal, and can output the QA2 signal by receiving the clock signal CLK through the control terminal. In other words, the first flip-flop loop 110a may generate a QA2 signal having 5T as a period and a phase gap of 0.5T with the phase of the QA1 signal.
In the above-described process of generating the QA1 signal and the QA2 signal, by applying a signal inverted from the clock signal CLK to the control terminal of the flip-flop 113a and applying the clock signal CLK to the control terminal of the flip-flop 112a, which may be connected in series to the flip-flop 113a, a signal having a phase gap of half a period therebetween may be generated.
The flip-flop 111a may receive a signal inverted from the clock signal CLK through the control terminal and a QA2 signal (from the flip-flop 112 a) through the D input terminal, thereby passing throughThe output terminal outputs a QA signal. In other words, the first flip-flop loop 110a may generate a QA signal having 5T as a period and having a phase difference of 0.5T from a signal generated by inverting the QA2 signal.
Similar to the first flip-flop loop 110a, the second flip-flop loop 120a may also receive the frequency divided signal s_div and generate a QB1 signal, a QB2 signal, and a QB signal according to the flip-flop operation.
According to an exemplary embodiment of the inventive concept, the second flip-flop loop 120a generates the QB1 signal based on the clock signal CLK, and generates the QB1 signal based on the clock inversion signalThe QB2 signal is generated and based on the clock signal CLK, the QB signal is generated. In other words, the second flip-flop loop 120a is different from the first flip-flop loop 110a in that the first flip-flop loop 110a is based on the clock inversion signal/>The QA1 signal is generated, the QA2 signal is generated based on the clock signal CLK, and the QA signal is generated from the clock inversion signal. The first flip-flop loop 110a and the second flip-flop loop 120a have different methods by which the clock signal CLK is applied to the plurality of flip-flops 111a to 113a and 121a to 123a.
Accordingly, depending on the order in which the clock signal CLK is input to the control terminals of the plurality of flip-flops 111a to 113a and 121a to 123a and whether the clock signal CLK is inverted when input to the plurality of flip-flops 111a to 113a and 121a to 123a, the QA1 signal and the QB1 signal, the QA2 signal and the QB2 signal, and the QA signal and the QB signal may have the same frequency division ratio and a phase gap of 2.5T.
The frequency dividing core circuit 100a may generate the frequency dividing signal s_div through the NAND gate 130 and the inverter 140 by using the QA signal and the QB signal generated by the first flip-flop loop 110a and the second flip-flop loop 120a, respectively. The frequency divided signal s_div may be fed back to the first and second flip-flop loops 110a and 120a.
Referring to fig. 4, the frequency division signal s_div may have a period of 2.5T, which is 2.5 times the period T of the clock signal CLK. In addition, since the proportion of the logic high voltage per cycle is 40%, the frequency division signal s_div may have a duty ratio of 40%.
The frequency dividing core circuits 100, 100a and 100b described above may have a small number of flip-flops, each including a small number of loops, thereby reducing frequency spurs. In contrast to a frequency divider comprising many loops, the frequency is not divided precisely, and thus the target frequency may be mixed with other frequencies. However, in the frequency divider according to the exemplary embodiment of the inventive concept, by including the frequency dividing core circuit, the clock signal CLK and the clock inversion signal are alternately received by usingThe method of (2) obtains a divided signal s_div having a target frequency.
Fig. 5 is a circuit diagram of a duty ratio correction circuit according to an exemplary embodiment of the inventive concept. Fig. 6 is a timing diagram of signals generated by a duty cycle correction circuit according to an exemplary embodiment of the inventive concept.
Referring to fig. 5, the duty ratio correction circuit 200 may include an operational amplifier circuit 210, a transistor circuit 220, an inverter circuit 230, and a differential conversion circuit 240.
According to an exemplary embodiment of the inventive concept, the duty ratio correction circuit 200 receives the frequency-divided signal s_div and corrects the duty ratio of the frequency-divided signal s_div to a target duty ratio. For example, when the duty ratio of the frequency-divided signal s_div is 40%, the duty ratio correction circuit 200 may correct the duty ratio to 50% and output the corrected duty ratio. In addition, the duty correction circuit 200 may convert a uniform signal (unity signal) into a duty differential signal (duty DIFFERENTIAL SIGNAL).
According to an exemplary embodiment of the inventive concept, the operational amplifier circuit 210 may feedback the first differential output signal s_dp and the second differential output signal s_dn output from the output terminal of the duty ratio correction circuit 200, and receive the fed-back signals. The operational amplifier circuit 210 may include: a first RC filter including a resistor R1 and a capacitor C1; and a second RC filter including a resistor R2 and a capacitor C2 between the input terminal of the operational amplifier 211 and the output terminal of the duty correction circuit.
According to an exemplary embodiment of the inventive concept, the operational amplifier circuit 210 may receive a first differential output signal s_dp having a first voltage and a second voltage. In this case, the first differential output signal s_dp may have the form of a square wave. The first RC filter provided at the inverting input (-) of the operational amplifier 211 may receive the first differential output signal s_dp and apply an average value of the first differential output signal s_dp to the inverting input (-) of the operational amplifier 211.
The second differential output signal s_dn may also be a voltage having the form of a square wave. In this case, the second RC filter provided at the non-inverting input (+) of the operational amplifier 211 may receive the second differential output signal s_dn and apply an average value of the second differential output signal s_dn to the non-inverting input (+) of the operational amplifier 211.
According to an exemplary embodiment of the inventive concept, when the inverting input and the non-inverting input are different from each other, the operational amplifier 211 applies the control voltage Vctrl, which varies according to time, to the transistor circuit 220. In this case, the inverting input and the non-inverting input of the operational amplifier 211 tend to have the same average level as the inverting input and the non-inverting input due to the principle of the virtual short.
When the inverting input and the non-inverting input are identical to each other, the operational amplifier 211 may control the control voltage Vctrl to have a uniform constant value. For example, when the first differential output signal s_dp and the second differential output signal s_dn are inverted with respect to each other, the average values applied to the input terminals of the operational amplifier 211 may be identical to each other. When the control voltage Vctrl has a constant value (e.g., direct Current (DC) 1.5V), the feedback loop process of the duty correction circuit 200 by using the operational amplifier circuit 210 is stopped. Accordingly, the operational amplifier circuit 210 applies the uniform control voltage Vctrl having a constant value to the transistor circuit 220, and outputs the first differential output signal s_dp and the second differential output signal s_dn in an inverted form.
According to an exemplary embodiment of the inventive concept, the transistor circuit 220 may include a first transistor M1 for receiving the frequency division signal s_div and a second transistor M2 that may be modeled by using a variable resistor according to the control voltage Vctrl.
The first transistor M1 may function as a common source amplifier. For example, the first transistor M1 may receive the frequency-divided signal s_div through the gate terminal, invert the frequency-divided signal s_div, and output the inverted frequency-divided signal s_div to the node a. In fig. 5, the node a is connected to the drain terminal of the first transistor M1.
The second transistor M2 may correct the voltage applied to the node a to have a response in the form of an exponential function according to the control voltage Vctrl. In other words, the edge slope of the frequency-divided signal s_div may be adjusted according to the control voltage Vctrl generated based on the first and second differential output signals s_dp and s_dn. The edge slope is the slope that occurs when the voltage or current transitions from a first value to a second value at a rise time or a fall time. For example, the second transistor M2 may be a variable resistor that varies according to the control voltage Vctrl, and the first transistor M1, the second transistor M2, and the parasitic capacitor Cp of the transistor circuit 220 may be connected in parallel to the node a. Accordingly, the transistor circuit 220 may receive the frequency-divided signal s_div and output a voltage having an edge slope based on a time constant generated by multiplying a variable resistor changed according to the control voltage Vctrl by the value of the parasitic capacitor Cp, and may adjust the control voltage Vctrl and the edge slope, thereby adjusting the duty ratio.
Inverter circuit 230 may receive a voltage from node a and output the voltage to node B. For example, the inverter circuit 230 may include a plurality of inverters connected in series, and the duty ratio may be adjusted based on decision levels of the plurality of inverters.
Referring to fig. 6, the frequency division signal s_div may include a logic high voltage and a logic low voltage, each having a square form. The transistor circuit 220 may receive the frequency-divided signal s_div, invert the frequency-divided signal s_div through the first transistor M1, and output the frequency-divided signal s_div through the second transistor M2 and the parasitic capacitor Cp to have a response in the form of a digital index (digital index). Thus, a voltage can be output as shown in the voltage diagram of the node a shown in fig. 6. Thereafter, each inverter included in the inverter circuit 230 may output a voltage lower than the decision level as a logic low voltage, and may output a voltage higher than the decision level as a logic high voltage.
For example, at time ta, the frequency-divided signal s_div transitions from a logic high voltage to a logic low voltage. The transistor circuit 220 may invert the frequency-divided signal s_div, adjust an edge slope of the frequency-divided signal s_div, and output the frequency-divided signal s_div having the adjusted edge slope to the node a. For example, after time point ta and before time point tb, the signal indicated by node a in fig. 6 has an adjusted edge slope. The time point tb is a time point when the decision level of the inverter is equal to the voltage level.
Thereafter, a square wave having a fixed duty ratio of 50% can be obtained by the inverter circuit 230 according to the decision level. For example, when an odd number of inverters are included in the inverter circuit 230, the transistor circuit 220 may output a periodic square wave having a logic high voltage before the time point tb and a logic low voltage after the time point tb through the node B.
At the point in time tc when the frequency divided signal s_div transitions from a logic low voltage to a logic high voltage, the fall time may be very short or non-existent. At a time point tc, the first transistor M1 operated by using the common source amplifier (e.g., the operational amplifier 211) is turned off, and when the node a is temporarily grounded, the voltage of the node a may drop in the form of a step function without a falling time.
Referring again to fig. 5, the differential conversion circuit 240 may convert a single signal input from the inverter circuit 230 to the differential conversion circuit 240 into a differential signal and output the converted differential signal. The differential signals may be a first differential output signal s_dp and a second differential output signal s_dn. Each of the first differential output signal s_dp and the second differential output signal s_dn is a signal having a phase 180 degrees out of phase with the phase of the other signal. According to an exemplary embodiment of the inventive concept, the differential conversion circuit 240 may output the first differential output signal s_dp having the same phase as that of the frequency division signal s_div and having a duty ratio of 50% by using an even number of inverters connected in series. In addition, the differential conversion circuit 240 may output a second differential output signal s_dn having a phase opposite to that of the first differential output signal s_dp by using a common gate amplifier and an inverter.
Fig. 7A is a circuit diagram of an output circuit according to an exemplary embodiment of the inventive concept. Fig. 7B is a view of a logic circuit included in an output circuit according to an exemplary embodiment of the inventive concept.
Referring to fig. 7A, the output circuit 300 may include an input buffer 311, a plurality of output buffers, for example, a first output buffer 312, a second output buffer 313 and a third output buffer 314, a phase delay circuit 320 and an operational amplifier circuit 330.
According to an exemplary embodiment of the inventive concept, the output circuit 300 may receive the first differential output signal s_dp and the second differential output signal s_dn through the input buffer 311. The first output buffer 312 and the second output buffer 313 may amplify the signals amplified by the input buffer 311, respectively, and output I signals s_i and IB signals s_ib. In other words, the I signals s_i and IB signals s_ib may be output by fixing phases of the first differential output signal s_dp and the second differential output signal s_dn and amplifying magnitudes.
According to an exemplary embodiment of the inventive concept, the phase delay circuit 320 may delay the phase of the input signal based on the delay control signal DLY CTRL. The third output buffer 314 amplifies the signal output from the phase delay circuit 320 and outputs Q signals s_q and QB signals s_qb.
According to an exemplary embodiment of the inventive concept, the operational amplifier circuit 330 may output the delay control signal DLY CTRL based on the received plurality of input signals s_qp, s_qn, s_ip, and s_in. IN other words, the operational amplifier circuit 330 may output the delay control signal DLY CTRL IN response to the input signals s_qp, s_qn, s_ip, and s_in. In this case, a bias circuit may be added to the output terminal of the operational amplifier 331, and the bias circuit may redistribute the voltage according to the input required by the phase delay circuit 320 and input the redistributed voltage to the phase delay circuit 320.
The plurality of input signals s_qp, s_qn, s_ip, and s_in received by the operational amplifier circuit 330 are signals generated by performing feedback on the plurality of output signals s_i, s_ib, s_q, and s_qb output by the output circuit 300, the details of which will be described with reference to fig. 7B.
Referring to fig. 7B, the plurality of NAND gates 332, 333, 334, and 335 may receive a plurality of output signals s_i, s_ib, s_q, s_qb output by the output circuit 300 and generate input signals s_ip, s_in, s_qp, and s_qn of the operational amplifier circuit 330. The plurality of NAND gates 332 to 335 may be included in the output circuit 300, and may also be included in the operational amplifier circuit 330. In other words, the plurality of NAND gates 332 to 335 may be included between the second output buffer 313, the third output buffer 314, and the RC filter included in the operational amplifier circuit 330.
Referring again to fig. 7A, the RC filter connected to the inverting input terminal (-) of the operational amplifier 331 applies an output due to the QP signal s_qp and the QN signal s_qn to the inverting input terminal (-) of the operational amplifier 331. The RC filter connected to the non-inverting input (+) of the operational amplifier 331 applies an output due to the IP signal s_ip and the IN signal s_in to the non-inverting input (+) of the operational amplifier 331.
When the average value of the QP signal s_qp and the QN signal s_qn and the average value of the IP signal s_ip and the IN signal s_in are equal to each other (by each RC filter) (IN other words, when the inverting input and the non-inverting input of the operational amplifier 331 are equal to each other), the operational amplifier 331 outputs the voltage of the delay control signal DLY CTRL as a constant value. When the output signal of the output circuit 300 is a quadrature signal, the operational amplifier 331 outputs the delay control signal DLY CTRL as a constant value. For example, when the I signal s_i and the Q signal s_q are orthogonal to each other and the IB signal s_ib and the QB signal s_qb are orthogonal to each other, the average values of the voltages input to the inverting input terminal (-) and the non-inverting input terminal (+) of the operational amplifier 331 are identical to each other.
When the delay control signal DLY CTRL is received as a constant value, the phase delay circuit 320 no longer performs phase delay. In other words, the delay operation performed by the operational amplifier circuit 330 is locked.
Fig. 8 is a timing diagram of signals generated by an output circuit according to an exemplary embodiment of the inventive concept. For convenience of explanation, fig. 8 will be described by using identifiers used in fig. 7A and 7B.
Referring to fig. 8,I, the signals s_i and IB are inverted with respect to each other, and the Q signals s_q and QB are inverted with respect to each other. The I signal s_i and the Q signal s_q may be orthogonal with respect to each other, and the IB signal s_ib and the QB signal s_qb may be orthogonal with respect to each other. In other words, the plurality of output signals s_i, s_ib, s_q, and s_qb output from the output circuit 300 may be signals orthogonal to each other.
The plurality of signals s_ip, s_in, s_qp, and s_qn input to the operational amplifier circuit 330 are signals obtained by applying the plurality of output signals s_i, s_ib, s_q, and s_qb output from the output circuit 300 to the NAND gates 332 to 335. By doing so, the Q signal s_q output from the output circuit 300 is delayed by 90 degrees compared to the I signal s_i, and the QB signal s_qb is delayed by 90 degrees compared to the IB signal s_ib.
For example, the IP signal s_ip is generated by a Negative AND (NAND) operation on the I signal s_i AND the Q signal s_q, the IN signal s_in is generated by a NAND operation on the IB signal s_ib AND the QB signal s_qb, the QP signal s_qp is generated by a NAND operation on the Q signal s_q AND the IB signal s_ib, AND the QN signal s_qn is generated by a NAND operation on the QB signal s_qb AND the I signal s_i.
Fig. 9 is a circuit diagram of an output circuit according to an exemplary embodiment of the inventive concept.
Referring to fig. 9, the output circuit 300 may further include a driving voltage control circuit 340, and an output terminal of the output circuit 300 may be connected to an input terminal of the operational amplifier circuit 330.
According to an exemplary embodiment of the inventive concept, the driving voltage control circuit 340 may provide the driving voltage to at least one of the first output buffer 312, the second output buffer 313 and the third output buffer 314 and the phase delay circuit 320 according to process, voltage and temperature (PVT) conditions. The phases of components included in the output circuit 300 can be easily changed according to PVT conditions.
According to another exemplary embodiment of the inventive concept, the driving voltage control circuit 340 may be disposed outside the output circuit 300, and in this case, the driving voltage control circuit 340 may control not only the driving voltages supplied to the components of the output circuit 300, but also the driving voltages supplied to the flip-flops of the frequency dividing core circuit 100, the operational amplifier circuit 210 of the duty ratio correction circuit 200, the inverter circuit 230, and the differential conversion circuit 240.
Fig. 10 is a circuit diagram of a driving voltage control circuit 340 according to an exemplary embodiment of the inventive concept.
Referring to fig. 10, the driving voltage control circuit 340 may include a current source 341, a diode 342, a voltage regulator 343, and a reference resistor 344.
According to an exemplary embodiment of the inventive concept, the current source 341 may generate a current Proportional To Absolute Temperature (PTAT). The generation of PTAT is used to control the drive voltage applied to the output circuit 300 due to temperature variations in PVT conditions. The voltage regulator 343 may be, for example, a Low Drop Out (LDO) regulator.
According to an exemplary embodiment of the inventive concept, the reference voltage V ref node is connected in parallel to the current source 341 and the voltage regulator 343, and the reference voltage V ref node is also connected in parallel to the diode 342 and the reference resistor 344 connected in series to each other. Thus, the reference voltage V ref can be expressed by equation 1 as follows:
[ formula 1]
Vref＝IPTAT·Rref+2·(Vov+Vth)
Here, V ov and V th represent the overdrive voltage and the threshold voltage of the diode 342, respectively.
According to the reference voltage V ref, the voltage regulator 343 may provide the driving voltage according to the temperature variation to the phase delay circuit 320 and the first output buffer 312. In other words, the phase delay fluctuation due to the temperature change can be reduced by supplying different voltages according to the temperature change instead of directly supplying the power supply Voltage (VDD).
Fig. 11 is a graph of delay time when a driving voltage control circuit is operated according to an exemplary embodiment of the inventive concept.
Referring to fig. 11, the horizontal axis represents the voltage of the control signal DLY CTRL for controlling the operational amplifier circuit 330 in the output circuit 300 of the phase delay circuit 320, and the vertical axis represents the delay time in picoseconds. In the case where the driving voltage control circuit 340 is used for the duty correction circuit 200, when the driving voltage control circuit 340 supplies the driving voltage to the operational amplifier circuit 210 of the duty correction circuit 200, the horizontal axis may represent the control voltage Vctrl output by the operational amplifier 211.
Referring to fig. 11, a solid line of the graph represents a delay time when the driving voltage is supplied to the output circuit 300 through the driving voltage control circuit 340, and a broken line of the graph represents a delay time when the power supply voltage is supplied to the output circuit 300 as the driving voltage.
According to an exemplary embodiment of the inventive concept, when the driving voltage control circuit 340 supplies the driving voltage to the phase delay circuit 320, the time variation delayed by the phase delay circuit 320 is reduced according to the temperature variation of-40, 50, and 110, and thus the reduction of the error range can be recognized. On the other hand, when the driving voltage VDD is directly applied to the phase delay circuit 320, the phase delay performance is deteriorated due to strong fluctuation of the delay time caused by temperature variation.
Fig. 12 is a block diagram for describing a transceiver according to an exemplary embodiment of the inventive concept.
Referring to fig. 12, a transceiver 2000 may include a local oscillator 410, a signal source 420, mixers (e.g., a first mixer 431 and a second mixer 432), an adder 440, a power amplifier 450, and an antenna 460. As shown in fig. 12, the local oscillator 410 may include a frequency divider 1000, a filter 411, and a buffer 412.
The local oscillator 410 may generate the clock signal CLK based on the ac signal received from the signal source 420. The local oscillator 410 adjusts various characteristics of the clock signal CLK, and outputs the clock signal CLK through the mixers 431 and 432. Divider 1000 may be implemented as one of the various embodiments described in fig. 1-12. In other words, the frequency divider 1000 receives the clock signal CLK and divides the frequency of the clock signal CLK in the frequency division core circuit 100, corrects the duty ratio of the clock signal CLK in the duty ratio correction circuit 200, and outputs the output signals s_i, s_ib, s_q, and s_qb orthogonal to each other from the output circuit 300 to the first mixer 431 and the second mixer 432.
According to an exemplary embodiment of the inventive concept, the first mixer 431 mixes the I signal IBB in the baseband with the first output signals s_1 and s_ib, the second mixer 432 mixes the Q signal QBB in the baseband with the second output signals s_q and s_qb, and the first mixer 431 and the second mixer 432 output the mixed signals to the adder 440. In this case, I and Q may be components orthogonal to each other. The IQ signal summed in the summer 440 is amplified in the power amplifier 450, and the amplified IQ signal is output through the antenna 460 as a frequency in a Radio Frequency (RF) band.
Exemplary embodiments of the inventive concept provide a frequency divider that reduces frequency spurs due to a small number of flip-flop loops, corrects a duty cycle, and outputs a quadrature signal, and a transceiver including the frequency divider.
Further, the frequency divider and the transceiver including the same according to exemplary embodiments of the inventive concept can reduce a pulling effect and frequency spurs while correcting a duty ratio and outputting a quadrature signal.
While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various modifications may be made without departing from the scope of the inventive concept as defined by the following claims.
Claims (19)
1. A frequency divider, comprising:
A core circuit comprising a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received through a control terminal of the flip-flop, wherein the core circuit is configured to:
Outputting a divided signal based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first signal and the second signal having the same division ratio and different phases, and feeding back the divided signal through an input of each of the first flip-flop loop and the second flip-flop loop;
A duty ratio correction circuit that receives the frequency-divided signal and outputs a differential output signal generated by correcting the duty ratio of the frequency-divided signal; and
And an output circuit that outputs a first output signal that is a signal amplified from the differential output signal and a second output signal that is a quadrature signal of the first output signal.
2. The frequency divider of claim 1, wherein,
The first flip-flop loop and the second flip-flop loop each include the same number of flip-flops, and each control terminal of the flip-flop receives a clock signal or a signal inverted from the clock signal.
3. The frequency divider of claim 2, wherein,
Each of the flip-flops in the first flip-flop loop is connected in series, the first flip-flop in the first flip-flop loop that receives the clock signal and the second flip-flop in the first flip-flop loop that receives the signal inverted from the clock signal are alternately connected to each other, and
Each of the second flip-flop circuits is connected in series, and the first flip-flop in the second flip-flop circuit that receives the clock signal and the second flip-flop in the second flip-flop circuit that receives the signal inverted from the clock signal are alternately connected to each other.
4. The frequency divider of claim 3, wherein,
The frequency-divided signal is output by performing an AND operation on a first signal AND a second signal output from the first flip-flop loop AND the second flip-flop loop, respectively.
5. The frequency divider of claim 1, wherein,
The duty cycles of the differential output signal, the first output signal and the second output signal are corrected to 50%.
6. The frequency divider of claim 1, wherein,
The duty cycle correction circuit further comprises a transistor circuit, wherein an input terminal of the duty cycle correction circuit is connected to the transistor circuit, and
The duty ratio correction circuit feeds back the differential output signal to the transistor circuit, and adjusts the duty ratio of the divided signal by adjusting the edge slope of the divided signal based on the differential output signal.
7. The frequency divider of claim 6, wherein,
The duty cycle correction circuit further comprises a first operational amplifier, wherein,
The output terminal of the duty correction circuit outputting the differential output signal is electrically connected to the input terminal of the first operational amplifier, and the output terminal of the first operational amplifier is electrically connected to the input terminal of the duty correction circuit to which the frequency-divided signal is input.
8. The frequency divider of claim 7, wherein,
The first operational amplifier receives the differential output signal and generates a control signal that adjusts an edge slope of the divided signal, and the transistor circuit adjusts the edge slope of the divided signal in response to the control signal.
9. The frequency divider of claim 8, wherein,
The transistor circuit includes a first transistor and a second transistor, wherein a frequency-divided signal is applied to a gate terminal of the first transistor, a control signal is applied to a gate terminal of the second transistor, and wherein the transistor circuit adjusts an edge slope of the frequency-divided signal by using the first transistor and the second transistor.
10. The frequency divider of claim 9, further comprising:
a resistor-capacitor (RC) filter connected to the output of the duty cycle correction circuit and to the input of the first operational amplifier.
11. The frequency divider of claim 1, further comprising:
A driving voltage control circuit that controls the level of the driving voltage supplied to the output circuit according to process, voltage and temperature (PVT) conditions.
12. The frequency divider of claim 11, wherein,
The drive voltage control circuit further includes: a current source that generates a current proportional to temperature; and a voltage regulator that provides a driving voltage based on the current generated by the current source.
13. The frequency divider of claim 1, wherein,
The output circuit further comprises an output buffer and a phase delay circuit, wherein,
The first output signal is output through the output buffer, the second output signal is output through the phase delay circuit, and the phase delay circuit delays the phase of the differential output signal based on the first output signal and the second output signal so that the second output signal is orthogonal to the first output signal.
14. The frequency divider of claim 13, wherein,
The output circuit further includes an operational amplifier circuit, and
The output circuit receives the first output signal and the second output signal at an input terminal of the operational amplifier circuit, and outputs a signal controlling a phase delay operation of the phase delay circuit from the output terminal of the operational amplifier circuit to the phase delay circuit.
15. A frequency divider, comprising:
a core circuit that receives a clock signal and outputs a frequency-divided signal generated by dividing the frequency of the clock signal; and
A duty correction circuit that receives the frequency-divided signal and outputs a differential output signal having a new duty according to a decision level,
Wherein the duty cycle correction circuit adjusts the original duty cycle so that the differential output signal has a new duty cycle by performing feedback on the differential output signal and adjusting an edge slope of the divided signal based on the fed-back differential output signal.
16. The frequency divider of claim 15, wherein,
The duty cycle correction circuit further comprises a first operational amplifier,
The output end of the duty ratio correction circuit outputting the differential output signal is electrically connected to the input end of the first operational amplifier, and the output end of the first operational amplifier is electrically connected to the input end of the duty ratio correction circuit inputting the frequency division signal.
17. The frequency divider of claim 16, wherein,
The first operational amplifier receives the differential output signal and generates a control signal that adjusts an edge slope of the divided signal, and the duty cycle correction circuit adjusts the edge slope of the divided signal in response to the control signal.
18. A transceiver, comprising:
A core circuit that receives a clock signal, outputs a frequency-divided signal generated by dividing a frequency of the clock signal, and includes a first flip-flop loop and a second flip-flop loop, each of the first flip-flop loop and the second flip-flop loop including a plurality of flip-flops; and
A duty ratio correction circuit that receives the frequency-divided signal and outputs a differential output signal generated by correcting the duty ratio of the frequency-divided signal;
And an output circuit that outputs a first output signal that is a signal amplified from the differential output signal and a second output signal that is a signal delayed from the first output signal.
19. The transceiver of claim 18, further comprising:
the driving voltage control circuit is used for controlling the driving voltage,
Wherein the output circuit comprises an output buffer and a phase delay circuit, wherein,
The first output signal is a signal generated by amplifying the differential output signal by the output buffer, the second output signal is a signal delayed by the phase delay circuit, and the driving voltages of the output buffer and the phase delay circuit are supplied by the driving voltage control circuit.
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| CN111464153A (en) * | 2020-05-14 | 2020-07-28 | 京东方科技集团股份有限公司 | Pulse signal generation circuit, pulse signal generation method, clock generation module and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6016422A (en) * | 1997-10-31 | 2000-01-18 | Motorola, Inc. | Method of and apparatus for generating radio frequency quadrature LO signals for direct conversion transceivers |
| JP2002057570A (en) * | 2000-08-07 | 2002-02-22 | Nec Corp | 90° phase shifter |
| US8471607B1 (en) * | 2011-12-30 | 2013-06-25 | St-Ericsson Sa | High-speed frequency divider architecture |
| US9219470B1 (en) * | 2013-04-30 | 2015-12-22 | Pmc-Sierra Us, Inc. | Systems and methods for clock path single-ended DCD and skew correction |
| CN105322952A (en) * | 2014-05-27 | 2016-02-10 | 恩智浦有限公司 | Multi-modulus frequency divider |
| KR20170014905A (en) * | 2015-07-31 | 2017-02-08 | 엘지전자 주식회사 | Frequency dividng circuit |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442670A (en) * | 1994-02-16 | 1995-08-15 | National Semiconductor Corporation | Circuit for dividing clock frequency by N.5 where N is an integer |
| US6121801A (en) * | 1997-01-08 | 2000-09-19 | Advanced Micro Devices, Inc. | Non-integer clock divider |
| TW425766B (en) * | 1999-10-13 | 2001-03-11 | Via Tech Inc | Non-integer frequency division device |
| US6611573B2 (en) * | 2001-08-14 | 2003-08-26 | Sun Microsystems, Inc. | Non-integer division of frequency |
| TWI228873B (en) * | 2003-10-08 | 2005-03-01 | Ali Corp | Method and related apparatus for non-integer frequency division |
| KR100545148B1 (en) * | 2003-12-09 | 2006-01-26 | 삼성전자주식회사 | Duty cycle correction circuit and delay-locked loop circuit employing the same and method for correcting duty cycle |
| JP2005223829A (en) * | 2004-02-09 | 2005-08-18 | Nec Electronics Corp | Fractional frequency divider circuit and data transmission apparatus using the same |
| KR100842404B1 (en) * | 2007-04-12 | 2008-07-01 | 삼성전자주식회사 | Quadrature phase voltage controlled oscillator |
| TWI319264B (en) * | 2007-09-12 | 2010-01-01 | Via Tech Inc | Fractional frequency divider |
| DE602007008439D1 (en) * | 2007-11-13 | 2010-09-23 | Fujitsu Semiconductor Ltd | Phase error reduction circuit for 90o offset clock signals |
| KR101046245B1 (en) * | 2009-11-30 | 2011-07-04 | 주식회사 하이닉스반도체 | Duty compensation circuit |
| KR102240275B1 (en) * | 2014-12-01 | 2021-04-14 | 삼성전자주식회사 | Delay locked loop and memory device having the same |
-
2018
- 2018-07-05 KR KR1020180078249A patent/KR102523417B1/en active IP Right Grant
- 2018-11-27 CN CN201811424661.1A patent/CN109842410B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6016422A (en) * | 1997-10-31 | 2000-01-18 | Motorola, Inc. | Method of and apparatus for generating radio frequency quadrature LO signals for direct conversion transceivers |
| JP2002057570A (en) * | 2000-08-07 | 2002-02-22 | Nec Corp | 90° phase shifter |
| US8471607B1 (en) * | 2011-12-30 | 2013-06-25 | St-Ericsson Sa | High-speed frequency divider architecture |
| US9219470B1 (en) * | 2013-04-30 | 2015-12-22 | Pmc-Sierra Us, Inc. | Systems and methods for clock path single-ended DCD and skew correction |
| CN105322952A (en) * | 2014-05-27 | 2016-02-10 | 恩智浦有限公司 | Multi-modulus frequency divider |
| KR20170014905A (en) * | 2015-07-31 | 2017-02-08 | 엘지전자 주식회사 | Frequency dividng circuit |
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|---|---|
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