CN109840151A - A kind of load-balancing method and device for multi-core processor - Google Patents
A kind of load-balancing method and device for multi-core processor Download PDFInfo
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Abstract
The present embodiments relate to field of computer technology, more particularly to a kind of load-balancing method and device for multi-core processor, it include: to obtain the second process for having accessed the mark of first processor entrained by the first process of the shared data and having needed to access the shared data at least one shared data；It is identical to judge that the mark of second processor entrained by second process is identified whether with the first processor, if not identical, processor flag entrained by second process is revised as the first processor and is identified；It, will be under second process migration to the first processor within the load balancing period.It can be seen that, multiple processes of shared data can all be migrated to same processor, without shared data is placed under respective caching respectively again, but shared data is placed into the caching of same processor, therefore, it is able to ascend the Buffer Utilization of operating system, so as to promote the execution efficiency of process.
Description
Technical field
The present embodiments relate to field of computer technology more particularly to a kind of load balancing sides for multi-core processor
Method and device.
Background technique
Currently, multi-core processor has become the processor of mainstream, it is widely used.(SuSE) Linux OS kernel
Performance of the process scheduler under SMP (Symmetrical Multi-Processing, symmetric multi-processors) architecture be
More excellent, it is also widely used.But (SuSE) Linux OS cache availability is insufficient under SMP architecture, very great Cheng
The execution efficiency of process is reduced on degree.For example, when multiple processes under multi-core processor exist and share shared data, then often
A process is required to for the shared data being placed into respective caching from taking-up in memory, such as when using the shared data
This, causes the utilization rate of the caching of operating system insufficient, also reduces the execution efficiency of process.
Summary of the invention
The embodiment of the present invention provides a kind of load-balancing method and device for multi-core processor, to promote operation system
The Buffer Utilization of system, to promote the execution efficiency of process.
The embodiment of the present invention provides a kind of load-balancing method for multi-core processor, comprising:
For at least one shared data, acquisition has accessed the first processing entrained by the first process of the shared data
Device identifies and needs to access the second process of the shared data；
It is identical to judge that the mark of second processor entrained by second process is identified whether with the first processor, if
It is not identical, then processor flag entrained by second process is revised as the first processor and identified；
Within the load balancing period, for the second process under any processor, scheduler judges the second process institute
Identifying whether for the processor flag of carrying and the processor is identical, if it is not the same, then by second process migration to institute
It states under first processor.
Preferably, the acquisition has accessed the mark of first processor entrained by the first process of the shared data and has needed
Access the second process of the shared data, comprising:
Determine the multiple processes for accessing the shared data；
After first in the multiple process is monitored using the first process of the shared data, described first is obtained
The mark of first processor entrained by process；
Processor flag entrained by second process is revised as the first processor mark, comprising:
For each process in the multiple process in addition to first process, by processing entrained by the process
Device mark is revised as the first processor mark.
Preferably, having accessed the mark of first processor entrained by the first process of the shared data and needs obtaining
Before the second process for accessing the shared data, further includes:
In initialization, for any process, processor flag entrained by the process is assigned to the process.
Preferably, identifying it processor flag entrained by second process is revised as the first processor
Afterwards, further includes:
Statistics is revised as the number of processes of the first processor mark；
According to the number of processes, process migration amount is determined；
Scheduler judge processor flag entrained by the process and the processor identify whether it is identical before, also
Include:
Judge that the process migration amount is not zero.
The embodiment of the present invention also provides a kind of load balancing apparatus for multi-core processor, comprising:
Module is obtained, for being directed at least one shared data, obtains the first process institute for having accessed the shared data
The first processor of carrying identifies and needs to access the second process of the shared data；
Feedback module, for judging the mark of second processor entrained by second process and the first processor mark
Whether knowledge is identical, if not identical, processor flag entrained by second process is revised as the first processor mark
Know；
Scheduler module, for for the second process under any processor, judging described second within the load balancing period
Identifying whether for processor flag entrained by process and the processor is identical, if it is not the same, then moving second process
It moves under the first processor.
Preferably, the acquisition module, is specifically used for:
Determine the multiple processes for accessing the shared data；
After first in the multiple process is monitored using the first process of the shared data, described first is obtained
The mark of first processor entrained by process；
The feedback module, is specifically used for:
For each process in the multiple process in addition to first process, by processing entrained by the process
Device mark is revised as the first processor mark.
Preferably, further include: initialization module；
The initialization module is used in initialization, for any process, by processor mark entrained by the process
Know and assigns the process.
Preferably, the feedback module, is also used to:
After processor flag entrained by second process to be revised as to the first processor mark, statistics is repaired
It is changed to the number of processes of the first processor mark；
According to the number of processes, process migration amount is determined；
Scheduler module judge processor flag entrained by the process and the processor identify whether it is identical before,
Judge that the process migration amount is not zero.
Another embodiment of the present invention provides a kind of calculating equipment comprising memory and processor, wherein the storage
Device is for storing program instruction, and the processor is for calling the program instruction stored in the memory, according to the journey of acquisition
Sequence executes any of the above-described kind of method.
Another embodiment of the present invention provides a kind of computer storage medium, the computer-readable recording medium storage has
Computer executable instructions, the computer executable instructions are for making the computer execute any of the above-described kind of method.
A kind of load-balancing method and device for multi-core processor provided by the above embodiment, comprising: at least
One shared data, acquisition have accessed the mark of first processor entrained by the first process of the shared data and have needed to access
Second process of the shared data；Judge the mark of second processor entrained by second process and the first processor
It identifies whether identical, if not identical, processor flag entrained by second process is revised as the first processor
Mark；Within the load balancing period, for the second process under any processor, scheduler judges entrained by second process
Processor flag and the processor identify whether it is identical, if it is not the same, then by second process migration to described
Under one processor.As can be seen that when, there are when shared data, obtaining accessed the shared data first in multi-core operation system
First processor entrained by first process identifies and needs to access the second process of the shared data, then in the second process institute
It, will be entrained by the second process when the first processor mark that second processor mark and the first process of carrying carry is not identical
Processor flag modifies first processor mark, finally within the load balancing period, for the second process under any processor,
Scheduler judge processor flag entrained by the second process and the processor identify whether it is identical, if it is not the same, then will
Under second process migration to first processor, thus at the processor flag entrained by remaining process of shared data and first
Manage device mark it is not identical when, can be by under remaining process migration to first processor, in this way, can be by multiple processes of shared data
It all migrates to same processor, in this way, not having to respectively will again when multiple processes of shared data reuse the shared data
Shared data is placed under respective caching, but shared data is placed into the caching of first processor, therefore, Neng Gouti
The Buffer Utilization of lift operations system, so as to promote the execution efficiency of process.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced.
Fig. 1 is a kind of flow diagram of the load-balancing method for multi-core processor provided in an embodiment of the present invention；
Fig. 2 is process of feedback schematic diagram provided in an embodiment of the present invention；
Fig. 3 is the flow diagram of scheduler provided in an embodiment of the present invention judgement；
Fig. 4 is a kind of structural schematic diagram of the load balancing apparatus for multi-core processor provided in an embodiment of the present invention.
Specific embodiment
In order to which the purpose of the present invention, technical solution and beneficial effect is more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used to explain this hair
It is bright, it is not intended to limit the present invention.
It should be noted that load-balancing method provided in an embodiment of the present invention and device can be applied to comprising isomorphism multicore
In the operating system of processor.For example, can be applied to SMP (Symmetrical Multi-Processing, symmetric multi-processors)
In operating system under architecture.
Fig. 1 illustrates a kind of stream of load-balancing method for multi-core processor provided in an embodiment of the present invention
Journey schematic diagram, as shown in Figure 1, this method can include:
S101, it is directed at least one shared data, acquisition has accessed first entrained by the first process of the shared data
Processor flag and the second process for needing to access the shared data.
S102, judge second processor entrained by the second process mark identified whether with first processor it is identical, if
Not identical, going to step is S103, otherwise, terminates process.
S103, processor flag entrained by the second process is revised as to first processor mark.
S104, within the load balancing period, for the second process under any processor, scheduler judges the second process institute
Identifying whether for the processor flag of carrying and the processor is identical, if it is not the same, then will be at the second process migration to first
It manages under device.
Specifically, in the load balancing period, for the process under any processor in multi-core processor, scheduler judgement
Whether processor flag entrained by the process identifies whether identical with the processor, if identical, does not migrate, if not
It is identical, then the process is migrated to processing entrained by the process under the processor and is identified under corresponding processor.
Firstly, before above-mentioned steps S101, it can also be in initialization, under the operating system comprising multi-core processor
Any process, the mark of processor belonging to the process is assigned to the process, so that the process carries place belonging to the process
Manage the mark of device.
Specifically, the structural body of process can be defined by modifying operating system, increase processor flag, thus by process institute
The mark of the processor of category assigns process, so that the process carries the mark of processor belonging to the process.For example, can operate
System, which defines in the structural body of process, increases " CPU number ", thus assign the mark of processor belonging to process to the process, with
The process is set to carry the number information of CPU belonging to the process.
In a kind of optional embodiment, it can realize that modification operating system defines process by following program code
Structural body increases processor flag, to assign the mark of processor belonging to process to process.
struct task_struct{
int prio,static_prio,normal_prio；// process priority
unsigned int rt_priority；
const struct sched_class*sched_class；Affiliated scheduler class
unsigned int policy；
cpumask_t cpus_allowed；The CPU that // limiting process can be run
struct sched_entity se；
struct sched_rt_entity rt；
int cpu_num；// save the CPU number that the process needs to be migrated
…………………………..
}
It should be noted that above-mentioned program code is merely illustrative used, must not be used for realization side of the embodiment of the present invention
The limitation of formula, the i.e. embodiment of the present invention also can be realized in other ways the structural body that modification operating system defines process, increase
Add processor flag, to assign the mark of processor belonging to process to process.
Above-mentioned steps S103 is being executed, i.e., processor flag entrained by the second process is being revised as first processor
After mark, the also statistics available number of processes for being revised as first processor mark determines process migration according to the process data
Amount.
In order to promote the execution efficiency of scheduler, whether scheduler can first determine that process migration amount before migrating processes
It is zero, in the case where process migration amount is zero, scheduler does not just have to judge that the process under it is taken for each processor again
The processor flag of band whether with the processor identify whether it is identical, without again by the second process migration to first processor
Under, so as to promote the execution efficiency of scheduler.
In an operating system, when there are shared data, lock mechanism is generallyd use, for example, passing through Futex on linux
The basic tool of locking and advanced mutual exclusion lock that (fast userspace muttex, express user space mutexes) are realized,
Futex is the synchronization mechanism of a kind of User space and kernel state mixing, needs two parts cooperation to complete, Linux is provided accordingly
System is called, and is provided support to the stationary problem in the case where process competition, is needed synchronous process by sharing one piece of memory
Space, and Futex is sitting in this section of memory headroom.In addition, the excellent properties based on Futex itself, can also construct higher
The lock of rank, it is such as common based on POSIX (Portable Operating System Interface of UNIX, portable
Operating system interface) mutual exclusion lock etc..
On the basis of lock mechanism based on operating system, above-mentioned steps S101 can be by presetting in an operating system
Shared data acquisition module executes, and shared data acquisition module is used to acquire the information of each process of shared data.Above-mentioned steps
S102 can be by presetting shared data feedback module execution in an operating system, and in order to accelerate to modify speed, promotion is repaired
Change efficiency, shared data acquisition module obtain the mark of first processor entrained by the first process of accessing shared data with
Afterwards, processor flag entrained by remaining process under the shared data can be judged one by one by shared data feedback module whether
It is identical as first processor mark entrained by the first process, if it is not the same, then by processor flag entrained by the process
It is revised as first processor mark.
On the basis of lock mechanism based on operating system, above-mentioned steps S101 and above-mentioned steps S102 can also be according to Fig. 2 institutes
Show that process of feedback is realized.
In Fig. 2, acquired first entrained by first process using shared data by shared data acquisition module
After managing device mark, first processor mark is sent to shared data feedback module, shared data feedback module remaining into
When any process scheduling of journey, it is identical to judge that the processor flag of process carrying is identified whether with first processor, if not
It is identical, then the processor flag that the process carries is revised as first processor mark.For example, can sentence when the process wakes up
The processor flag that the process of breaking carries identified whether with first processor it is identical, if it is not the same, then the process is carried
Processor flag is revised as first processor mark.
In a kind of optional embodiment, above-mentioned steps S101 and above-mentioned steps can be realized by the code of following procedure
The operation of S102.
It should be noted that above-mentioned program code is merely illustrative used, must not be used for realization side of the embodiment of the present invention
The limitation of formula, the i.e. embodiment of the present invention can also above-mentioned steps S101 and above-mentioned steps S102 by another way operation.
Based on the lock mechanism in operating system, it may be determined that multiple processes of accessing shared data, when monitoring multiple processes
In after first the first process using the shared data, obtain the mark of first processor entrained by the first process, then needle
To each process in multiple processes in addition to the first process, the mark of processing entrained by the process is revised as first processor
Mark.
For example, based on the Futex (Fast userspace mutex, express user space mutexes) in Linux operation
Lock, it is assumed that it can determine that three processes need shared " shared data A ", these three processes are respectively as follows: process 1, process 2, process 3,
And assume that processor flag entrained by process 1 is " CPU1 ", processor flag entrained by process 2 is " CPU2 ", 3 institute of process
The processor flag of carrying is " CPU3 ", it is further assumed that the process 1 in these three processes is first use " shared data A "
Process, then processor flag entrained by process 2 can be revised as " CPU1 " from " CPU2 ", processor entrained by process 3
Mark is revised as " CPU1 " from " CPU3 ".
Based on the lock mechanism in operating system, determines there are when multiple shared datas, can first determine that discovery process
Sequentially, then after monitoring in multiple processes first the first process using the shared data, first process of acquisition is taken
The first processor of band identifies, will be entrained by the process then for each process in multiple processes in addition to the first process
Processing mark be revised as first processor mark.
For example, based on the Futex lock 1 in Linux operation, it may be determined that two processes need shared " shared data B ", this two
A process is respectively as follows: process 4, process 5, and based on the Futex lock 2 in Linux operation, it is shared " shared to determine that two processes need
Data C ", the two processes are respectively as follows: process 6, process 7.And assume processor flag entrained by process 4 be " CPU4 ", into
Processor flag entrained by journey 5 is " CPU5 ", processor flag entrained by process 6 is " CPU6 ", place entrained by process 7
Reason device is identified as " CPU7 ", it is further assumed that the sequence of discovery process are as follows: process 4, process 5, process 6, process 7, it is further false
If process 4 is first process for using " shared data B ", then processor flag entrained by process 5 can be repaired from " CPU5 "
It is changed to " CPU4 ".Find that process 6 and process 7 share " shared data C " and process 6 is first use " shared data C " again
The processor flag that process 7 carries then can be revised as " CPU4 " from " CPU7 " by process.
It based on the lock mechanism in operating system, is determining there are when multiple shared datas, and there are a process needs
When sharing multiple shared datas, and the sequence of discovery process is determined first, then make when monitoring in multiple processes first
After the first process of the shared data, the mark of first processor entrained by the first process is obtained, multiple processes are then directed to
In each process in addition to the first process, the mark of processing entrained by the process is revised as first processor mark.
For example, based on the Futex lock 3 in Linux operation, it may be determined that two processes need shared " shared data E ", this two
A process is respectively as follows: process 8, process 9, and based on the Futex lock 2 in Linux operation, it is shared " shared to determine that two processes need
Data F ", the two processes are respectively as follows: process 9, process 10.And assume processor flag entrained by process 8 be " CPU8 ", into
Processor flag entrained by journey 9 is " CPU9 ", processor flag entrained by process 10 is " CPU10 ", it is assumed that discovery process
Sequence are as follows: process 8, process 9, process 10 then can will it is further assumed that process 8 is first process using shared data E
Processor flag entrained by process 9 is revised as " CPU8 " from " CPU9 ", at this point, finding that process 9 and process 10 are shared " shared again
Processor flag entrained by process 10 is then also revised as " CPU8 " from " CPU10 " by data F ".
It in the specific implementation, will be entrained by the process when each process being directed in multiple processes in addition to the first process
Processing mark be revised as first processor mark when, in order to accelerate modify speed, promoted modification efficiency, monitor it is multiple into
After first in journey uses the first process of shared data, processor flag entrained by the first process is obtained, then one by one
Judge processor flag entrained by remaining process under the shared data whether with processor mark entrained by first process
It is sensible same, if it is not the same, processor flag entrained by the process is then revised as processor mark entrained by the first process
Know.
It in the specific implementation, will be entrained by the process when each process being directed in multiple processes in addition to the first process
Processing mark be revised as first processor mark when, monitoring first in multiple processes using shared data first
After process, processor flag entrained by the first process is obtained, any process being then directed in remaining process of shared data,
While the process is waken up, judge processor flag entrained by the process whether with processing mark entrained by the first process
Whether knowledge is identical, if it is not the same, the mark of first processor entrained by the first process is then sent to the process, and by pre-
Processor flag entrained by the process is revised as the first processing mark by the structural body first defined.
Within the load balancing period, for the process under any processor in multi-core processor, the tool of scheduler judgement
Body process, reference can be made to Fig. 3.
S301, judge whether the amount of migration is zero, if it is not, then going to step S302, otherwise, terminate process.
S302, judge processor flag that process in the queue of current processor carries whether the mark with current processor
It is sensible same, if it is, going to step S303, otherwise, go to step S304.
S303, without process migration.
Under processor corresponding to S304, the processor flag for carrying the process migration to the process.
Specifically, scheduler can be by calling pull_task () function by the process migration to the processing carried
Under the corresponding processor of device mark.
S305, judge whether there are also other processes not judged in the queue of current processor, if it is, going to step
Otherwise rapid S302 terminates process.
According to the above as can be seen that when, there are when shared data, obtaining accessed this first in multi-core operation system
First processor entrained by first process of shared data identifies and needs to access the second process of the shared data, then exists
Second processor entrained by second process mark with the first process carry first processor mark it is not identical when, by second into
Processor flag entrained by journey modifies first processor mark, finally within the load balancing period, under any processor
The second process, scheduler judge processor flag entrained by the second process and the processor identify whether it is identical, if
It is not identical, then by under the second process migration to first processor, thus the processor entrained by remaining process of shared data
It, can be by under remaining process migration to first processor, in this way, can be by shared number when mark and not identical first processor mark
According to multiple processes all migrate to same processor, in this way, when multiple processes of shared data reuse the shared data,
Without shared data is placed under respective caching respectively again, but shared data is placed into the caching of first processor
In, therefore, it is able to ascend the Buffer Utilization of operating system, so as to promote the execution efficiency of process.In addition, scheduler exists
Before migrating processes, can first determine that whether process migration amount is zero, in the case where process migration amount is zero, scheduler does not just have to
It is directed to each processor again, judges whether processor flag entrained by the process under it with the processor identifies whether phase
Together, without again by under the second process migration to first processor, so that the execution efficiency of scheduler can also be promoted.
Based on the same technical idea, the embodiment of the present invention also provides a kind of load balancing dress for multi-core processor
It sets, as shown in figure 4, the device can include:
Module 402 is obtained, for being directed at least one shared data, obtains the first process for having accessed the shared data
Entrained first processor identifies and needs to access the second process of the shared data；
Feedback module 403, for judging the mark of second processor entrained by second process and first processing
Device identify whether it is identical, if not identical, by processor flag entrained by second process be revised as it is described first processing
Device mark；
Scheduler module 404, within the load balancing period, for the second process under any processor, described in judgement
Identifying whether for processor flag entrained by second process and the processor is identical, if it is not the same, then by described second into
Journey is migrated to the first processor.
Preferably, obtaining module 402, it is specifically used for:
Determine the multiple processes for accessing the shared data；
After first in the multiple process is monitored using the first process of the shared data, described first is obtained
The mark of first processor entrained by process；
Preferably, feedback module 403, is specifically used for:
For each process in the multiple process in addition to first process, by processing entrained by the process
Device mark is revised as the first processor mark.
Preferably, further includes: initialization module 401；
Initialization module 401 is used in initialization, for any process, by processor mark entrained by the process
Know and assigns the process.
Preferably, feedback module 403, is also used to:
After processor flag entrained by second process to be revised as to the first processor mark, statistics is repaired
It is changed to the number of processes of the first processor mark；
According to the number of processes, process migration amount is determined；
Scheduler module judge processor flag entrained by the process and the processor identify whether it is identical before,
Judge that the process migration amount is not zero.
The embodiment of the present invention also provides a kind of calculating equipment, which is specifically as follows desktop computer, portable
Computer, smart phone, tablet computer, personal digital assistant (Personal Digital Assistant, PDA) etc..The meter
Calculating equipment may include central processing unit (Center Processing Unit, CPU), memory, input-output apparatus etc.,
Input equipment may include keyboard, mouse, touch screen etc., and output equipment may include display equipment, such as liquid crystal display
(Liquid Crystal Display, LCD), cathode-ray tube (Cathode Ray Tube, CRT) etc..
Memory may include read-only memory (ROM) and random access memory (RAM), and provide storage to processor
The program instruction and data stored in device.In embodiments of the present invention, memory can be used for storing for multi-core processor
The program of load-balancing method.
Processor is by the program instruction for calling memory to store, and processor according to the program instruction of acquisition for executing
State any method.
The embodiment of the present invention also provides a kind of computer storage medium, for being stored as calculating used in above-mentioned calculating equipment
Machine program instruction, it includes the programs for executing the above-mentioned load-balancing method for multi-core processor.
The computer storage medium can be any usable medium or data storage device that computer can access, packet
Include but be not limited to magnetic storage (such as floppy disk, hard disk, tape, magneto-optic disk (MO) etc.), optical memory (such as CD, DVD,
BD, HVD etc.) and semiconductor memory (such as it is ROM, EPROM, EEPROM, nonvolatile memory (NAND FLASH), solid
State hard disk (SSD)) etc..
To sum up, when in multi-core operation system there are when shared data, obtain first accessed the first of the shared data into
First processor entrained by journey identifies and needs to access the second process of the shared data, then entrained by the second process
When second processor mark and the not identical first processor mark that the first process carries, by processor entrained by the second process
Mark modification first processor mark, finally within the load balancing period, for the second process under any processor, scheduler
Judge processor flag entrained by the second process and the processor identify whether it is identical, if it is not the same, then by second into
Journey is migrated to first processor, thus the processor flag entrained by remaining process of shared data and first processor mark
It, can be by under remaining process migration to first processor, in this way, can all migrate multiple processes of shared data when knowing not identical
To same processor, in this way, not having to when multiple processes of shared data reuse the shared data again respectively by shared number
According to being placed under respective caching, but shared data is placed into the caching of first processor, therefore, is able to ascend operation
The Buffer Utilization of system, so as to promote the execution efficiency of process.In addition, scheduler is before migrating processes, it can first really
Determine whether process migration amount is zero, in the case where process migration amount is zero, scheduler does not just have to sentence for each processor again
Processor flag entrained by the process under it of breaking whether with the processor identify whether it is identical, without again by the second process
It migrates to first processor, so that the execution efficiency of scheduler can also be promoted.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method or computer program product.
Therefore, complete hardware embodiment, complete software embodiment or embodiment combining software and hardware aspects can be used in the present invention
Form.It is deposited moreover, the present invention can be used to can be used in the computer that one or more wherein includes computer usable program code
The shape for the computer program product implemented on storage media (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.)
Formula.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of load-balancing method for multi-core processor characterized by comprising
For at least one shared data, acquisition has accessed first processor mark entrained by the first process of the shared data
Know and need to access the second process of the shared data；
It is identical to judge that the mark of second processor entrained by second process is identified whether with the first processor, if not phase
Together, then processor flag entrained by second process first processor is revised as to identify；
Within the load balancing period, for the second process under any processor, scheduler judges entrained by second process
Processor flag and the processor identify whether it is identical, if it is not the same, then by second process migration to described
Under one processor.
2. the method as described in claim 1, which is characterized in that described to obtain the first process institute for having accessed the shared data
The first processor of carrying identifies and needs to access the second process of the shared data, comprising:
Determine the multiple processes for accessing the shared data；
After first in the multiple process is monitored using the first process of the shared data, first process is obtained
Entrained first processor mark；
Processor flag entrained by second process is revised as the first processor mark, comprising:
For each process in the multiple process in addition to first process, by processor mark entrained by the process
Knowledge is revised as the first processor mark.
3. method according to claim 2, which is characterized in that taken obtaining the first process for having accessed the shared data
Before the first processor of band identifies and needs to access the second process of the shared data, further includes:
In initialization, for any process, processor flag entrained by the process is assigned to the process.
4. the method as described in claim 1, which is characterized in that modified by processor flag entrained by second process
After first processor mark, further includes:
Statistics is revised as the number of processes of the first processor mark；
According to the number of processes, process migration amount is determined；
Scheduler judge processor flag entrained by the process and the processor identify whether it is identical before, also wrap
It includes:
Judge that the process migration amount is not zero.
5. a kind of load balancing apparatus for multi-core processor characterized by comprising
Module is obtained, for being directed at least one shared data, acquisition has been accessed entrained by the first process of the shared data
First processor mark and need to access the second process of the shared data；
Feedback module, for judge second processor entrained by second process mark with the first processor identify be
It is no identical, if not identical, processor flag entrained by second process is revised as the first processor and is identified；
Scheduler module, for for the second process under any processor, judging second process within the load balancing period
Identifying whether for entrained processor flag and the processor is identical, if it is not the same, then extremely by second process migration
Under the first processor.
6. device as claimed in claim 5, which is characterized in that the acquisition module is specifically used for:
Determine the multiple processes for accessing the shared data；
After first in the multiple process is monitored using the first process of the shared data, first process is obtained
Entrained first processor mark；
The feedback module, is specifically used for:
For each process in the multiple process in addition to first process, by processor mark entrained by the process
Knowledge is revised as the first processor mark.
7. device as claimed in claim 6, which is characterized in that further include: initialization module；
The initialization module, for for any process, processor flag entrained by the process being assigned in initialization
Give the process.
8. device as claimed in claim 5, which is characterized in that the feedback module is also used to:
After processor flag entrained by second process to be revised as to the first processor mark, statistics is revised as
The number of processes of the first processor mark；
According to the number of processes, process migration amount is determined；
Scheduler module judge processor flag entrained by the process and the processor identify whether it is identical before, judgement
The process migration amount is not zero.
9. a kind of calculating equipment characterized by comprising
Memory, for storing program instruction；
Processor requires 1 to 4 according to the program execution benefit of acquisition for calling the program instruction stored in the memory
Described in any item methods.
10. a kind of computer storage medium, which is characterized in that the computer storage medium is stored with the executable finger of computer
It enables, the computer executable instructions are for making the computer perform claim require 1 to 4 described in any item methods.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112346879A (en) * | 2020-11-06 | 2021-02-09 | 网易（杭州）网络有限公司 | Process management method and device, computer equipment and storage medium |
| CN113515388A (en) * | 2021-09-14 | 2021-10-19 | 统信软件技术有限公司 | Process scheduling method and device, computing equipment and readable storage medium |
| CN115617494A (en) * | 2022-12-06 | 2023-01-17 | 中科方德软件有限公司 | Process scheduling method and device in multi-CPU environment, electronic equipment and medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102947807A (en) * | 2010-06-14 | 2013-02-27 | 富士通株式会社 | Multi-core processor system, cache coherency control method, and cache coherency control program |
| CN103092788A (en) * | 2012-12-24 | 2013-05-08 | 华为技术有限公司 | Multi-core processor and data access method |
| US20140359225A1 (en) * | 2013-05-28 | 2014-12-04 | Electronics And Telecommunications Research Institute | Multi-core processor and multi-core processor system |
| CN105095144A (en) * | 2015-07-24 | 2015-11-25 | 中国人民解放军国防科学技术大学 | Multi-core Cache consistency maintenance method and device based on fence and lock |
| US20170103022A1 (en) * | 2015-06-10 | 2017-04-13 | Mobileye Vision Technologies Ltd. | System on chip with image processing capabilities |
-
2017
- 2017-11-29 CN CN201711229966.2A patent/CN109840151B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102947807A (en) * | 2010-06-14 | 2013-02-27 | 富士通株式会社 | Multi-core processor system, cache coherency control method, and cache coherency control program |
| CN103092788A (en) * | 2012-12-24 | 2013-05-08 | 华为技术有限公司 | Multi-core processor and data access method |
| US20140359225A1 (en) * | 2013-05-28 | 2014-12-04 | Electronics And Telecommunications Research Institute | Multi-core processor and multi-core processor system |
| US20170103022A1 (en) * | 2015-06-10 | 2017-04-13 | Mobileye Vision Technologies Ltd. | System on chip with image processing capabilities |
| CN105095144A (en) * | 2015-07-24 | 2015-11-25 | 中国人民解放军国防科学技术大学 | Multi-core Cache consistency maintenance method and device based on fence and lock |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112346879A (en) * | 2020-11-06 | 2021-02-09 | 网易（杭州）网络有限公司 | Process management method and device, computer equipment and storage medium |
| CN112346879B (en) * | 2020-11-06 | 2023-08-11 | 网易（杭州）网络有限公司 | Process management method, device, computer equipment and storage medium |
| CN113515388A (en) * | 2021-09-14 | 2021-10-19 | 统信软件技术有限公司 | Process scheduling method and device, computing equipment and readable storage medium |
| CN115617494A (en) * | 2022-12-06 | 2023-01-17 | 中科方德软件有限公司 | Process scheduling method and device in multi-CPU environment, electronic equipment and medium |
| WO2024119988A1 (en) * | 2022-12-06 | 2024-06-13 | 中科方德软件有限公司 | Process scheduling method and apparatus in multi-cpu environment, electronic device, and medium |
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