CN109829240B - Method for optimizing integrated circuit performance - Google Patents
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- CN109829240B CN109829240B CN201910121601.0A CN201910121601A CN109829240B CN 109829240 B CN109829240 B CN 109829240B CN 201910121601 A CN201910121601 A CN 201910121601A CN 109829240 B CN109829240 B CN 109829240B
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Abstract
The invention provides an optimization method of integrated circuit structure performance, which comprises the following steps: providing an integrated circuit structure provided with at least one transistor; acquiring the performance of the integrated circuit structure; determining the performance of the transistor in accordance with the performance of the integrated circuit structure; determining a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor; wherein the stressed insulating film is used to change the performance of the transistor. The optimization method meets the requirement of different parts of a circuit in SoC design on the performance of a transistor, thereby reducing the power consumption of the SoC as much as possible under the condition of ensuring that the performance of the circuit is met, particularly reducing the power consumption of the SoC with extremely low subthreshold power consumption, and further improving the working energy efficiency of the SoC.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for optimizing the performance of an integrated circuit.
Background
In the manufacturing process of an integrated circuit, in order to meet the requirements of a circuit on different performances of devices, transistors with different threshold voltage versions are generally manufactured for the same type of transistors, so as to meet different circuit design requirements, for example, a high-threshold voltage device is mostly used for forming a low-power consumption or low-speed circuit part, a low-threshold voltage device is mostly used for forming a high-speed circuit part, and a normal-threshold voltage device is mostly used for forming a medium-speed circuit part.
However, the limited number of threshold voltage controls enables the control of device performance only in a very limited coarse grain range, and in order to meet circuit performance, transistors with performance far exceeding circuit requirements are often selected, thereby consuming unnecessary energy.
Disclosure of Invention
In view of the above, in order to solve the above problems, the present invention provides a method for optimizing performance of an integrated circuit, which includes the following steps:
a method of optimizing performance of an integrated circuit, the method comprising:
providing an integrated circuit provided with at least one transistor;
acquiring the performance requirement of the integrated circuit;
determining the performance of the transistor in accordance with the performance requirements of the integrated circuit;
determining a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor;
wherein the stressed insulating film is used to change the performance of the transistor.
Preferably, in the above optimization method, the determining a stressed insulating film to cover a gate structure of the transistor according to the performance of the transistor includes:
determining the type of a stress insulating film covering a gate structure of the transistor according to the performance of the transistor;
the types of the stress insulating film include: a tensile stress insulating film, a compressive stress insulating film, and a non-stress insulating film.
Preferably, in the above optimization method, the determining a stressed insulating film to cover a gate structure of the transistor according to the performance of the transistor includes:
the stress density of a stressed insulating film covering a gate structure of the transistor is determined according to the performance of the transistor.
Preferably, in the above optimization method, the determining a stress density of the stressed insulating film covering the gate structure of the transistor includes:
determining the stress density of the stress insulating film from a preset stress density list of the stress insulating film;
or, determining the stress density of the stress insulating film in at least one continuous interval from a preset stress density list of the stress insulating film.
Preferably, in the above optimization method, the determining a stress density of the stressed insulating film covering the gate structure of the transistor further includes:
degenerating the determined stress density of the insulating film.
Preferably, in the above optimization method, the obtaining performance of the integrated circuit structure includes:
dividing the integrated circuit into a plurality of sub-circuit areas, wherein each sub-circuit area at least comprises a current-stage trigger or latch, a front-end combination logic circuit and a preceding-stage trigger or latch;
and acquiring the performance of the sub-circuit area according to the clock signal frequency and the duty ratio connected with the current stage of trigger or latch, the establishment time, the holding time and the output delay time of the current stage of trigger or latch, and the delay time of the front-end combinational logic circuit.
Preferably, in the above optimization method, the determining a stressed insulating film covering the gate structure of the transistor includes:
determining a signal flow order of the sub-circuit regions in the integrated circuit;
and determining a stress insulating film covering the gate structure of the transistor according to the performance of the transistor for the transistor in the sub-circuit region according to the signal flow sequence.
Preferably, in the above optimization method, the determining, for the transistors in the sub circuit region in accordance with the signal flow order, a stressed insulating film to be covered onto the gate structures of the transistors in accordance with the performance of the transistors includes:
and according to the determined stress insulating film covered by the transistor gate structure in the prior stage trigger or latch circuit, covering the stress insulating film of the transistor gate structure in the present stage trigger or latch circuit.
Preferably, in the above optimization method, the optimization method further includes:
acquiring performance parameters of the transistor;
wherein the performance parameters at least include gate width, gate length, and fork index.
Preferably, in the above optimization method, the optimization method further includes:
and determining whether the source contact area and the drain contact area of the transistor are doped with Ge element according to the performance of the transistor.
Preferably, in the above optimization method, the optimization method further includes:
evaluating performance requirements of the integrated circuit using at least one set of device models, wherein each transistor corresponds to a set of device models;
each model in the group of models respectively corresponds to the model of the transistor under different stress insulating film type parameter values, stress density parameter values and Ge element doped parameter values of a source contact region and a drain contact region;
each transistor selects a target model from a group of models corresponding to the transistor according to at least one selected parameter value from among a stress insulation film type parameter value, a stress density parameter value, a source contact region doping Ge element parameter value and a drain contact region doping Ge element parameter value.
Preferably, in the above optimization method, the optimization method further includes:
optimizing the integrated circuit according to the target model selected by each transistor in the integrated circuit to obtain a gate width parameter value, a gate length parameter value, an interdigital parameter value, a sub-circuit area performance parameter value and a sub-circuit area power consumption parameter value of the optimized transistor;
and carrying out optimization tests in an optimization environment of the type parameter value, the stress density parameter value, the Ge element doping parameter value of the source contact area and the drain contact area of the stress insulation film to obtain a plurality of optimization schemes.
Preferably, in the above optimization method, the optimization method further includes:
obtaining the plurality of optimization schemes;
any one of the optimization schemes corresponds to at least one parameter value of a gate width parameter value, a gate length parameter value, an interdigital parameter value, a type parameter value of a stress insulation film, a stress density parameter value, a Ge element doping parameter value of a source contact area and a drain contact area of the transistor, and a performance parameter value of a sub-circuit area and a power consumption parameter value of the sub-circuit area under the corresponding parameter values;
and selecting one optimization scheme which meets optimization requirements and has the lowest power consumption parameter value of the sub-circuit area from the multiple optimization schemes as a target optimization scheme.
Compared with the prior art, the invention has the following beneficial effects:
the optimization method meets the requirement of different parts of a circuit in SoC design on the performance of the transistor, thereby reducing the power consumption of the SoC as much as possible under the condition of ensuring that the performance of the circuit is met, particularly reducing the power consumption of the SoC with extremely low subthreshold power consumption, and further improving the working energy efficiency of the SoC.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for optimizing performance of an integrated circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a system for optimizing performance of an integrated circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic flowchart of an optimization method for integrated circuit performance according to an embodiment of the present invention, where the optimization method includes:
s101: an integrated circuit is provided that is provided with at least one transistor.
In this step, the specific structure of the integrated circuit is not limited, and the integrated circuit includes at least one transistor.
S102: performance requirements of the integrated circuit are obtained.
In this step, the specific manner of obtaining the performance requirement of the integrated circuit is not limited, and the parameters characterizing the performance requirement of the integrated circuit are various, and the performance requirement of the integrated circuit can be interpreted according to specific situations.
S103: the performance of the transistor is determined in accordance with the performance requirements of the integrated circuit.
In this step, the performance requirements of the integrated circuit can be changed by changing the performance of the transistor, and therefore, the performance of the transistor can be determined according to the performance requirements required of the integrated circuit.
S104: determining a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor;
wherein the stressed insulating film is used to change the performance of the transistor.
In this step, in order to improve the performance of the transistor, an insulating film having a suitable stress is generally covered on the gate structure of the transistor, for example, a stressed insulating film having a tensile stress is covered on the gate structure of the NMOS transistor to improve the performance of the NMOS transistor, and a stressed insulating film having a compressive stress is covered on the gate structure of the PMOS transistor to improve the performance of the PMOS transistor.
Similarly, in order to reduce the performance of the transistor, an insulating film with stress is covered on the gate structure of the transistor, for example, a stressed insulating film with non-tensile stress is covered on the gate structure of the NMOS transistor to reduce the performance of the NMOS transistor, and a stressed insulating film with non-compressive stress is covered on the gate structure of the PMOS transistor to reduce the performance of the PMOS transistor.
Therefore, a larger number of transistors with controllable performance ranges can be generated through the optimization, and the accurate matching of different parts of a circuit in the SoC (System-on-Chip) design to the performance requirements of the transistors is met, so that the power consumption of the SoC, especially the power consumption of the SoC with extremely low subthreshold power consumption, is reduced as much as possible under the condition that the circuit performance is ensured to be met, and the working energy efficiency of the SoC is further improved.
Further, the determining a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor includes:
determining the type of a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor;
the types of the stress insulating film include: a tensile stress insulating film, a compressive stress insulating film, and a non-stress insulating film.
In the embodiment, the compressive stress insulating film can reduce the carrier mobility in the channel of the NMOS transistor, the performance of the NMOS transistor is reduced, and when the requirement on the performance of the NMOS transistor in a circuit is not high, the transistor with the structure can further reduce the power consumption of the circuit on the premise of meeting the circuit performance requirement.
Compared with a compressive stress insulating film when the stress-free insulating film is used, the carrier mobility in the channel of the NMOS transistor is higher, the transistor performance is higher, but compared with the tensile stress insulating film, the carrier mobility in the channel of the NMOS transistor is lower, the transistor performance is lower, and when the requirement on the performance of the NMOS transistor in a circuit is not low or low, the power consumption of the circuit can be further reduced by using the transistor with the structure on the premise of meeting the circuit performance requirement.
The tensile stress insulating film can reduce the carrier mobility in the channel of the PMOS transistor, the performance of the PMOS transistor is reduced, and when the performance requirement of the PMOS transistor in a circuit is not high, the transistor with the structure can further reduce the power consumption of the circuit on the premise of meeting the performance requirement of the circuit.
Compared with a tensile stress insulating film, the non-stress insulating film has higher carrier mobility in a channel of the PMOS transistor and higher performance of the PMOS transistor, but compared with a compressive stress insulating film, the non-stress insulating film has lower carrier mobility in the channel of the PMOS transistor and lower performance of the transistor, and when the requirement on the performance of the PMOS transistor in a circuit is not high or low, the transistor with the structure can further reduce the power consumption of the circuit on the premise of meeting the performance requirement of the circuit.
As is apparent from the above description, by changing the type of the stress insulating film covering the gate structure of the transistor, the performance of the transistor can be flexibly changed.
Further, the determining a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor includes:
determining the stress density of the stress insulating film covering the gate structure of the transistor according to the performance of the transistor.
In this embodiment, the stress densities of the stress insulating films of the same type covered on the gate structures of the transistors of the same type may be different, that is, the stress densities of the stress insulating films of the same type covered on the gate structures of the transistors of the same type may be multiple, so that the transistors with different performances are provided through the difference of the stress densities, different requirements of designing different circuits on the performances of the transistors can be better satisfied, and the power consumption can be reduced to the maximum extent.
Further, the determining a stress density of a stressed insulating film covering a gate structure of the transistor includes:
determining the stress density of the stress insulating film from a preset stress density list of the stress insulating film;
or, determining the stress density of the stress insulating film in at least one continuous interval from a preset stress density list of the stress insulating film.
In this embodiment, the list of stress densities of the predetermined stressed insulating film is predetermined, and may be obtained through experimental simulation or experimental measurement, and the determination manner is not limited, and generally, the stress density value corresponds to the carrier mobility and the threshold voltage of the transistor, and the carrier mobility and the threshold voltage characterize the influence on the transistor performance.
That is, different performance requirements of transistors may correspond to different stress densities.
A type of transistor corresponds to a list of stress densities of a predetermined stressed insulating film, and a plurality of stress density values exist in the list of stress densities of the predetermined stressed insulating film, each stress density value corresponding to a carrier mobility and a threshold voltage of the type of transistor. Two adjacent stress density values define a continuous interval between them. According to the required transistor performance, the required carrier mobility and threshold voltage can be obtained, and the required stress density value can be obtained according to the carrier mobility and the threshold voltage; or obtaining the stress density value which best meets the transistor performance requirement from the fitted relation between the stress density value and the carrier mobility and the relation between the stress density value and the threshold voltage.
Since the relationship between the stress density value and the carrier mobility and the relationship between the stress density value and the threshold voltage are generally nonlinear or approximately linear, in order to reduce the error in solving the stress density values, the interval between adjacent stress density value sampling points is small, and a plurality of stress density values are often sampled, so that the most satisfactory stress density value can be obtained by determining the stress density of the stress insulating film in at least one continuous interval.
Further, the determining a stress density of a stressed insulating film covering a gate structure of the transistor further includes:
degenerating the determined stress density of the insulating film.
In this embodiment, on the basis of the same type of stress insulating film, when the difference or relative difference between the stress density values is smaller than a preset value, a plurality of close values are taken as one and the same value. And further reducing the number of different stress density values of the stress insulation films of the same type, thereby reducing the manufacturing cost.
It should be noted that the value of the preset value may be determined according to the process cost, and is not limited in the embodiment of the present invention.
Further, the obtaining performance of the integrated circuit structure includes:
dividing the integrated circuit into a plurality of sub-circuit areas, wherein each sub-circuit area at least comprises a current stage trigger or latch, a front end combination logic circuit and a previous stage trigger or latch;
and acquiring the performance of the sub-circuit area according to the clock signal frequency and the duty ratio connected with the current stage of trigger or latch, the establishment time, the holding time and the output delay time of the current stage of trigger or latch, and the delay time of the front-end combinational logic circuit.
In this embodiment, the data input of a flip-flop or latch is terminated by a data input signal, and the combinational logic that generates the data input signal is referred to as the front-end combinational logic circuit of the flip-flop or latch, i.e., the front-end is with respect to the flip-flop or latch of the present stage.
Where the definition of front-end and front-end stages is distinguished, the input signals of the front-end combinational logic circuit come directly from the data output of one or several flip-flops or latches, which are then referred to as front-stage flip-flops or latches in relation to the present stage flip-flops or latches.
The clock signal frequency and duty ratio connected with the present stage of flip-flop or latch, the setup time, hold time and output delay time of the present stage of flip-flop or latch, and the delay time of the front-end combinational logic circuit constitute the performance requirement of the sub-circuit region, so that the performance requirement of the transistor of the sub-circuit region is used as the constraint condition for optimizing the subsequent integrated circuit.
Further, the determining a stressed insulating film covering to the gate structure of the transistor includes:
determining a signal flow order of the sub-circuit regions in the integrated circuit;
determining a stress insulation film covering to a gate structure of the transistor for the transistor in the sub-circuit region in accordance with the performance of the transistor in accordance with the signal flow order.
In this embodiment, signal flow refers to the path that a signal propagates within an integrated circuit, and signal flow order refers to the order of propagation of a signal from an input to an output on the propagation path.
The optimization according to the signal flow sequence is a better scheme, the number of unknown parameters is less from the point of solving the mathematical inequality, iteration can be reduced from the point of view of effect, and the optimization process can be accelerated.
Further, the determining, for the transistors in the sub circuit region in accordance with the signal flow order, a stressed insulating film covering the gate structures of the transistors in accordance with the performance of the transistors includes:
and according to the determined stress insulating film covered by the transistor gate structure in the prior stage trigger or latch circuit, covering the stress insulating film of the transistor gate structure in the present stage trigger or latch circuit.
Further, the optimization method further comprises:
acquiring performance parameters of the transistor;
wherein the performance parameters at least include gate width, gate length, and fork index.
In this embodiment, other parameters of the transistor, including, but not limited to, gate width, gate length, and number of fingers, for example, are also obtained while determining the stressed insulating film in the integrated circuit overlying the gate structure of the transistor.
This parameter is also an important parameter for the performance of the reaction transistor.
Further, the optimization method further comprises:
and determining whether the source contact area and the drain contact area of the transistor are doped with Ge element according to the performance of the transistor.
In this embodiment, ge is doped in two P-type regions of the PMOS transistor, i.e., the source contact region and the drain contact region, to form SiGe, which generates compressive stress in the channel direction of the PMOS transistor, thereby improving the performance of the PMOS transistor.
SiGe is formed by doping Ge elements in two N-type regions of an NMOS transistor, namely a source contact region and a drain contact region, and compressive stress is generated in the channel direction of the NMOS transistor, so that the performance of the NMOS transistor is reduced.
Therefore, whether to improve the performance of the PMOS transistor or not can be determined by doping the source contact area and the drain contact area of the transistor with Ge element, and the performance and the power consumption of the NMOS transistor can be reduced.
Further, the optimization method further comprises:
evaluating performance requirements of the integrated circuit using at least one set of device models, wherein each transistor corresponds to a set of device models;
each model in the group of models respectively corresponds to the model of the transistor under different stress insulating film type parameter values, stress density parameter values and Ge element doped parameter values of a source contact region and a drain contact region;
each transistor selects a target model from a group of models corresponding to the transistor according to at least one selected parameter value from among a stress insulation film type parameter value, a stress density parameter value, a source contact region doping Ge element parameter value and a drain contact region doping Ge element parameter value.
In this embodiment, the device model is a mathematical equation describing the electrical characteristics (I-V characteristics and C-V characteristics) of the transistor, and is one of the bases for circuit simulation and analysis.
Further, the optimization method further comprises:
optimizing the integrated circuit according to the target model selected by each transistor in the integrated circuit to obtain a gate width parameter value, a gate length parameter value, an interdigital number parameter value, a sub-circuit area performance parameter value and a sub-circuit area power consumption parameter value of the optimized transistor;
and carrying out optimization tests in an optimization environment of the type parameter value, the stress density parameter value, the Ge element doping parameter value of the source contact area and the drain contact area of the stress insulation film to obtain a plurality of optimization schemes.
Further, the optimization method further comprises:
obtaining the plurality of optimization schemes;
any one of the optimization schemes corresponds to at least one parameter value of a gate width parameter value, a gate length parameter value, an interdigital parameter value, a type parameter value of a stress insulation film, a stress density parameter value, a Ge element doping parameter value of a source contact area and a drain contact area of the transistor, and a performance parameter value of a sub-circuit area and a power consumption parameter value of the sub-circuit area under the corresponding parameter values;
and selecting one optimization scheme which meets optimization requirements and has the lowest power consumption parameter value of the sub-circuit area from the multiple optimization schemes as a target optimization scheme.
In the prior art, one transistor corresponds to only one model, which has the advantage of simplicity and the disadvantage of inaccuracy in view of different stress densities.
In the embodiment of the invention, the device characteristics under different stress densities are respectively described by adopting a plurality of models, the method has the advantages of higher precision, and the best model can be obtained by selecting the models according to the type of the stress insulating film, the stress density, whether the source contact region and the drain contact region are doped with Ge and the like in practical application.
Based on all the above embodiments of the present invention, in another embodiment of the present invention, there is provided an optimization system for performance of an integrated circuit, the optimization system at least includes:
a device model module 21 for evaluating performance and power consumption of the integrated circuit;
a constraint generating module 22 for generating constraints that must be followed by the optimization circuit in accordance with the relationships between the various parts of the integrated circuit;
a circuit optimization module 23 for searching a parameter value which makes the performance of the integrated circuit meet the requirement of lowest power consumption by optimizing an iterative process according to a constraint condition in a space of at least one parameter value among a type parameter of the stress insulating film, a stress density parameter value, a parameter value of Ge element doping of the source contact region and the drain contact region, and a gate length parameter, a gate width parameter and an interdigital number parameter of the transistor;
further, the device model module may provide a device model for a type of transistor, and the provided device model includes at least one of a stress insulating film type parameter value, a stress density parameter value, a source contact region doping Ge element parameter value, and a drain contact region doping Ge element parameter value;
or the device model module can provide a group of models for each type of transistor, wherein each model in the group of models respectively corresponds to the model of the transistor under different stress insulating film type parameter values, stress density parameter values and Ge element doping parameter values of a source contact region and a drain contact region;
each transistor selects a target model from a group of models corresponding to the transistor according to at least one selected parameter value from among a stress insulation film type parameter value, a stress density parameter value, a source contact region doping Ge element parameter value and a drain contact region doping Ge element parameter value.
Further, the constraint conditions include, but are not limited to, a clock signal frequency and a duty ratio to which the present stage flip-flop or latch is connected, a setup time, a hold time and an output delay time of the present stage flip-flop or latch, and a delay time of the front-end combinational logic circuit.
Further, the circuit optimization module at least comprises:
a new parameter generation submodule for generating a new parameter value in a space of at least one of a stress insulating film type parameter, a stress density parameter value, a source contact region and drain contact region Ge element doping parameter value, and a gate length parameter, a gate width parameter and an interdigital number parameter of the transistor;
and the circuit performance and power consumption calculation submodule is used for calculating the performance and power consumption of the circuit design according to the new parameter values and the device model selected by the device model module. It should be noted that, in order to ensure accuracy, calculation is generally performed based on a circuit simulation structure;
the constraint checking and optimizing structure updating submodule is used for checking whether the constraint condition is met or not according to the obtained performance and power consumption data, if the constraint condition is met and the power consumption is smaller than the minimum power consumption obtained by the circuit optimizing history, recording a new parameter value, and updating the minimum power consumption obtained by the optimizing history to be the power consumption corresponding to the current new parameter value;
and the control submodule is used for controlling the optimization iterative process to continuously and repeatedly execute the new parameter generation submodule, the circuit performance and power consumption calculation submodule and the constraint checking and optimization structure updating submodule, or the current optimal circuit design meets the design requirement, or the optimization iterative process is terminated when the iterative times exceed a threshold value.
Further, the optimization system further comprises:
the circuit dividing module is used for dividing the integrated circuit into a plurality of sub-circuit areas, and each sub-circuit area at least comprises a current-stage trigger or latch, a front-end combination logic circuit and a preceding-stage trigger or latch.
In this embodiment, the data input of a flip-flop or latch is terminated by a data input signal, and the combinational logic that generates the data input signal is referred to as the front-end combinational logic circuit of the flip-flop or latch, i.e., the front-end is relative to the flip-flop or latch of the present stage.
Where the definition of front-end and front-end stages is distinguished, the input signals of the front-end combinational logic circuit come directly from the data output of one or several flip-flops or latches, which are then referred to as front-stage flip-flops or latches in relation to the present stage flip-flops or latches.
Further, the optimization system further comprises:
the circuit optimization scheduling module is used for determining the signal flow sequence of the sub-circuit area in the integrated circuit and optimizing the sub-circuit area according to the signal flow sequence.
In this embodiment, signal flow refers to the path that a signal propagates within an integrated circuit, and signal flow order refers to the order in which a signal propagates from an input to an output on a propagation path.
The optimization according to the signal flow sequence is a better scheme, from the viewpoint of solving the mathematical inequality, the number of unknown parameters is less, and from the aspect of effect, the iteration can be reduced, so that the optimization process can be accelerated.
The method for optimizing the performance of the integrated circuit provided by the invention is described in detail above, and the principle and the implementation of the invention are explained in the text by applying specific examples, and the description of the above examples is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A method for optimizing performance of an integrated circuit, the method comprising:
providing an integrated circuit provided with at least one transistor;
dividing the integrated circuit into a plurality of sub-circuit regions;
acquiring the performance requirement of the integrated circuit;
determining the performance of the transistor in accordance with the performance requirements of the integrated circuit;
determining a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor; the determining a stressed insulating film overlying a gate structure of the transistor, comprising: determining a signal flow order of the sub-circuit regions in the integrated circuit; determining a stressed insulating film covering a gate structure of a transistor in the sub circuit region according to the performance of the transistor according to the signal flow sequence;
wherein the stressed insulating film is used to change the performance of the transistor.
2. The optimization method according to claim 1, wherein the determining a stressed insulating film to cover a gate structure of the transistor according to the performance of the transistor comprises:
determining the type of a stressed insulating film covering a gate structure of the transistor according to the performance of the transistor;
the types of the stress insulating film include: a tensile stress insulating film, a compressive stress insulating film, and a non-stress insulating film.
3. The optimization method according to claim 1, wherein the determining a stressed insulating film to cover a gate structure of the transistor according to the performance of the transistor comprises:
the stress density of a stressed insulating film covering a gate structure of the transistor is determined according to the performance of the transistor.
4. The optimization method of claim 3, wherein said determining a stress density of a stressed insulating film overlying a gate structure of said transistor comprises:
determining the stress density of the stress insulating film from a preset stress density list of the stress insulating film;
or, determining the stress density of the stress insulating film in at least one continuous interval from a preset stress density list of the stress insulating film.
5. The optimization method of claim 4, wherein said determining a stress density of a stressed insulating film overlying a gate structure of said transistor further comprises:
degenerating the determined stress density of the insulating film.
6. The optimization method of claim 1, wherein each of the sub-circuit regions comprises at least a present stage flip-flop or latch, a front end combinational logic circuit and a previous stage flip-flop or latch, and the obtaining the performance of the integrated circuit structure comprises:
and acquiring the performance of the sub-circuit area according to the clock signal frequency and the duty ratio connected with the current stage of trigger or latch, the establishment time, the holding time and the output delay time of the current stage of trigger or latch, and the delay time of the front-end combinational logic circuit.
7. The optimization method according to claim 6, wherein the determining, for the transistors in the sub circuit region in accordance with the signal flow order, the stressed insulating films to be covered onto the gate structures of the transistors in accordance with the performances of the transistors includes:
and according to the determined stress insulating film covered by the transistor gate structure in the prior stage trigger or latch circuit, covering the stress insulating film of the transistor gate structure in the present stage trigger or latch circuit.
8. The optimization method according to claim 7, further comprising:
acquiring performance parameters of the transistor;
wherein the performance parameters include at least gate width, gate length, and fork index.
9. The optimization method of claim 8, further comprising:
and determining whether the source contact area and the drain contact area of the transistor are doped with Ge element according to the performance of the transistor.
10. The optimization method according to claim 9, further comprising:
evaluating performance requirements of the integrated circuit using at least one set of device models, wherein each transistor corresponds to a set of device models;
each model in the group of device models respectively corresponds to the model of the transistor under different stress insulating film type parameter values, stress density parameter values and Ge element doped parameter values of a source contact region and a drain contact region;
and selecting a target model from a group of models corresponding to the transistors according to at least one selected parameter value in the type parameter value of the stress insulating film, the stress density parameter value and the Ge-doped parameter value of the source contact area and the drain contact area of each transistor.
11. The optimization method according to claim 10, further comprising:
optimizing the integrated circuit according to the target model selected by each transistor in the integrated circuit to obtain a gate width parameter value, a gate length parameter value, an interdigital number parameter value, a sub-circuit area performance parameter value and a sub-circuit area power consumption parameter value of the optimized transistor;
and carrying out optimization tests in an optimization environment of the type parameter value, the stress density parameter value, the Ge element doping parameter value of the source contact area and the drain contact area of the stress insulation film to obtain a plurality of optimization schemes.
12. The optimization method according to claim 11, further comprising:
obtaining the plurality of optimization schemes;
any one of the optimization schemes corresponds to at least one parameter value of a gate width parameter value, a gate length parameter value, an interdigital number parameter value, a type parameter value of a stress insulation film, a stress density parameter value, a Ge element doping parameter value of a source contact area and a drain contact area of the transistor, and a performance parameter value of a sub-circuit area and a power consumption parameter value of the sub-circuit area under the corresponding parameter values;
and selecting one optimization scheme which meets optimization requirements and has the lowest power consumption parameter value of the sub-circuit area from the multiple optimization schemes as a target optimization scheme.
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