CN109828934A - Internal storage access chip and device - Google Patents
Internal storage access chip and device Download PDFInfo
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- CN109828934A CN109828934A CN201811649998.2A CN201811649998A CN109828934A CN 109828934 A CN109828934 A CN 109828934A CN 201811649998 A CN201811649998 A CN 201811649998A CN 109828934 A CN109828934 A CN 109828934A
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Abstract
The present invention discloses a kind of internal storage access device and chip.Device includes: memory device, and any memory device includes at least two storage chips, and storage chip is configured as being read the data of storage；Bridging chip, be configured to supply the first high-speed serial bus interface and respectively at least two memory access interfaces of storage chip unique association；Bridging chip passes through the access request that the first high-speed serial bus interface high-speed serial bus is sent, bridging chip addresses the storage chip of unique association according to access request by memory access interface, and the data for being addressed storage chip storage are read, bridging chip sends the data read to high-speed serial bus by the first high-speed serial bus interface.The present invention is able to solve chip by selecting the scheme of serial line interface to replace parallel interface in the prior art, realizes the communication with external master chip.Reduce chip external interface quantity and chip volume.
Description
Technical field
The present invention relates to computer communication construction field, in particular to a kind of for processor and internal storage access
Device and device.
Background technique
As asic chip is in AI artificial intelligence, large data center, the application in the fields such as cloud computing, device is to be treated
A large amount of data, algorithm complexity is higher and higher, and device is also increasing for the demand of memory size and bandwidth.
For example, memory bandwidth demand is 8Tbps in the dedicated AI chip of Nervana of intel.The Volta frame of NVIDIA
Structure chip Tesla V100, memory bandwidth 7.2Tbps；(1Byte=8bit, 900GB/sec=7.2Tbps).It is Cambrian
Cambricon MLU100-Perf machine learning chip, memory bandwidth 819.2Gbps；(1Byte=8bit, 102.4GB/
Sec=819.2bps).
Said chip is generally docked using more DDR4 chips with master chip to meet higher memory bandwidth demand,
Such as 8 DDR4, reach the parallel bus bandwidth of 256bit；Above scheme uses parallel interface, can effectively improve memory band
It is wide.But it is more using the IO quantity that parallel interface uses, chip interface is more, and chip area is caused inevitably to be extended.
Summary of the invention
The embodiment of the present invention at least discloses a kind of internal storage access device, is able to solve chip and passes through the side of selection serial line interface
Case replaces parallel interface in the prior art, realizes the communication with external master chip.Reduce chip external interface quantity and core
Piece volume.
Described device includes:
Memory device, any memory device include at least two storage chips, the storage chip be configured as by
Read the data of storage；
Bridging chip, be configured to supply the first high-speed serial bus interface and respectively with the storage chip unique association
At least two memory access interfaces；
The bridging chip is asked by the access that the first high-speed serial bus interface high-speed serial bus is sent
It asks, the bridging chip addresses the storage core of unique association according to the access request by the memory access interface
Piece, and the data for being addressed the storage chip storage are read, the bridging chip passes through first high-speed serial bus
Interface sends the data read to high-speed serial bus.
In some embodiments disclosed by the invention, the storage chip is configured as being written into the data of storage；
The bridging chip is write by what high-speed serial bus described in the first high-speed serial bus interface was sent
Enter request and data, the bridging chip requests the institute that unique association is addressed by the memory access interface according to said write
Storage chip is stated, and data are written in the storage chip being addressed.
In some embodiments disclosed by the invention, the bridging chip configures the chip address of the storage chip, with
And the chip address that the bridging chip is read or is written into according to access request or said write request, and
The storage chip is addressed by the chip address.
In some embodiments disclosed by the invention, described device includes at least two memory devices；
Any memory device unique association has the bridging chip；
Any bridging chip is configured to supply the first high-speed serial bus interface and an at least memory access interface；
The visit that any bridging chip is sent by the first high-speed serial bus interface high-speed serial bus
Ask request, the storage chip passes through a memory access interface in the storage of unique association according to the access request
The storage chip is addressed in device, and reads the data for being addressed the storage chip storage, and the bridging chip passes through
The first high-speed serial bus interface sends the data that read to high-speed serial bus；
The bridging chip is write by what high-speed serial bus described in the first high-speed serial bus interface was sent
Enter request and data, described in the bridging chip is requested through the memory access interface in unique association according to said write
The storage chip is addressed in memory device, and data are written in the storage chip being addressed.
In some embodiments disclosed by the invention, described device includes:
The main equipment is configured to supply the second high-speed serial bus interface and the main equipment executes application, and
And operation requests and/or data are sent to the high speed serialization by the second high-speed serial bus interface according to the application
Bus, or data are received from the high-speed serial bus；
The operation requests are access request or write request.
In some embodiments disclosed by the invention, the high-speed serial bus is SERDES.
In some embodiments disclosed by the invention, the storage chip is GDDR6.
In some embodiments disclosed by the invention, the chip is by the memory device and its bridge of unique association
Connect chip package；
The chip is configured as providing first serial communication interface to outside.
In some embodiments disclosed by the invention, the chip is by least two memory devices and its unique association
The bridging chip encapsulation；
The chip is configured as connecing outside offer first serial communication identical with the bridging chip quantity
Mouthful.
For above scheme, the present invention is by being referring to the drawings described in detail disclosed exemplary embodiment, also
The other feature and its advantage for making the embodiment of the present invention understand.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is the view of one chip of embodiment；
Fig. 2 is the view of embodiment two devices；
Fig. 3 is the view of three mainboard of embodiment；
Fig. 4 is the view of example IV device.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.
Therefore, the detailed description of disclosed the embodiment of the present invention in the accompanying drawings is not intended to limit below claimed
The scope of the present invention, but be merely representative of selected embodiment of the invention.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without creative efforts belongs to the model that the present invention protects
It encloses.
Embodiment 1
The present embodiment discloses a kind of internal storage access chip.Chip is by selecting the scheme of serial line interface to replace in the prior art
Parallel interface, realize the communication with external master chip.Reduce chip external interface quantity and chip volume.
Referring to FIG. 1, the chip of the present embodiment includes several GDDR6 particles using CSP encapsulation and is connect by GDDR6
The generic bridge chip that mouth couples respectively with GDDR6 particle；GDDR6 particle is configured as being read or being written into the number of storage
According to.
Generic bridge chip provide one first high-speed serial bus interface and communicated respectively with GDDR6 particle several in
Deposit access interface.Generic bridge chip is used to realize data communication with external high-speed serial bus SERDES, realizes and go here and there at a high speed
Conversion of the row bus to GDDR6 interface.Through the above scheme, one and only one I/O port of the chip of the present embodiment, for
High-speed serial bus SERDES communication, reduces chip volume, reduces cabling difficulty.
In order to preferably explain that chip, the present embodiment show the workflow of chip.
Generic bridge chip is sent by the first high-speed serial bus interface high-speed serial bus SERDES
SERDES data packet.Generic bridge chip obtains access and asks to SERDES resolve packet；Pass through GDDR6 interface and its association again
Access request is sent GDDR6 particle by view.
GDDR6 particle is read the data of storage according to access request；It will be read by GDDR6 interface and its agreement again
Data be sent to generic bridge chip, data are packaged as SERDES data packet and by the first high speeds by generic bridge chip
Serial bus interface is sent to high-speed serial bus SERDES.
Through the above scheme, the internal storage access chip of the present embodiment can be applied in AI artificial intelligence, large data center, cloud
The fields such as calculating.Original parallel bus is replaced using universal serial bus compared with prior art, reduces master chip and the IO of this chip
Port number saves chip area；Meanwhile there is more excellent interference free performance, indirectly reduce master chip Interface design
Difficulty.
Embodiment two
Referring to FIG. 2, the present embodiment discloses a kind of internal storage access device, device includes main equipment and passes through height with main equipment
The internal storage access chip of fast universal serial bus SERDES data communication.
Main equipment at least be configured to supply the second high-speed serial bus interface.
Main equipment at least be configured to execute externally input application, and when reading data according to application,
The SERDES data packet comprising access request is sent to high-speed serial bus SERDES by the second high-speed serial bus interface.It is main
Equipment sends the write-in comprising SERDES data packet when data are written according to application, through the second high-speed serial bus interface
Request and data are to high-speed serial bus SERDES.Internal storage access chip receives SERDES data from high-speed serial bus SERDES
Bao Houru embodiment one executes.
Embodiment three
Referring to FIG. 3, the present embodiment discloses a kind of internal storage access mainboard.The internal storage access device and embodiment of the present embodiment
A kind of the generic bridge chip and several GDDR6 particles of identical function.
The generic bridge chip of the present embodiment selects the scheme of individual packages.The generic bridge chip of so individual packages mentions
For one first high-speed serial bus interface, for realizing data communication with high-speed serial bus SERDES；Basis is designed simultaneously
Coupling GDDR6 particle quantity, several GDDR6 interfaces with GDDR6 particle are provided.Several GDDR6 particles and independent envelope
The generic bridge chip of dress is coupled in pcb board.
Through the above scheme, the present embodiment can at least reduce master chip, the i.e. end IO of external equipment compared with prior art
Mouthful, reduce master chip volume；Meanwhile, it is capable to which flexible connection universal bridging chip and several GDDR6 particles on pcb board, make
The circuit design of pcb board is more flexible.
Example IV
Referring to FIG. 4, the present embodiment discloses a kind of internal storage access device, device include main equipment and with internal storage access master
Plate.Main equipment is mounted on internal storage access mainboard and passes through high speed with the generic bridge chip being connected on internal storage access mainboard
Universal serial bus SERDES data communication.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of internal storage access device, which is characterized in that
Described device includes:
Memory device, any memory device includes at least two storage chips, and the storage chip is configured as being read
The data of storage；
Bridging chip, be configured to supply the first high-speed serial bus interface and respectively with the storage chip unique association extremely
Few two memory access interfaces；
The access request that the bridging chip is sent by the first high-speed serial bus interface high-speed serial bus, institute
The storage chip that bridging chip addresses unique association according to the access request by the memory access interface is stated, and
The data for being addressed the storage chip storage are read, the bridging chip is sent by the first high-speed serial bus interface
The data of reading are to high-speed serial bus.
2. internal storage access device as described in claim 1, which is characterized in that
The storage chip is configured as being written into the data of storage；
The bridging chip is asked by the write-in that high-speed serial bus described in the first high-speed serial bus interface is sent
It asks and data, the bridging chip is requested to address by the memory access interface and be deposited described in unique association according to said write
Chip is stored up, and data are written in the storage chip being addressed.
3. internal storage access device as claimed in claim 2, which is characterized in that
The chip address and the bridging chip that the bridging chip configures the storage chip are according to access request or described
Write request obtains the chip address for being read or being written into, and addresses the storage core by the chip address
Piece.
4. internal storage access device as claimed in claim 2, which is characterized in that
Described device includes at least two memory devices；
Any memory device unique association has the bridging chip；
Any bridging chip is configured to supply the first high-speed serial bus interface and an at least memory access interface；
Any bridging chip is asked by the access that the first high-speed serial bus interface high-speed serial bus is sent
It asks, the storage chip passes through a memory access interface in the memory device of unique association according to the access request
The middle addressing storage chip, and the data for being addressed the storage chip storage are read, the bridging chip passes through described
First high-speed serial bus interface sends the data read to high-speed serial bus；
The bridging chip is asked by the write-in that high-speed serial bus described in the first high-speed serial bus interface is sent
It asks and data, the bridging chip requests the storage by the memory access interface in unique association according to said write
The storage chip is addressed in device, and data are written in the storage chip being addressed.
5. internal storage access device as claimed in claim 2, which is characterized in that
Described device includes:
The main equipment is configured to supply the second high-speed serial bus interface and the main equipment executes application, and root
Operation requests are sent by the second high-speed serial bus interface according to the application and/or data are total to the high speed serialization
Line, or data are received from the high-speed serial bus；
The operation requests are access request or write request.
6. internal storage access device as claimed in claim 2, which is characterized in that
The high-speed serial bus is SERDES.
7. internal storage access device as claimed in claim 2, which is characterized in that
The storage chip is GDDR6.
8. a kind of internal storage access chip as claimed in claim 2, which is characterized in that
The chip is encapsulated by the bridging chip of the memory device and its unique association；
The chip is configured as providing first serial communication interface to outside.
9. a kind of internal storage access chip as claimed in claim 4, which is characterized in that
The chip is encapsulated by the bridging chip of at least two memory devices and its unique association；
The chip is configured as providing first serial communication interface identical with the bridging chip quantity to outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811649998.2A CN109828934A (en) | 2018-12-31 | 2018-12-31 | Internal storage access chip and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811649998.2A CN109828934A (en) | 2018-12-31 | 2018-12-31 | Internal storage access chip and device |
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| CN109828934A true CN109828934A (en) | 2019-05-31 |
Family
ID=66861481
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| CN201811649998.2A Pending CN109828934A (en) | 2018-12-31 | 2018-12-31 | Internal storage access chip and device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6721313B1 (en) * | 2000-08-01 | 2004-04-13 | International Business Machines Corporation | Switch fabric architecture using integrated serdes transceivers |
| CN102609378A (en) * | 2012-01-18 | 2012-07-25 | 中国科学院计算技术研究所 | Message type internal memory accessing device and accessing method thereof |
| CN108536642A (en) * | 2018-06-13 | 2018-09-14 | 北京比特大陆科技有限公司 | Big data operation acceleration system and chip |
-
2018
- 2018-12-31 CN CN201811649998.2A patent/CN109828934A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6721313B1 (en) * | 2000-08-01 | 2004-04-13 | International Business Machines Corporation | Switch fabric architecture using integrated serdes transceivers |
| CN102609378A (en) * | 2012-01-18 | 2012-07-25 | 中国科学院计算技术研究所 | Message type internal memory accessing device and accessing method thereof |
| CN108536642A (en) * | 2018-06-13 | 2018-09-14 | 北京比特大陆科技有限公司 | Big data operation acceleration system and chip |
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