CN109818630A

CN109818630A - A kind of programmable wireless communication development platform

Info

Publication number: CN109818630A
Application number: CN201811634843.1A
Authority: CN
Inventors: 宋体飞
Original assignee: Nanjing Ness Electronics Technology Co Ltd
Current assignee: Nanjing Ness Electronics Technology Co Ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2019-05-28
Anticipated expiration: 2038-12-29
Also published as: CN109818630B

Abstract

The present invention discloses a kind of programmable wireless communication development platform, comprising: network interface, logic level output interface, starting configuration interface and power interface；Further include: DSP module, FPGA module and radio-frequency module.It is communicated to connect between the DSP module and the FPGA module by high speed digital interface；It is communicated to connect between the FPGA module and the radio-frequency module using LVDS.Most multipotency supports the transmitting-receiving of 4 road wireless communication protocols on one piece of hardware platform, substantially increases the flexibility and efficiency of product, substantially increases the efficiency of wireless communication developer.

Description

A kind of programmable wireless communication development platform

Technical field

The invention belongs to communicate the technical field of development platform, developed more particularly to a kind of programmable wireless communication flat Platform.

Background technique

The hardware structure of bottom wireless communication platform is similar for wireless communication system, if therefore can customize one Block processing capacity platform powerful enough supports that various wireless communication agreement is a kind of relatively reason by way of software programming The settling mode thought.And now most of wireless communication development platform is typically only capable to support single one kind wireless in the market Communication protocol, if it is desired to it completely supports certain a kind of wireless protocols (such as mobile communication 2/3/4G), then needs a plurality of hardware platforms, Developer then needs to be familiar with a plurality of hardware platforms simultaneously in this way, this will be related to huge workload, and cannot say that energy is special Note is in the exploitation of communication protocol itself, therefore the Software Radio platform that highly desirable one kind is flexible and efficient.

Summary of the invention

The present invention is to solve technical problem present in above-mentioned background technique, and providing one kind can assist in various wireless communication A kind of programmable wireless communication development platform being switched fast between view.

The present invention is achieved through the following technical solutions: a kind of programmable wireless communication development platform, comprising: network interface, Logic level output interface, starting configuration interface and power interface；Further include:

DSP module is provided with dsp chip, and for the processing of digital signal, the inside of the dsp chip includes that there are four DSP Core, each DSP core can be independently programmed；

FPGA module, including XILINX-FPGA chip, the FPGA module are programmed by verilog；

Radio-frequency module is connect with four road radio frequency interfaces, every road radio frequency interface include transceiver interface respectively all the way；

It is communicated to connect between the DSP module and the FPGA module by high speed digital interface；The FPGA module with it is described It is communicated to connect between radio-frequency module using LVDS.

In a further embodiment, the DSP module is connect with DSP debugging interface, and the DSP debugging interface passes through DSP emulator is connected to computer.

In a further embodiment, the FPGA module is connect with FPGA debugging interface, and the FPGA debugging interface is logical It crosses FPGA emulator and is connected to computer.

In a further embodiment, the FPGA debugging interface is adjacent with DSP debugging interface and set, the FPGA debugging Interface is the high voltage interface of power supply close to one end of DSP debugging interface.

In a further embodiment, the network interface is two, is used to interact with host computer, supports TCP and UDP The format content of the agreement of format, the agreement is customized by user.

In a further embodiment, the logic level output interface is adjacent with the radio frequency interface, the logic electricity Flat output interface includes several pins, wherein for GND pin, other pins are to use to the interface at radio frequency interface Person is customized.

In a further embodiment, it includes six pins that starting configuration interface, which is located at, wherein be three pins with DSP module is connected the Starting mode for controlling DSP module；Remaining three pins are connected with FPGA module, for controlling The Starting mode of FPGA module, six pins are that user is customized.

In a further embodiment, the power interface is connected with power module, and the power module is 12V power supply, Supply current is 3A.

In a further embodiment, the DSP module further includes coprocessor associated with wireless communication.

In a further embodiment, every road radio frequency interface includes radio-frequency channel X and radio-frequency channel Y, be used for and its He connects accessory.

Beneficial effects of the present invention: hardware platform provided by the invention is strong with data-handling capacity, data throughout is big, The advantages that small in size, can easily switch between various wireless communication standard, and the most multipotency on one piece of hardware platform The transmitting-receiving for supporting 4 road wireless communication protocols substantially increases the flexibility and efficiency of product, substantially increases wireless communication and open The efficiency of hair personnel.

Detailed description of the invention

Fig. 1 is structural framing figure of the invention.

Fig. 2 is that hardware PCB of the invention schemes.

Each mark of the Fig. 1 into Fig. 2 are as follows: dsp chip 1, XILINX-FPGA chip 2, radio-frequency module 3, radio frequency interface 4, FPGA debugging interface 5, DSP debugging interface 6, network interface 7, starting configuration interface 8, power interface 9, radio-frequency channel X10, radio-frequency channel Y11。

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that, term " on ", "lower", "front", "rear", "left", "right", "top", The orientation or positional relationship of the instructions such as "bottom", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, merely to just In description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with Specific orientation construction and operation, therefore be not considered as limiting the invention.

As shown in Figure 1, a kind of programmable wireless communication development platform, comprising: network interface 7, opens logic level output interface Dynamic configuration interface 8 and power interface 9；Further include: DSP module, FPGA module and radio-frequency module 3.The DSP module with it is described It is communicated to connect between FPGA module by high speed digital interface；LVDS is used between the FPGA module and the radio-frequency module 3 Communication connection.

As shown in Fig. 2, DSP module, is provided with DSPDSP chip 1, for the processing of digital signal, the dsp chip 1 Inside includes there are four DSP core, and each DSP core can be independently programmed；It include multiple associations relevant to wireless communication inside DSP Processor, user can need to write wireless communication relative program according to oneself, which can pass through network interface 7 and host computer It interacts, can also be interacted by high speed digital interface SRIO and FPGA.

The DSP module is connect with FPGA debugging interface 5, and the FPGA debugging interface 5 is connected to electricity by DSP emulator Brain.User can be by the program of the interface on-line debugging DSP internal composition or by the starting of startup program programming to DSP In FLASH.

FPGA module, including XILINX-FPGA chip 2, the FPGA module are programmed by verilog；Specifically Function is defined by user oneself, and external interface includes the SRIO interface between DSP, i.e. high speed digital interface, and with penetrate LVDS interface between frequency.

The FPGA module is connect with FPGA debugging interface 5, and the FPGA debugging interface 5 is connected to by FPGA emulator Computer.User can by interface download online FPGA program, check inside FPGA time sequence status or burn startup program It writes in the starting FLASH of FPGA.

Signal transmission for the multiple modules being connect with FPGA, by the way of flow control between adjustment module.It is first First, the handling capacity of each module input and output, the data stream size of control predetermined module input are analyzed, i.e. opening data flow makes a reservation for Time cycle is then shut off the tentation data stream predetermined time, forms compartment flow and adjusts, to ensure the output data of the module Phenomena such as stream can normally be input to next module, overflow without data.In this fashion, module output end without Control signal must be gone by handshake, input terminal is controlled using " switch " of active, that is, can guarantee the data flow of output end Normal communication.

The FPGA debugging interface 5 is adjacent with FPGA debugging interface 5 and sets, and the FPGA debugging interface 5 is close to FPGA tune Try mouth 5 one end be power supply high voltage interface.

Radio-frequency module 3 is connect with four road radio frequency interfaces 4, every road radio frequency interface 4 include transceiver interface respectively all the way；Every road is penetrated Frequency interface 4 includes radio-frequency channel X10 and radio-frequency channel Y11 for connecting with other accessories, such as power amplifier.

The network interface 7 is two, is used to interact with host computer, supports the agreement of TCP and UDP format, the association The format content of view is customized by user.

The logic level output interface is adjacent with the radio frequency interface 4, and the logic level output interface includes several A pin can usually make wherein for GND pin, other pins are that user is customized to the interface at radio frequency interface 4 Output low and high level is generated with the interface come come the transmitting-receiving that controls power amplifier.

It includes six pins that the starting configuration interface 8, which is located at, wherein being that three pins are connected with DSP module for controlling The Starting mode of DSP module processed；Remaining three pins are connected with FPGA module, for controlling the Starting mode of FPGA module, Six pins are that user is customized.As DSP can be configured to start journey from 7 startup program of network interface or from FLASH Sequence.

The power interface 9 is connected with power module, is powered using 12V, and supply current selects fitting for 3A or more as far as possible Orchestration, present invention power consumption when operating at full capacity can reach 30W or so.

User can be by writing the program of different DSP and FPGA for different wireless communication protocols, and configures DSP Starting mode is DSP from the starting of network interface 7 and FPGA Starting mode is DSP load FPGA.The communication protocols of work will be needed when use Agenda sequence is placed in host computer, and plank internal work can be automatically loaded by powering on rear program, while being worked as and being needed to be switched to other nothings When line standard, new program is put into host computer and is re-powered.Simultaneously in order to support multiple types concurrent efforts, Various communications protocols can be integrated into a program by user when writing program.

For those of ordinary skill in the art, it is possible to understand that without departing from the principles and spirit of the present invention A variety of change, modification, replacement and modification can be carried out to these embodiments, the scope of the present invention is by appended claims and its waits Jljl limits.

Claims

1. a kind of programmable wireless communication development platform, comprising: network interface, logic level output interface, starting configuration interface and Power interface；It is characterized by further comprising:

2. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that the DSP module It is connect with DSP debugging interface, the DSP debugging interface is connected to computer by DSP emulator.

3. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that the FPGA module It is connect with FPGA debugging interface, the FPGA debugging interface is connected to computer by FPGA emulator.

4. a kind of programmable wireless communication development platform according to claim 3, which is characterized in that the FPGA debugging Interface is adjacent with DSP debugging interface and sets, and the FPGA debugging interface is the high voltage of power supply close to one end of DSP debugging interface Interface.

5. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that the network interface is two It is a, be used to interact with host computer, support the agreement of TCP and UDP format, the format content of the agreement by user from Definition.

6. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that the logic level Output interface is adjacent with the radio frequency interface, and the logic level output interface includes several pins, wherein connecing close to radio frequency For GND pin, other pins are that user is customized to interface at mouthful.

7. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that the starting configuration It includes six pins that interface, which is located at, wherein being the Starting mode that three pins are connected for controlling DSP module with DSP module； Remaining three pins are connected with FPGA module, and for controlling the Starting mode of FPGA module, six pins are to use Person is customized.

8. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that the power interface It is connected with power module, the power module is 12V power supply, supply current 3A.

9. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that the DSP module It further include coprocessor associated with wireless communication.

10. a kind of programmable wireless communication development platform according to claim 1, which is characterized in that every road is penetrated Frequency interface includes radio-frequency channel X and radio-frequency channel Y, for connecting with other accessories.