CN109818609A - A kind of multi-modulus frequency divider based on GaAs HBT technique - Google Patents
A kind of multi-modulus frequency divider based on GaAs HBT technique Download PDFInfo
- Publication number
- CN109818609A CN109818609A CN201811564888.6A CN201811564888A CN109818609A CN 109818609 A CN109818609 A CN 109818609A CN 201811564888 A CN201811564888 A CN 201811564888A CN 109818609 A CN109818609 A CN 109818609A
- Authority
- CN
- China
- Prior art keywords
- unit
- bimodulus
- frequency divider
- output signal
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a kind of multi-modulus frequency dividers based on GaAs HBT technique, including n grades of cascade bimodulus ÷ Unit 2/3, every level-one is all identical, and the clock output signal of prime is as secondary clock input signal, mode control input signal of the secondary mode output signal as prime；The clock input signal of the first order connects outside from external input, the mode output signal of the first order；N-th grade of mode control input signal connects outside from external input, n-th grade of clock output signal.The present invention uses GaAs HBT technological design, bimodulus ÷ Unit 2/3 include four triggers and three or, transmission delay can be reduced and promote the operating rate of frequency divider；The structure of master-slave flip-flop is powered using single supply, can greatly reduce the power consumption of frequency divider, while can be reduced the area of chip and be increased the stability of output signal；The present invention can be used for well in frequency agility and fractional frequency division source under GaAs HBT technique.
Description
Technical field
The present invention relates to multi-modulus frequency divider, a kind of be specifically related under the HBT technique based on GaAs multi-modulus frequency divider.
Background technique
A key modules of the frequency source as wireless communication RF the front end, " heart being called in entire communication system
It is dirty ", largely restrict the development of the entire communication technology.And important component of the frequency divider as frequency source, it is frequency source
Middle work limits the working frequency and power consumption of entire frequency source in one of the module of highest frequency.
The power consumption of multi-modulus frequency divider, rate, division range are very important index, and researcher wishes guaranteeing frequency divider
Under the premise of realizing normal division function, reduces the power consumption of frequency divider as far as possible and promote its operating rate.Existing literature and skill
In art, realize that programmable multi-modulus frequency divider is all based on Si/SiGe technique mostly, and with GaAs HBT (GaAs hetero-junctions
Bipolar junction transistor) technique realize multi-modulus frequency divider it is actually rare, this make such frequency divider research become frequency microwave, milli
A research emphasis and difficult point for metric wave Circuits and Systems.GaAs technique is with processing cost is low, anti-radiation performance is good and makes an uproar
The advantages that sound is small, but due to its disadvantage in terms of power consumption, operating rate and design flexibility, so that using this kind of technique
Design multi-modulus frequency divider needs to face more challenges.Programmable frequency divider is usually cascaded by multistage dual-modulus prescaler real
It is existing.Therefore, the design of the dual-modulus prescaler of low-power consumption is the key that entire multi-modulus frequency divider.
In the prior art, the realization of frequency divider is mainly the following mode.Researcher Wang, S.Y are double by reducing
The operating current of latch in mould pre-divider greatly reduces the power consumption of entire frequency divider.Referring to document Wang,
S.Y.,Wu, X.L.,Wu,J.H.,and Zhang,M,“Low power design of multi-modulus
programmable frequency divider,"Electronic Letters,vol.45,pp.1017-1019,2009。
Researcher Ray, M. realize a multi-modulus frequency divider, the frequency divider by 5 cascade forms of dual-mode frequency divider
The frequency dividing that the stepping that achievable frequency dividing ratio is 128-159 is 1.Referring to document Ray, M., Souder, W., Ratcliff, M.,
Dai,F.,and Irwin,J.D.:‘A 13GHz Low Power Multi-Modulus Divider Implemented in
0.13μm SiGe Technology’,IEEE Topical Meeting on Silicon Monolithic Integrated
Circuits in RF Systems,2009, pp.1-4。
The form of researcher Tseng, S.C based on sampling hold circuit realizes the frequency divider that duty ratio is 50%.Ginseng
See document Tseng, S.C., Meng, C.C., and Chen, W.Y, " SSH and SHH GaInP/GaAs HBT divide-
By-3 prescalers with true 50%duty cycle, " Electronic Letters, vol.42, pp.796-
797,2006。
Although multimode frequency dividing may be implemented in the first frequency divider, while power consumption is significantly improved, but due to text
The method mentioned in offering needs to use Si base CMOS differential pair tube, therefore cannot be used in conventional GaAs technique.Second point
Frequency device be although realized based on GaAs HBT technique, but its frequency dividing ratio be it is fixed immutable, still cannot be used for agile
In frequency and fractional frequency division frequency synthesizer.The third frequency divider is using SiGe technique, and its dual-modulus prescaler
The structure for being trigger and realizing with door, this kind of structure will increase transmission delay, and reduce its operating rate.In addition, above three
Basic logic unit in kind method is all based on single latch, this just inevitably will increase the unstability of output signal.
Therefore these three methods have the limitation of itself.
Summary of the invention
In view of the above technical defects, in order to not only be able to achieve variable frequency dividing ratio, but also there is lower power consumption, the present invention proposes
A kind of multi-modulus frequency divider based on GaAs HBT technique, the multi-modulus frequency divider have the characteristics that high-speed and low-power consumption, can
In the frequency agility and fractional frequency division frequency source that perform well under GaAs HBT technique.
Technical scheme is as follows:
A kind of multi-modulus frequency divider based on GaAs HBT technique, it is characterised in that: n is included using the production of GaAs HBT technique
The cascade bimodulus ÷ Unit 2/3 of grade, every level-one bimodulus ÷ Unit 2/3 is all identical, the clock output of previous stage bimodulus ÷ Unit 2/3
Clock input signal of the signal as secondary bimodulus ÷ Unit 2/3, before the mode output signal of secondary bimodulus ÷ Unit 2/3 is used as
The mode control input signal of level-one bimodulus ÷ Unit 2/3；The clock input signal of first order bimodulus ÷ Unit 2/3 is single from outside
Member input, the mode output signal of first order bimodulus ÷ Unit 2/3 connect external unit；The mode control of n-th grade of bimodulus ÷ Unit 2/3
Input signal processed is inputted from external unit, and the clock output signal of n-th grade of bimodulus ÷ Unit 2/3 connects external unit；Wherein, n >=
1。
For every grade of bimodulus ÷ Unit 2/3:
(1) scheme control input Mod_in is high level, and it is low level that frequency dividing control, which inputs PB,；Alternatively, working as scheme control
Input Mod_in is high level, and it is high level that frequency dividing control, which inputs PB,；Alternatively, when scheme control input Mod_in is low level,
When frequency dividing control input PB is high level: bimodulus ÷ Unit 2/3 can be reduced to the cascade of two triggers, realize remove at this time
2 frequency dividings；
(2) when scheme control inputs Mood_in and frequency dividing control input PB is low level, the bimodulus ÷ 2/3 is single
Member can be reduced to one, four triggers or cascade, at this time realize except 3 frequency dividing.
Therefore the frequency dividing ratio realized for the entire multi-modulus frequency divider can be indicated by following formula:
Wherein: ToutIndicate the period of output signal, TinIndicate the period of input signal, PB0、PB1、……PBn-1Respectively
Indicate the frequency dividing control input of frequency divider, n is total series of ÷ Unit 2/3.
Bimodulus ÷ Unit 2/3 is using emitter-coupled logic (Emitter-coupled Logic, abridge ECL)
Structure realizes, structure include four triggers and three or.In order to reduce the transmission delay of signal, it can incite somebody to action or door is embedded into
In trigger.
The structure of bimodulus ÷ Unit 2/3 uses the structure of master flip-flop and slave flipflop, to promote the steady of output
It is qualitative.The sample circuit part and holding circuit part of traditional structure master-slave flip-flop use different input clock signal controls
System needs 14 transistors in total, wherein at least includes 2 large-size crystals pipes as tail current source.What the present invention designed
Master-slave flip-flop, sample circuit part and holding circuit part are controlled using the same clock signal.
The master flip-flop and slave flipflop of bimodulus ÷ Unit 2/3 can be powered using single supply, not only can be substantially
Reduce the power consumption of entire frequency divider, while can effectively reduce the area of entire chip.
The present invention is using GaAs HBT technological design and realizes, wherein being improved bimodulus ÷ Unit 2/3, using four
A trigger and three are constituted, and this structure is conducive to reduce transmission delay and the operating rate that promotes frequency divider；It is this
Bimodulus ÷ Unit 2/3 can be realized single supply power supply, can not only greatly reduce frequency dividing in this way using master-slave flip-flop
The power consumption of device, while can reduce the area of chip and increasing the stability of output signal.Finally, being based on to bimodulus ÷ 2/
The change of Unit 3 and trigger structure is provided simultaneously with so that the power consumption and operating rate of the multi-modulus frequency divider are all improved
Smaller area；The multi-modulus frequency divider can be good at in the frequency agility and fractional frequency division source under GaAs HBT technique.
Detailed description of the invention
Fig. 1 is topological structure schematic diagram of the invention.
Fig. 2 is traditional 2/3 cellular construction schematic diagram of ÷.
Fig. 3 is 2/3 cellular construction schematic diagram of ÷ used in the present invention.
Fig. 4 is simplification electrical block diagram when ÷ Unit 2/3 in the present invention realizes just 2 frequency dividing.
Fig. 5 is simplification electrical block diagram when ÷ Unit 2/3 in the present invention realizes just 3 frequency dividing.
Fig. 6 is the structural schematic diagram of traditional master-slave flip-flop.
Fig. 7 is the structural schematic diagram of master-slave flip-flop of the invention.
Fig. 8 is that when the invention works, input frequency is 6GHz, realizes the simulation result schematic diagram of 256 frequency dividings.
Fig. 9 is that when the invention works, input frequency is 7GHz, realizes the simulation result schematic diagram of 511 frequency dividings.
Specific embodiment
A kind of multi-modulus frequency divider based on GaAs HBT technique, including n grades of cascade bimodulus ÷ Unit 2/3, every level-one are double
Mould ÷ Unit 2/3 is all identical, the clock output signal of previous stage bimodulus ÷ Unit 2/3 as secondary bimodulus ÷ Unit 2/3 when
The mode output signal of clock input signal, secondary bimodulus ÷ Unit 2/3 is defeated as the scheme control of previous stage bimodulus ÷ Unit 2/3
Enter signal；The clock input signal of first order bimodulus ÷ Unit 2/3 is inputted from external unit, first order bimodulus ÷ Unit 2/3
Mode output signal connects external unit；The mode control input signal of n-th grade of bimodulus ÷ Unit 2/3 is inputted from external unit, and n-th
The clock output signal of grade bimodulus ÷ Unit 2/3 connects external unit.As shown in Figure 1, the multi-modulus frequency divider specifically designed, n=8,
Including eight grades of cascade bimodulus ÷ Unit 2/3.
As shown in figure 3, there are four by Heterojunction Bipolar Transistors for design for bimodulus ÷ Unit 2/3 in the present invention
The trigger Q1-Q4 of composition, specific control model are as follows:
(1) scheme control input Mod_in is high level, and it is low level that frequency dividing control, which inputs PB,；Alternatively, working as scheme control
Input Mod_in is high level, and it is high level that frequency dividing control, which inputs PB,；Alternatively, when scheme control input Mod_in is low level,
When frequency dividing control input PB is high level: bimodulus ÷ Unit 2/3 can be reduced to the cascade of two triggers, realize remove at this time
2 frequency dividings, as shown in Figure 4；
(2) when scheme control inputs Mood_in and frequency dividing control input PB is low level, the bimodulus ÷ 2/3 is single
Member can be reduced to one, four triggers or cascade, at this time realize except 3 frequency dividing, as shown in Figure 5.
Therefore the frequency dividing ratio realized for the entire multi-modulus frequency divider can be indicated by following formula:
Wherein: ToutIndicate the period of output signal, TinIndicate the period of input signal, PB0、PB1、……PBn-1Respectively
Indicate the frequency dividing control input of frequency divider, n is total series of ÷ Unit 2/3.
As shown in Figure 2,6, it is traditional using single latch and with bimodulus ÷ Unit 2/3 for being constituted by the way of door, can increase
Add transmission delay, to increase the power consumption of frequency divider, and it is possible to lead to the unstable of output.
As shown in fig. 7, bimodulus ÷ Unit 2/3 is using emitter-coupled logic (Emitter-coupled
Logic, abridge ECL) structure realizes, structure include four triggers and three or.Prolong to reduce the transmission of signal
When, it can incite somebody to action or door is embedded into trigger.The structure of bimodulus ÷ Unit 2/3 uses the knot of master flip-flop and slave flipflop
Structure, to promote the stability of output.The sample circuit part of traditional structure master-slave flip-flop and holding circuit part be not using
Same input clock signal control needs 14 transistors in total, wherein at least includes that 2 large scales as tail current source are brilliant
Body pipe.The master-slave flip-flop that the present invention designs, sample circuit part and holding circuit part use the same clock signal
Control.
The master flip-flop and slave flipflop of bimodulus ÷ Unit 2/3 can be powered using single supply, not only can be substantially
Reduce the power consumption of entire frequency divider, while can effectively reduce the area of entire chip.Show such as Fig. 8-9 from simulation result
Shown, multi-modulus frequency divider of the invention can be to realize that division range reaches in 50MHz-7GHz frequency range in input frequency
The frequency dividing for being 1 with stepping of 256-511；For the frequency divider using 5V as supply voltage, total current is lower than 175mA.
The area design of the entire frequency divider chip is 4800um × 852um.
Claims (7)
1. a kind of multi-modulus frequency divider based on GaAs HBT technique, it is characterised in that: including n grades of cascade bimodulus ÷ Unit 2/3,
Every level-one bimodulus ÷ Unit 2/3 is all identical, and the clock output signal of previous stage bimodulus ÷ Unit 2/3 is as secondary bimodulus ÷ 2/3
The clock input signal of unit, mould of the mode output signal of secondary bimodulus ÷ Unit 2/3 as previous stage bimodulus ÷ Unit 2/3
Formula controls input signal；The clock input signal of first order bimodulus ÷ Unit 2/3 is inputted from external unit, first order bimodulus ÷ 2/
The mode output signal of Unit 3 connects external unit；The mode control input signal of n-th grade of bimodulus ÷ Unit 2/3 is from external unit
Input, the clock output signal of n-th grade of bimodulus ÷ Unit 2/3 connect external unit；Wherein, n >=1.
2. the multi-modulus frequency divider according to claim 1 based on GaAs HBT technique, which is characterized in that for every grade of bimodulus
÷ Unit 2/3: when scheme control input Mod_in is high level, it is low level that frequency dividing control, which inputs PB,；Alternatively, working as scheme control
Input Mod_in is high level, and it is high level that frequency dividing control, which inputs PB,；Alternatively, when scheme control input Mod_in is low level,
When frequency dividing control input PB is high level: bimodulus ÷ Unit 2/3 is reduced to the cascade of two triggers, realizes remove 2 at this time
Frequency dividing.
3. the multi-modulus frequency divider according to claim 1 based on GaAs HBT technique, which is characterized in that for every grade of bimodulus
÷ Unit 2/3: when scheme control inputs Mood_in and frequency dividing control input PB is low level, bimodulus ÷ Unit 2/3
Be reduced to one, four triggers or cascade, at this time realize except 3 frequency dividing.
4. the multi-modulus frequency divider based on GaAs HBT technique according to claim 1 to 3, it is characterised in that: right
It is indicated in the frequency dividing ratio that the entire multi-modulus frequency divider is realized by following formula:
Wherein: ToutIndicate the period of output signal, TinIndicate the period of input signal, PB0、PB1、……PBn-1It respectively indicates point
The frequency dividing control of frequency device inputs, and n is total series of ÷ Unit 2/3.
5. the multi-modulus frequency divider according to claim 1 or 2 based on GaAs HBT technique, which is characterized in that the bimodulus
÷ Unit 2/3 using emitter-coupled logic structure, including four triggers and three or.
6. the multi-modulus frequency divider according to claim 5 based on GaAs HBT technique, which is characterized in that the bimodulus ÷ 2/
Unit 3 use the structure of master flip-flop and slave flipflop, when sample circuit part and holding circuit part use same
The control of clock signal.
7. the multi-modulus frequency divider according to claim 6 based on GaAs HBT technique, which is characterized in that the bimodulus ÷ 2/
The master flip-flop and slave flipflop of Unit 3 are powered using single supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811564888.6A CN109818609A (en) | 2018-12-20 | 2018-12-20 | A kind of multi-modulus frequency divider based on GaAs HBT technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811564888.6A CN109818609A (en) | 2018-12-20 | 2018-12-20 | A kind of multi-modulus frequency divider based on GaAs HBT technique |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109818609A true CN109818609A (en) | 2019-05-28 |
Family
ID=66601710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811564888.6A Pending CN109818609A (en) | 2018-12-20 | 2018-12-20 | A kind of multi-modulus frequency divider based on GaAs HBT technique |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109818609A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003019781A2 (en) * | 2001-08-29 | 2003-03-06 | Koninklijke Philips Electronics N.V. | Improved frequency divider with reduced jitter and transmitter based thereon |
| CN101355361A (en) * | 2008-09-24 | 2009-01-28 | 东南大学 | High-speed wide-region multi-mode programmable frequency divider capable of adjusting dutyfactor |
| CN101399540A (en) * | 2008-10-10 | 2009-04-01 | 东南大学 | High speed wide range multi-mode programmable frequency divider with 50 26676056uty ratio |
| CN101789786A (en) * | 2009-01-22 | 2010-07-28 | 中国科学院半导体研究所 | Full-difference bimodule prescalar with low power consumption |
| CN101908883A (en) * | 2009-06-03 | 2010-12-08 | 中国科学院微电子研究所 | Programmable decimal frequency divider |
| CN102356369A (en) * | 2009-03-19 | 2012-02-15 | 高通股份有限公司 | Frequency divider with synchronized outputs |
| CN102739239A (en) * | 2012-06-15 | 2012-10-17 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
| CN103297037A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Multi-mode frequency divider based on modularization |
-
2018
- 2018-12-20 CN CN201811564888.6A patent/CN109818609A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003019781A2 (en) * | 2001-08-29 | 2003-03-06 | Koninklijke Philips Electronics N.V. | Improved frequency divider with reduced jitter and transmitter based thereon |
| CN101355361A (en) * | 2008-09-24 | 2009-01-28 | 东南大学 | High-speed wide-region multi-mode programmable frequency divider capable of adjusting dutyfactor |
| CN101399540A (en) * | 2008-10-10 | 2009-04-01 | 东南大学 | High speed wide range multi-mode programmable frequency divider with 50 26676056uty ratio |
| CN101789786A (en) * | 2009-01-22 | 2010-07-28 | 中国科学院半导体研究所 | Full-difference bimodule prescalar with low power consumption |
| CN102356369A (en) * | 2009-03-19 | 2012-02-15 | 高通股份有限公司 | Frequency divider with synchronized outputs |
| CN101908883A (en) * | 2009-06-03 | 2010-12-08 | 中国科学院微电子研究所 | Programmable decimal frequency divider |
| CN102739239A (en) * | 2012-06-15 | 2012-10-17 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
| CN103297037A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Multi-mode frequency divider based on modularization |
Non-Patent Citations (2)
| Title |
|---|
| 于云丰等: "基于新型双模分频器的低功耗多模分频器", 《微电子学》, no. 02, 20 April 2010 (2010-04-20) * |
| 王培章等: "《现代微波与天线测量技术》", 东南大学出版社, pages: 41 - 44 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI429188B (en) | Dual-modulus prescaler circuit operating at a very high frequency | |
| Lin et al. | A 5.5-GHz 1-mW full-modulus-range programmable frequency divider in 90-nm CMOS process | |
| Alioto et al. | Design of high-speed power-efficient MOS current-mode logic frequency dividers | |
| CN102474258B (en) | There is the frequency divider of configurable dividing ratio | |
| CN107306133A (en) | A kind of frequency divider and frequency synthesizer | |
| CN102497201A (en) | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption | |
| CN101931396B (en) | Prescaler with clock-controlled transistor | |
| CN109818609A (en) | A kind of multi-modulus frequency divider based on GaAs HBT technique | |
| Balaji et al. | Low power and high speed synchronous circuits using transmission gates | |
| CN104113325B (en) | A kind of multi-mode programmable frequency divider | |
| Balaji et al. | Rapid low power Synchronous circuits using transmission gates | |
| Guo et al. | Design and optimization of dual modulus prescaler using the extended true-single-phase-clock | |
| Jia et al. | A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic | |
| Bhattacharjee et al. | A 23.52 µW/0.7 V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock | |
| CN208299782U (en) | A kind of four/five pre-divider of high-speed low-power-consumption | |
| Ali et al. | A multigigahertz multimodulus frequency divider in 90-nm CMOS | |
| Wang et al. | Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | |
| Jia et al. | A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic | |
| CN111711447A (en) | Prescaler and frequency divider | |
| JP2004228812A (en) | Frequency divider | |
| Do et al. | A 2GHz programmable counter with new re-loadable D flip-flop | |
| Nagarajan et al. | Efficient timing element design featuring low power vlsi application | |
| Nehru et al. | Analysis of 16-bit counter using GDI technique and CMOS logic | |
| US6696857B1 (en) | High speed CMOS dual modulus prescaler using pull down transistor | |
| Sharma et al. | A 7.69 GHz High Speed Dual Modulus Prescaler: Using True Single Phase Clock |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |