CN109815749B

CN109815749B - System, method and chip for controlling SE

Info

Publication number: CN109815749B
Application number: CN201711164962.0A
Authority: CN
Inventors: 陈迎国; 潘时林
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-11-21
Filing date: 2017-11-21
Publication date: 2021-01-15
Anticipated expiration: 2037-11-21
Also published as: CN109815749A; WO2019100693A1

Abstract

A system, method and chip for controlling SE. The system comprises an SE, a processor, a power-on component, a PMU and a communication unit; the SE, the processor and the power-on assembly are positioned in the first semiconductor chip; the communication unit is used for receiving a communication signal meeting a preset condition and outputting a first power-on signal to the power-on assembly according to the communication signal; the power-on component is used for triggering the processor to be powered on; the processor is used for acquiring the SE power-on indication information from the power-on assembly and controlling the SE power-on according to the SE power-on indication information; the SE is used for interacting the safety communication data with the communication unit and carrying out safety processing on the safety communication data; and the PMU is used for supplying power to the processor, the SE, the power-on component and the communication unit. According to the scheme provided by the embodiment of the application, aiming at the scheme of the built-in SE, the SE power-on can be still triggered to perform the safety processing after the processor is powered off, and the use of the safety function is not influenced on the premise of saving the power consumption as much as possible.

Description

System, method and chip for controlling SE

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to a system, a method and a chip for controlling a Secure Element (SE).

Background

With the continuous development of mobile terminals, mobile terminals have more and more functions, and people pay more and more attention to data security in the mobile terminals. Generally, data security in a mobile terminal is protected by an SE. The SE is independent of a main processor in the system and is provided with an encryption logic circuit and a decryption logic circuit, wherein the encryption logic circuit and the decryption logic circuit internally comprise a processor special for security processing and various hardware circuits, and the encryption logic circuit is used for encrypting and decrypting data interacted between devices in a data interaction process so as to improve the security of the data. Generally, SE can be used to implement various types of security processing including mobile payment, public transit card swiping, or door card swiping.

Currently, in a mobile terminal, a scheme of embedding a SE in an Application Processor (AP) chip is adopted. The scheme of built-in SE means that the SE is integrated on an AP chip of the mobile terminal, that is, the SE is a part of the AP chip. For the built-in SE scheme, whether the SE starts depends on whether a Power Management Unit (PMU) of the mobile terminal supplies Power to the AP chip. When the mobile terminal is in a power-on state, the PMU supplies power to the AP chip, the AP chip is in a power-on state, and the SE is also in a power-on state; when the mobile terminal is in a power-off state, the PMU stops supplying power to the AP chip, the AP chip is in a power-off state, and the SE is also in the power-off state.

According to the scheme of the built-in SE, when the mobile terminal is in a power-off state, the SE integrated on the AP chip is in a power-off state, so that the safety processing of interactive data cannot be performed, and the safety of the data is reduced.

Disclosure of Invention

The embodiment of the application provides a system, a method and a chip for controlling SE, aiming at the scheme of built-in SE, when a processor in the system is in a power-off state, the SE is utilized for carrying out safety processing.

In a first aspect, an embodiment of the present application provides a system for controlling an SE, including an SE, a processor, a power-on component, a power management unit PMU, and a communication unit. The SE, the processor and the power-on component are located in the first semiconductor chip. Optionally, at least one of the PMU and communication unit is located within the first semiconductor chip. Optionally, the PMU and the communication unit are located in the same or a different semiconductor chip than the first semiconductor chip.

The communication unit is used for receiving a communication signal meeting a preset condition and outputting a first power-on signal to the power-on assembly according to the communication signal. And the power-on component is used for acquiring a first power-on signal from the communication unit and triggering the processor to be powered on. And the processor is used for switching from the first power-down state to the first power-on state under the trigger of the power-on assembly, acquiring SE power-on indication information from the power-on assembly and controlling SE power-on according to the SE power-on indication information. And the SE is used for switching from the second power-off state to the second power-on state under the control of the processor, interacting the safety communication data with the communication unit and carrying out safety processing on the safety communication data. And the PMU is used for supplying power to the processor, the SE, the power-on component and the communication unit.

In the scheme provided by the embodiment of the application, for the scheme with the built-in SE, the communication unit outputs a first power-on signal to the upper electric module when detecting the communication signal meeting the preset condition, so that the processor is triggered to be powered on, the SE integrated with the processor on the same chip is powered on and started, the communication unit interacts with the secure communication data and performs secure processing on the secure communication data, the SE is still triggered to be powered on to perform the secure processing after the processor is powered off, and the use of the secure function is not influenced on the premise of saving the power consumption as much as possible.

In one possible embodiment, the power-up component is specifically configured to output a second power-up signal to the PMU in an aspect where the power-up component is configured to trigger power-up of the processor. And the PMU is used for acquiring a second power-on signal from the power-on component and supplying power to the processor according to the second power-on signal.

Through the mode, the power-on component can trigger the processor to be powered on through the PMU.

In yet another possible design, the processor is specifically configured to send a third power-up signal to the PMU in an aspect where the processor is configured to control the power-up of the SE. And the PMU is used for receiving a third power-on signal from the processor and supplying power to the SE according to the third power-on signal.

Through the method, the processor can control the SE to be powered on.

In yet another possible design, the PMU is further configured to send a first shutdown signal to the processor when the battery level is detected to be less than a first preset threshold. The processor is further configured to receive a first shutdown signal from the PMU, and execute a first shutdown operation according to the first shutdown signal, where the first shutdown operation includes: the control processor and SE are powered down.

In the embodiment of the invention, the processor and the SE are controlled to be powered off through the first shutdown operation, so that the mobile terminal triggers the SE to be powered on through the non-powered-off power-on component to perform safety processing.

In yet another possible design, the PMU is further configured to output a fourth power-on signal to the power-on component when it is detected that the battery level is less than a second preset threshold, where the second preset threshold is less than the first preset threshold. And the power-on component is also used for acquiring a fourth power-on signal from the PMU and triggering the processor to be powered on. The processor is further configured to switch from a first power-down state to a first power-on state under the trigger of the power-on component, acquire power-off indication information from the power-on component, and execute a second power-off operation according to the power-off indication information, where the second power-off operation includes: and controlling the processor, the SE and the power-on component to be powered down.

In this embodiment of the application, the PMU is used for detecting the battery power, and when the battery power is lower than a second preset threshold, the PMU outputs a fourth power-on signal to the power-on component, so that the power-on component triggers the processor to be powered on, and the processor executes a second shutdown operation to enable the mobile terminal to enter a normal shutdown state. Through the mode, the mobile terminal is prevented from consuming electric quantity in the first power-off state, so that a part of electric quantity is reserved for subsequent use (such as dialing an emergency call, starting a power-off alarm clock and the like).

In yet another possible design, the power-on assembly is further configured to: starting a timer after the processor performs a first shutdown operation; when the timer times out, the processor is triggered to be powered on. The processor is further configured to switch from a first power-down state to a first power-on state under the trigger of the power-on component, acquire power-off indication information from the power-on component, and execute a second power-off operation according to the power-off indication information, where the second power-off operation includes: and controlling the processor, the SE and the power-on component to be powered down.

In the embodiment of the application, the timer is used for timing, after the duration set by the timer, the power-on assembly controls the processor to be powered on, and the processor executes the second power-off operation to enable the mobile terminal to enter the normal power-off state. Through the mode, the time length for the mobile terminal to enter the first power-off state can be set according to user requirements, and the situation that the mobile terminal consumes the electric quantity in the first power-off state due to the fact that the mobile terminal keeps the first power-off state for too long time is avoided, so that a part of electric quantity is reserved for follow-up use (such as dialing of an emergency call, starting of a power-off alarm clock and the like).

In yet another possible design, the preset condition is that the communication signal includes a preset identifier, or the preset condition is that a frequency band of the communication signal is within a preset frequency band.

Through the mode, the communication unit can accurately identify the communication signal related to the card swiping function provided by the communication unit.

In yet another possible design, the processor is further configured to load an execution program of the SE from a memory external to the first semiconductor chip into a memory internal to the first semiconductor chip after acquiring the SE power-on instruction information from the power-on component. And the SE is also used for loading the execution program from the memory inside the first semiconductor chip into the memory inside the SE after switching from the second power-off state to the second power-on state under the control of the processor, and running the execution program to realize the functions of interacting the secure communication data with the communication unit and performing secure processing on the secure communication data.

By the above manner, the execution program of the SE is stored in the memory outside the first semiconductor chip, so that the storage space of the SE can be saved, and the SE can be designed to be thinner and lighter.

In yet another possible design, the processor is further configured to perform a third shutdown operation after a preset duration after the SE is powered on; or starting a timing clock after the SE is powered on, resetting the timing clock when receiving a reset command sent by the SE, wherein the SE sends the reset command to the processor every time the SE receives a signal from the communication unit, and executing a third shutdown operation when the timing clock is over; wherein the third shutdown operation includes controlling the processor and SE to power down, maintaining the powered on components in a powered on state.

Through the two modes, the automatic shutdown is executed after the SE performs the safety processing on the safety communication data, and the electric quantity of the mobile terminal is prevented from being wasted.

In another aspect, an embodiment of the present application provides a method for controlling an SE, where the method includes: the communication unit receives a communication signal meeting a preset condition and outputs a first power-on signal to a power-on component in the first semiconductor chip according to the communication signal; the power-on component acquires a first power-on signal from the communication unit and triggers a processor in the first semiconductor chip to be powered on; the processor is switched from a first power-down state to a first power-on state under the trigger of the power-on component, the SE power-on indication information is obtained from the power-on component, and the SE power-on in the first semiconductor chip is controlled according to the SE power-on indication information; the SE is switched from a second power-off state to a second power-on state under the control of the processor, interacts with the communication unit for safety communication data, and performs safety processing on the safety communication data; and the PMU is used for supplying power to the processor, the SE, the power-on component and the communication unit.

In yet another aspect, an embodiment of the present application provides a chip including a SE, a processor, and a power-on component. The power-on component is coupled with the communication unit and the PMU and used for receiving the power supply of the PMU, receiving a first power-on signal from the communication unit and triggering the processor to be powered on; the processor is coupled with the power-on component, the SE and the PMU and used for receiving the power supply of the PMU under the trigger of the power-on component, switching from a first power-off state to a first power-on state, acquiring SE power-on indication information from the power-on component and controlling the SE power-on according to the SE power-on indication information; and the SE is coupled with the communication unit, the processor and the PMU and is used for receiving the power supply of the PMU under the control of the processor, switching from the second power-off state to the second power-on state, interacting the safety communication data with the communication unit and carrying out safety processing on the safety communication data. Alternatively, the chip may also be implemented by various possible embodiments or designs in the first aspect.

In yet another aspect, an embodiment of the present application provides a mobile terminal including the system for controlling SE according to the above aspect.

In yet another aspect, the present application provides a computer program product, which when executed by a processor in a first semiconductor chip, is configured to implement the method steps of the processor side according to the above aspect.

In yet another aspect, the present application provides a computer program product for implementing the method steps of the SE side described in the above aspect when the computer program product is executed by the SE in the first semiconductor chip.

Compared with the prior art, in the scheme provided by the embodiment of the application, for the scheme with the built-in SE, the communication unit outputs the first power-on signal to the upper electric module when detecting the communication signal meeting the preset condition, so that the processor is triggered to be powered on, the SE integrated with the processor on the same chip is powered on and started, the secure communication data is interacted with the communication unit and is safely processed, the SE is still triggered to be powered on to be safely processed after the processor is powered off, and the use of the security function is not influenced on the premise of saving the power consumption as much as possible.

Drawings

FIG. 1 is a schematic illustration of an implementation environment provided by one embodiment of the present application;

fig. 2 is a schematic structural diagram of a mobile terminal according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a first semiconductor chip according to an embodiment of the present application;

FIG. 4 is a flow chart of a method of controlling a SE provided by an embodiment of the present application;

FIG. 5 is a flow chart of a method of controlling SE provided by another embodiment of the present application;

FIG. 6 is a flow chart for entering a normal shutdown state from a first shutdown state according to an embodiment of the present application;

FIG. 7 is a flow chart for entering a normal shutdown state from a first shutdown state according to another embodiment of the present application;

fig. 8 is a flowchart of a method for controlling SE according to another embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings. The system architecture and the service scenario described in the embodiment of the present application are for more clearly illustrating the technical solution of the embodiment of the present application, and do not constitute a limitation to the technical solution provided in the embodiment of the present application, and it can be known by a person skilled in the art that the technical solution provided in the embodiment of the present application is also applicable to similar technical problems along with the evolution of the system architecture and the appearance of a new service scenario.

Referring to fig. 1, a schematic diagram of an implementation environment provided by an embodiment of the present application is shown. The implementation environment includes: a mobile terminal 10 and a card reading device 20. The mobile terminal 10 may be a portable electronic device such as a cellular phone, a tablet computer, a wearable device, or the like. The card reading device 20 may be any electronic device with a card reading function, such as a Point Of Sale (POS) machine, a bus card reader, an entrance guard card reader, and the like.

For example, when the card reading device 20 is a POS machine, the mobile terminal 10 may communicate with the card reading device 20 instead of a bank card to complete a card payment operation; when the card reading device 20 is a bus card reader, the mobile terminal 10 may replace a bus card to communicate with the card reading device 20 to complete a bus card swiping operation; when the card reading device 20 is an entrance guard card reader, the mobile terminal 10 may replace an entrance guard card to communicate with the card reading device 20 to complete entrance guard card swiping operation.

The mobile terminal 10 and the card reading device 20 are equipped with adaptive communication units, and the card swiping operation is completed through the communication units. Wherein, the card swiping operation between the mobile terminal 10 and the card reading device 20 can be completed through a short-distance wireless communication technology. Illustratively, when the mobile terminal 10 and the card reading device 20 communicate with each other through a short-range wireless Communication protocol to complete the card swiping operation, the Communication unit may be a short-range Communication chip, such as a Near Field Communication (NFC) chip.

The above application scenario is a card swiping application based on short-distance communication, but in practice, the scheme can be extended to other application scenarios. For example, the communication unit may support various cellular communications, such as a Global System for Mobile communications (GSM) System, a Code Division Multiple Access (CDMA) System, a Wideband Code Division Multiple Access (WCDMA) System, a General Packet Radio Service (GPRS), a Long Term Evolution (LTE) System, an LTE Frequency Division Duplex (FDD) System, an LTE Time Division Duplex (TDD), a Universal Mobile Telecommunications System (UMTS), and the like. When the communication unit supports any type of cellular communication, the mobile terminal 10 may implement communication-based security operations, such as Subscriber Identity Module (SIM) security operations, with a correspondent device (e.g., a server, a base station, etc.).

In the embodiment of the present application, as shown in fig. 2, the mobile terminal 10 adopts a scheme of a built-in SE. The mobile terminal 10 includes a system for controlling the SE, which may include: a first semiconductor chip 11, a communication unit 12 and a PMU 13. The processor 11a, the powered component 11b, and the SE 11c are integrated on the first semiconductor chip 11. Where processor 11a is coupled to SE 11c and PMU13, respectively, SE 11c is coupled to PMU13 and communications unit 12, respectively, and powered component 11b is coupled to PMU13 and communications unit 12, respectively. When the communication unit 12 supports short-range communication, SE 11c correspondingly performs security processing related to card swiping. When the communication unit 12 supports cellular communication, SE 11c performs security processing related to the SIM of the cellular communication, e.g. virtual SIM functions or SIM card security encryption/decryption or authentication functions, respectively. In the following embodiments of the present application, a secure card swiping is taken as an example for introduction, but the application scenario is not used for limiting the application range of the technical solution.

The first semiconductor chip 11 is responsible for handling various operations of the mobile terminal 10, including power-on and power-off operations. Alternatively, the first semiconductor chip 11 is an AP chip of the mobile terminal 10. The AP Chip includes an application processor, and one or more devices other than the application processor to form a System on Chip (SoC). The first semiconductor chip 11 includes at least one memory for storing a program temporarily loaded on the first semiconductor chip 11 and temporary data generated by the processor 11a executing the program, in addition to the processor 11a, the power-on components 11b, and the SE 11 c. For example, the at least one Memory is a Random Access Memory (RAM).

Alternatively, the processor 11a may be an application processor for running a general-purpose operating system of the mobile terminal 10, such as an Android (Android) operating system, an iOS operating system, a Windows operating system, and the like. Illustratively, the processor 11a is a Central Processing Unit (CPU) or a Micro Control Unit (MCU) including an arm (advanced RISC machine) processor. Further, the processor 11a may be used to run various application scenarios or other programs based on the operating system described above.

The power-on component 11b is used for triggering the processor 11a to be powered on when shutdown card swiping is performed. Where powered component 11b is also in a powered state when PMU13 is in a powered state. The powered component 11b includes a Timer (Timer) and a RAM disposed within the powered component 11 b. The timer is used for timing, and when the timing is over, the power-on component 11b is triggered to power on the processor 11 a. The RAM within the powered component 11b is used to temporarily store data when the first semiconductor chip 11 is in a powered down state. The power-up component 11b is configured to be in a power-on state all the time when at least one other portion of the first semiconductor chip 11, such as the processor 11a, is powered down.

The SE 11c is configured to communicate with the communication unit 12, and further configured to perform security processing on secure communication data interacted between the mobile terminal 10 and a peer device (e.g., the card reading device 20 in a card swiping scenario) to improve data security. The security process may include at least one of: data encryption and data integrity protection. The security processes may also include various types of security driver or security application processes. For example, the SE 11c may support a secure Operating System software process, which may be various types of platform software, such as Chip Operating System (COS). A typical COS is an operating system that supports card swiping operations. Further, SE 11c may support secure application software processing. Typical security applications may be card swipe software based on the COS described above.

The communication unit 12 is used for communicating with a card reading device 20 to realize a card swiping operation. For example, when the communication unit 12 is an NFC chip, the NFC chip of the mobile terminal 10 and the NFC chip of the card reader 20 may communicate based on a Radio Frequency Identification (RFID) protocol to interact signals in the card swiping application. As previously described, in other application scenarios, the communication unit 12 may support other types of communications, such as cellular communications. The communication unit 12 is used for performing signal interaction with a peer device, and may include a baseband processor for performing communication protocol and algorithm processing and a transceiver for transceiving signals, and may further include an antenna and a radio frequency front-end device, such as components of filtering, impedance matching, and power amplification.

The PMU13 may be a highly integrated power management unit for portable applications to provide regulated power to the chips (e.g., the first semiconductor chip 11 and the communication unit 12 described above) or to the constituent components of the chips (e.g., the processor 11a, the powered components 11b, and the SE 11c described above). It is understood that PMU13 may be integrated in first semiconductor chip 11 or may exist as a separate chip.

Optionally, as shown in fig. 2, the mobile terminal 10 further includes: and a battery 14. Battery 14 is coupled to PMU13 and communication unit 12, respectively. The battery 14 is used to provide power to the mobile terminal 10. PMU13 may further generate power for first semiconductor chip 11 based on power provided by battery 14.

Optionally, the mobile terminal 10 further includes an external memory, which refers to a memory external to the first semiconductor chip 11. The memory outside the first semiconductor chip 11 may be an Embedded multimedia memory Card (eMMc) or a Universal Flash Storage (UFS). The Memory external to the first semiconductor chip 11 includes a playback Protected Memory Block (RPMB) for storing the execution program of the SE 11 c.

Exemplarily, as shown in fig. 3, a schematic structural diagram of the first semiconductor chip 11 is shown. The first semiconductor chip 11 includes: a processor 11a, a power-on component 11b, an SE 11c, a RAM 11d, and a memory controller 11 e.

The RAM 11d of the first semiconductor chip 11 is a memory in the first semiconductor chip 11 capable of directly exchanging data with the processor 11a, and is generally a storage medium for temporary data generated by a program in which the processor 11a is operating. The memory controller 11e controls data exchange of the first semiconductor chip 11 with the external memory.

Note that the first semiconductor chip 11 in fig. 2 and fig. 3 does not include the communication unit 12 and the PMU13, but this is an example. In fact, PMU13 may or may not be integrated with first semiconductor chip 11; the communication unit 12 may be integrated with the first semiconductor chip 11 or may not be integrated with the first semiconductor chip 11. In the present embodiment, only the case where PMU13 and communication unit 12 are not located on first semiconductor chip 11 will be described. PMU13 and communication unit 12 may be located on the same or different chip than first semiconductor chip 11.

In the embodiment of the application, a technical scheme for the built-in SE is provided, the SE power-on can be still triggered to be safely processed after the processor is powered down, the use of the safety function is not influenced on the premise of saving power consumption as much as possible, for example, the practical application requirements of the user on the operations of card swiping payment, bus card swiping, entrance guard card swiping and the like under the condition that the mobile terminal is in a low-power shutdown state are met, and the technical scheme provided by the embodiment of the application has high practical value.

The embodiments of the present application will be described in further detail below based on the common aspects related to the embodiments of the present application described above. With reference to the mobile terminal 10 shown in fig. 2, when the shutdown card swiping function is implemented by the above system for controlling SE, the functions of the components thereof are as follows:

the communication unit 12 is configured to receive a communication signal meeting a preset condition, and output a first power-on signal to the power-on component 11b according to the communication signal. The communication signal may be various types of communication signals as previously described including, but not limited to, short-range signals and cellular communication signals.

The communication unit 12 in the mobile terminal 10 is capable of receiving different communication signals while the mobile terminal 10 is in the first powered off state. The first power-off state refers to a case where at least one component of the mobile terminal 10 except the power-on component 11b, the communication unit 12, and the PMU13 on the first semiconductor chip 11 is in a power-off state, for example, in the first power-off state, both the processors 11a and SE 11c of the first semiconductor chip 11 are in the power-off state. In this embodiment of the application, the power-down state includes a complete power-down state and a low power consumption state, where the complete power-down state refers to a state where the chip or a component of the chip is not powered on, and is also referred to as a power-off state. The low power consumption state refers to a state that the chip or the components of the chip consume lower power consumption to maintain operation compared with a normal working state, and the starting speed of the chip or the components of the chip is faster when the chip or the components of the chip enter the normal working state from the power-off state compared with the state that the chip or the components of the chip enter the normal working state from the low power consumption state. For example, in a low power consumption state, a component of a chip may not perform the function or complete function of the component. For another example, in a low power state, the components of the chip only accept the lowest voltage, but the voltage is not sufficient to maintain it for full processing functionality. As mentioned above, each Unit in fig. 2 and 3 may be a component in a chip, and the chip may include other components, for example, the first semiconductor chip 11 may further include at least one of a Graphics Processing Unit (GPU), a codec, an interface circuit, a Three Dimensional (3D) Processing circuit, an Image Signal Processing (ISP), an Artificial Intelligence (AI) processor, an audio processor, or a sensor hub. At least one of these components may be powered down while the powered component 11b remains in an always-on state, as with the processor 11a, to save power consumption.

The card reading device 20 capable of cooperating with the mobile terminal 10 to implement the card swiping function may emit communication signals meeting preset conditions to the outside, and the communication signals are used for enabling the mobile terminal 10 around the card reading device 20 to sense the existence of the card reading device 20. For example, the card reading device 20 continuously transmits the communication signal outward, or transmits the communication signal outward once every predetermined time interval. The communication unit 12 in the mobile terminal 10 detects whether the communication signal meets a preset condition after receiving the communication signal, and outputs a first power-on signal to the power-on component 11b if the communication signal meets the preset condition. Exemplarily, assuming that the communication unit 12 is an NFC chip, when the NFC chip receives a communication signal meeting a preset condition, a first power-on signal is Output to the power-on component 11b through a General Purpose Input/Output (GPIO) interface. The power-on component 11b is provided with a GPIO interface for acquiring the first power-on signal. The first power-on signal is used to trigger the power-on component 11b to control the processor 11a to power on.

Optionally, the preset condition is that the communication signal includes a preset identifier. The preset identifier is used for the communication unit 12 in the mobile terminal 10 to recognize whether the communication signal received by the communication unit is a communication signal related to the card swiping function provided by the communication unit. For example, the communication signal detected by the communication unit 12 in the mobile terminal 10 includes a preset identifier related to the bus card swiping function, and after the communication unit 12 recognizes the preset identifier, it determines to subsequently perform the bus card swiping operation. Alternatively, the preset condition is that the frequency of the communication signal is within a preset frequency band. The preset frequency band may be preset according to actual requirements, for example, the preset frequency band may be a frequency band used by NFC, or may be a sub-frequency band in the frequency band used by NFC. Of course, in other possible embodiments, the preset condition may also be that the interval of the communication signal is a preset time length, and the preset time length may be a numerical value or a value range. In practical applications, the preset condition may be preset according to actual requirements, so as to ensure that the communication unit 12 can accurately identify the communication signal related to the card swiping function provided by itself and other unrelated communication signals. When the communication unit 12 is a short-range communication chip, such as an NFC chip, the communication signal may be a radio frequency signal.

And the power-on component 11b is used for acquiring a first power-on signal from the communication unit 12 and triggering the processor 11a to be powered on.

Optionally, the power-on component 11b triggers the processor 11a to power on by: powered component 11b outputs a second power-on signal to PMU13, which triggers PMU13 to provide power to processor 11 a. PMU13 obtains a second power-on signal from powered component 11b and provides power to processor 11a based on the second power-on signal.

Optionally, the powered component 11b includes a first register. The power-on component 11b is further configured to write, in the first register, SE power-on indication information for indicating to control the power-on of the SE 11c after acquiring the first power-on signal. For example, the SE power-on indication information written by the power-on component 11b in the first register is "01" for instructing the processor 11a to control the SE 11c to power on.

The processor 11a is configured to switch from the first power-down state to the first power-up state under the trigger of the power-up component 11b, acquire SE power-up indication information from the power-up component 11b, and control the SE 11c to power up according to the SE power-up indication information.

The first power-down state may be a fully powered-down state or a low power consumption state, and the first power-up state is a powered-on state. Optionally, the processor 11a obtains SE power-on indication information from a first register of the power-on component 11 b.

Optionally, the processor 11a controls the SE 11c to power up by: processor 11a sends a third power-up signal to PMU13, which instructs PMU13 to supply power to SE 11 c. PMU13 receives a third power-up signal from processor 11a and provides power to SE 11c based on the third power-up signal.

And the SE 11c is configured to switch from the second power-off state to the second power-on state under the control of the processor 11a, interact secure communication data with the communication unit 12, and perform secure processing on the secure communication data.

The second power-down state may be a fully powered-down state or a low power consumption state, while the second power-up state is a powered-on state. Illustratively, when the card reading device 20 is a POS, after the SE 11c is powered on, the communication unit 12 communicates with the communication unit 12 and interacts payment information, and at the same time, the payment information is processed securely, and the communication unit 12 communicates with the POS to complete a card swiping payment operation; when the card reading device 20 is a bus card reader, after the SE 11c is powered on, the communication unit 12 communicates with the communication unit 12 and interacts bus card information, and meanwhile, the bus card information is safely processed, and the communication unit 12 communicates with the bus card reader to complete bus card swiping operation; when the card reading device 20 is an entrance guard card reader, after the SE 11c is powered on, the communication unit 12 communicates with the communication unit 12 and interacts with entrance guard information, and meanwhile, security processing is performed on the entrance guard information, and the communication unit 12 communicates with the entrance guard card reader to complete entrance guard card swiping operation.

In the scheme provided by the embodiment of the application, for the scheme with the built-in SE, when receiving a communication signal meeting a preset condition, the communication unit 12 outputs a first power-on signal to the power-on component 11b, so that the processor 11a is triggered to be powered on, the SE 11c integrated on the same chip with the processor 11a is powered on and started, the secure communication data is interacted with the communication unit 12 and is safely processed, the SE 11c can be still triggered to be powered on for safe processing after the processor 11a is powered off, and the use of a secure function is not influenced on the premise of saving power consumption as much as possible.

The following are examples of the method of the present application, which correspond to the above product examples. For the content not described in the product embodiments of the present application, refer to the method embodiments of the present application; similarly, for the content not described in the method embodiments of the present application, reference may be made to the product embodiments of the present application.

Referring to fig. 4, a flowchart of a method for controlling a SE according to an embodiment of the present application is shown. The method may be applied to the mobile terminal 10 shown in fig. 2. The method may include the steps of:

in step 401, the communication unit 12 receives a communication signal meeting a preset condition, and outputs a first power-on signal to the power-on component 11b according to the communication signal.

In the first powered-off state of the mobile terminal 10, the communication unit 12 is in a powered-on state and is capable of receiving communication signals from the card reading device 20. When the communication unit 12 receives a communication signal meeting a preset condition, a first power-on signal is output to the power-on component 11b, and the first power-on signal is used for instructing the power-on component 11b to trigger the processor 11a to be powered on.

At step 402, the power-on component 11b obtains a first power-on signal from the communication unit 12 and triggers the processor 11a to power on.

After the power-on component 11b acquires the first power-on signal, the processor 11a is automatically triggered to be powered on. Optionally, the powered component 11b includes a first register. After acquiring the first power-on signal, the power-on component 11b writes SE power-on instruction information for instructing to control the power-on of the SE 11c in the first register.

In step 403, the processor 11a switches from the first power-down state to the first power-up state under the trigger of the power-up component 11b, acquires the SE power-up indication information from the power-up component 11b, and controls the SE 11c to power up according to the SE power-up indication information.

After switching from the first power-down state to the first power-up state, the processor 11a acquires indication information from the power-up component 11b, and performs a subsequent operation according to the indication information. Optionally, the processor 11a obtains the indication information from a first register of the powered component 11 b. If the indication information acquired by the processor 11a is SE power-on indication information, it indicates that the processor 11a is triggered to be powered on when the mobile terminal 10 is in the first power-off state, and the processor 11a controls the SE 11c to be powered on and started.

In addition, if the instruction information acquired by the processor 11a is normal boot instruction information, it indicates that the processor 11a is triggered to be powered on under the conditions of key boot, timer boot, charging boot, or the like, and then the processor 11a executes a normal boot operation. The normal booting operation includes starting an operating system and displaying a User Interface (UI).

In step 404, the SE 11c switches from the second power-off state to the second power-on state under the control of the processor 11a, interacts the secure communication data with the communication unit 12, and performs secure processing on the secure communication data.

After switching from the second power-off state to the second power-on state, the SE 11c communicates with the communication unit 12 and interacts with the secure communication data, completing the card swiping operation. The SE 11c performs security processing on the secure communication data, and the purpose of the security processing is to ensure the security of data interacting with the communication unit 12. For example, secure communication data is subjected to security arithmetic processing such as encryption/decryption, Message Authentication Code (MAC) calculation, or MAC solution calculation.

Alternatively, after the SE 11c is powered on and started, it can communicate with the communication Unit 12 through a Single Wire Protocol (SWP) to receive and respond to an Application Protocol Data Unit (APDU) command required for a card swiping operation, which is sent by the communication Unit 12.

Optionally, the communication unit 12 is an NFC chip. When the SE 11c communicates with the NFC chip and finishes the card swiping operation, the NFC chip can perform a card simulation operation, where the card simulation operation is to simulate a card signal to be swiped by the NFC chip, so as to swipe the card.

Referring to fig. 5, a flowchart of a method for controlling a SE according to another embodiment of the present application is shown. The method may be applied to the mobile terminal 10 shown in fig. 2. The method may include the steps of:

in step 501, the communication unit 12 receives a communication signal meeting a preset condition, and outputs a first power-on signal to the power-on component 11b according to the communication signal.

At step 502, the power-on component 11b obtains a first power-on signal from the communication unit 12 and triggers the processor 11a to power on.

Step 501 and step 502 are the same as step 401 and step 402 in the embodiment of fig. 4, and refer to the description in the embodiment of fig. 4, which is not described again in this embodiment.

In step 503, the processor 11a runs the processor ROM program, and runs the boot program through the processor ROM program.

After the processor 11a is powered on, a processor ROM program is executed, and the processor ROM program is stored in a Read-Only Memory (ROM) corresponding to the processor 11a, which may be in the first semiconductor chip 11. The processor ROM program is used to determine whether the processor 11a needs to run a boot program. The processor 11a judges whether the mobile terminal 10 is in a first power-off state when being triggered to be powered on through a processor ROM program; if yes, operating a bootstrap program; if not, executing normal starting operation. The boot program is used to control the processor 11a to perform operations associated with the first power-off state, such as controlling the SE 11c to power up in the first power-off state. If the processor 11a determines that the mobile terminal 10 is not in the first power-off state when the processor 11a is triggered to power on through the processor ROM program, it indicates that the mobile terminal 10 is triggered to power on in the normal power-off state, so the processor 11a executes the normal power-on operation. Alternatively, the normal power-off state refers to a situation where all components in the mobile terminal 10 are in a power-off state.

Optionally, a second register is further included in the powered component 11 b. When the processor 11a controls the mobile terminal 10 to enter the first power-off state, the first status data is written in the second register of the power-on component 11b, and the first status data is used to indicate that the mobile terminal 10 is in the first power-off state when the processor 11a is triggered to be powered on. After the processor 11a is powered on and started, the processor ROM program is run, the first status data is obtained from the second register through the processor ROM program, and it is determined that the mobile terminal 10 is in the first power-off state when it is triggered to be powered on according to the first status data. In addition, when the processor 11a controls the mobile terminal 10 to enter the normal power-off state, second status data is written in a second register in the power-on component 11b, where the second status data is used to indicate that the mobile terminal 10 is not in the first power-off state when the processor 11a is triggered to be powered on. After the processor 11a is powered on and started, the processor ROM program is run, the processor ROM program is used to obtain the second status data from the second register, and the mobile terminal 10 is determined not to be in the first power-off state when being triggered to be powered on according to the second status data

In one possible embodiment, after the processor 11a determines that the mobile terminal 10 is in the first power-off state when it is triggered to power up, the processor obtains a boot program from a memory external to the first semiconductor chip 11 through the memory controller, and verifies the validity of the boot program to ensure data security.

In another possible embodiment, when the processor 11a controls the mobile terminal 10 to enter the first power-off state, the storage controller obtains the boot program stored in the memory outside the first semiconductor chip 11, verifies the validity of the boot program to ensure data security, and stores the boot program in the RAM of the powered component 11 b. The processor 11a obtains the boot program from the RAM of the powered component 11b after determining that the mobile terminal 10 is in the first powered off state when it is triggered to be powered on.

At step 504, the processor 11a obtains the SE power-on instruction information from the power-on component 11b through the boot program, and controls the SE 11c to power on.

The processor 11a obtains the SE power-on instruction information from the first register of the power-on component 11b through the boot program, and controls the SE 11c to power on and start according to the SE power-on instruction information.

Alternatively, after acquiring the SE power-on instruction information, the processor 11a loads the execution program of the SE 11c from the memory outside the first semiconductor chip 11 to the memory inside the first semiconductor chip 11 by the boot program, and the processor 11a can access the memory outside the first semiconductor chip 11 through the memory controller in the first semiconductor chip 11. The executing program of the SE 11c may be COS. In the present embodiment, the execution program of the SE 11c is stored in the memory outside the first semiconductor chip 11, and the execution program of the SE 11c is acquired from the memory outside the first semiconductor chip 11, so that the storage space of the SE 11c can be saved, and the SE 11c can be designed to be thinner and lighter. In other possible embodiments, the execution program of the SE 11c may also be stored in a memory inside the SE 11c, or in a memory inside the first semiconductor chip 11.

In step 505, the SE 11c runs the ROM program of the SE 11c, and loads the execution program of the SE 11c through the ROM program of the SE 11 c.

After the SE 11c is powered on and started, the ROM program of the SE 11c is executed, and the ROM program of the SE 11c is used for loading the execution program of the SE 11 c. The ROM program of SE 11c is stored in the ROM inside SE 11 c.

The SE 11c loads its execution program from the memory inside the first semiconductor chip 11 into the memory inside the SE 11 c. Since the SE 11c cannot directly load the execution program of the SE 11c from the memory outside the first semiconductor chip 11, the processor 11a loads the execution program of the SE 11c from the memory outside the first semiconductor chip 11 into the memory inside the first semiconductor chip 11, and the SE 11c loads the execution program thereof from the memory inside the first semiconductor chip 11 into the memory inside the SE 11c by the ROM program of the SE 11c and runs the execution program.

Alternatively, the execution program of SE 11c may be an image file, and the image file may make a specific series of files into a single file according to a certain format, so as to facilitate loading and running.

Alternatively, the ROM program of SE 11c is executed by the processor in SE 11c, and the execution program of SE 11c is loaded into the RAM of SE 11c and executed by the processor of SE 11 c.

Optionally, before the SE 11c runs the ROM program of the SE 11c or executes the program, the validity of the program to be run is checked to ensure data security. Illustratively, taking the execution program of the SE 11c as an example, if the check result is that the execution program of the SE 11c is legal, the SE 11c runs the execution program; if the result of the verification is that the execution program of the SE 11c is illegal, the SE 11c does not run the execution program.

At step 506, the SE 11c interacts secure communication data with the communication unit 12 through its execution program, and performs secure processing on the secure communication data.

After the SE 11c runs its execution program, it communicates with the communication unit 12, and during the communication, the SE 11c can read data to be transmitted to the communication unit 12 from a memory outside the first semiconductor chip 11 through interaction with the processor 11a, and at the same time, the SE 11c can write data received from the communication unit 12 into a memory outside the first semiconductor chip 11 through interaction with the processor 11 a.

Alternatively, the SE 11c interacts with the processor 11a through Inter-Process Communication (IPC) and Mailbox memory (Mailbox) after running its execution program to access data stored in a memory outside the first semiconductor chip 11. The mailbox memory may also be replaced by a bus bridge, which is a dedicated interaction channel between the processors 11a and SE 11 c.

In this embodiment, the SE 11c is a hardware independent from the processor 11a, and can implement processing of various security services. Unlike a conventional secure enclave (Trustzone) or Trusted Execution Environment (TEE), the various types of computations that SE 11c performs secure processing may not be dependent on processor 11 a. For example, a processor dedicated to secure processing is included in SE 11c for running a COS or a secure application given to the COS. For another example, the SE 11c may further include a memory dedicated to security processing, such as a RAM or a ROM, and various hardware accelerators dedicated to security processing, such as a key generator, a cryptographic device, a Hash (Hash) device, or a One Time Programmable (OTP) memory. As another example, there may be a secure separation between SE 11c and the other device or devices in the first semiconductor chip 11 such that the other device or devices may not have any access to the data stored or running in SE 11 c. In a typical scenario, there is a secure isolation between SE 11c and processor 11 a. Under the above-described security isolation, the processor 11a cannot freely access the data stored or run in the SE 11 c. Under the above-mentioned security isolation, data interaction between the SE 11c and the processor 11a or other devices needs to pass through the aforementioned dedicated interaction channel. The dedicated interaction channel includes, but is not limited to, the mailbox memory and the bus bridge described above.

The SE 11c and communication unit 12 interaction secure communication data may be used for a card swipe operation. After completing the card swiping operation, the mobile terminal 10 may revert to the first powered-off state, so the processor 11a may perform a third powering-off operation after completing the card swiping operation, the third powering-off operation including controlling the processors 11a and SE 11c to power down, maintaining the powered-on component 11b in a powered-on state. When the processor completes the third power-off operation, only the powered component 11b present in the first semiconductor chip is in a powered-on state.

In one possible implementation, after the SE 11c is powered on and started, the processor 11a performs a third shutdown operation after a preset time period. The processor 11a is able to perform the third shutdown operation after the preset time period by the boot program. Illustratively, assuming the preset time period is 10 seconds, the processor 11a performs a third shutdown operation by the boot program after the SE 11c is powered on for 10 seconds.

In another possible implementation, after the SE 11c is powered on, the processor 11a starts the timing clock, and upon receiving a reset command sent by the SE 11c, the processor 11a resets the timing clock, and upon the timing clock timing out, the processor 11a performs a third shutdown operation. When the SE 11c communicates with the communication unit 12, a reset command is sent to the processor 11a every time a signal from the communication unit 12 is received, and the processor 11a resets the timing clock by the bootstrap program when receiving the reset command.

Through the two modes, the first power-off state is automatically entered after the card swiping operation is completed, and the electric quantity of the mobile terminal 10 is prevented from being wasted. In addition, in the automatic shutdown process, if the processor 11a receives a trigger signal for normal startup, the shutdown operation is not executed any more, and the normal startup operation is directly executed.

Optionally, the processor 11a in the first semiconductor chip 11 is a control device of the chip, and may be a CPU or an MCU, and since the MCU consumes less power, using the MCU as the processor 11a helps to reduce the power consumption of the first semiconductor chip 11 when the card is swiped in a shutdown mode. When the processor 11a is an MCU, another CPU exists in the system, that is, in the first semiconductor chip 11, and in this case, the other CPU is a main core of the first semiconductor chip 11, and the power consumption of the processor 11a is lower than that of the above main core, which is equivalent to a low power consumption core. At this time, the primary core is an application processor for running an operating system such as android and application software based on the operating system. Illustratively, the processor 11a is only used to implement necessary control functions, such as power consumption control for the entire first semiconductor chip 11 or parts thereof, and is not used to run a complicated operating system and application programs. The power consumption control includes, but is not limited to, adjustment of a clock frequency, an operating voltage, or an operating current. Further, the power consumption of the SE 11c may be lower than that of the processor 11 a.

In the scheme provided by the embodiment of the application, for the scheme of the built-in SE, when a communication signal meeting a preset condition is detected, the communication unit 12 outputs a first power-on signal to the power-on component 11b, so that the processor 11a is triggered to be powered on, the SE integrated with the processor 11a on the same chip is powered on and started, the secure communication data is interacted with the communication unit 12 and is safely processed, the SE is still triggered to be powered on to be safely processed after the processor 11a is powered off, and the use of a security function is not influenced on the premise of saving power consumption as much as possible.

The above embodiment describes the method for controlling the SE 11c in the first power-off state, and the following embodiment of fig. 6 describes the process of controlling the mobile terminal 10 to enter the first power-off state and to enter the normal power-off state from the first power-off state. Referring to fig. 6, the process may include the following steps:

in step 601, the processor 11a performs a first shutdown operation.

In the embodiment of the present application, the user may select whether to start the function of entering the first power-off state through the configuration item in the mobile terminal 10. If the mobile terminal 10 is turned on, the processor 11a executes a first power-off operation when the mobile terminal 10 is powered off, so that the mobile terminal 10 enters a first power-off state, and a power-off card swiping function can be realized. Wherein the first shutdown operation comprises: the control processors 11a and SE 11c are powered down. Optionally, the first shutdown operation may need to control power down of other components of the mobile terminal 10 besides the communication unit 12 and the PMU13, in addition to the processors 11a and SE 11 c.

In a possible implementation, the processor 11a performs the first shutdown operation when receiving the first shutdown signal sent by the PMU13, where the first shutdown signal is sent by the PMU13 to the processor 11a when detecting that the battery level is less than the first preset threshold. Wherein the first preset threshold value can be set according to practical experience. Illustratively, the battery power is 3000mAh, the first preset threshold is 150mAh, and when the battery power is less than 150mAh, the processor 11a performs a first power-off operation, so that the mobile terminal 10 enters a first power-off state, and meanwhile, it is ensured that the mobile terminal 10 still has a power of 150mAh for power-off card swiping.

In another possible embodiment, the processor 11a executes the first shutdown operation when detecting a second shutdown signal triggered by the user, where the second shutdown signal is a signal triggered by a manual shutdown operation of the user, for example, when the user presses a power key for shutdown for a long time, the second shutdown signal is triggered, and the processor 11a executes the first shutdown operation when detecting the second shutdown signal.

In step 602, the PMU13 outputs a fourth power-on signal to the power-on component 11b when detecting that the battery power is less than the second preset threshold.

After the mobile terminal 10 enters the first powered-off state, the mobile terminal 10 is still consuming battery power because the powered component 11b, PMU13, and communication unit 12 are still in a powered-on state. When the battery level is below the second preset threshold, the PMU13 outputs a fourth power-up signal to the power-on component 11 b. The second preset threshold value can be set according to actual experience or user requirements, and is smaller than the first preset threshold value.

At step 603, power-on component 11b obtains a fourth power-on signal from PMU13 and triggers processor 11a to power up.

Optionally, the powered component 11b includes a first register. After acquiring the fourth power-on signal, the power-on component 11b writes shutdown instruction information for instructing execution of the second shutdown operation in the first register. For example, the power-off indication information written by the powered-on component 11b in the first register is "11" for instructing the processor 11a to execute the second power-off operation.

In step 604, the processor 11a switches from the first power-down state to the first power-on state under the trigger of the power-on component 11b, acquires the power-off instruction information from the power-on component 11b, and executes the second power-off operation according to the power-off instruction information.

The processor 11a performs a second power-off operation such that the mobile terminal 10 enters a normal power-off state. The second shutdown operation includes: the control processors 11a, SE 11c and the power-up assembly 11b are powered down. Optionally, the second shutdown operation further includes: controlling the PMU13 and the communication unit 12 to power down.

In this embodiment of the application, after the mobile terminal enters a first shutdown state in which the card swiping operation can be shut down, the PMU13 detects the battery power, and when the battery power is lower than a second preset threshold, the PMU13 outputs a fourth power-on signal to the power-on component 11b, so that the power-on component 11b triggers the processor 11a to be powered on, and the processor 11a executes a second shutdown operation to enable the mobile terminal to enter a normal shutdown state. Through the mode, the mobile terminal is prevented from consuming electric quantity in the first power-off state, so that a part of electric quantity is reserved for subsequent use (such as dialing an emergency call, starting a power-off alarm clock and the like).

The above-described embodiment of fig. 6 describes one possible scenario for controlling the mobile terminal 10 to enter the normal power-off state from the first power-off state. The following embodiment of fig. 7 will describe another scenario for controlling the mobile terminal 10 to enter the normal power-off state from the first power-off state. Please refer to fig. 7, which may include the following steps:

in step 701, the processor 11a performs a first shutdown operation.

Step 701 is the same as step 601 in the embodiment of fig. 6, and reference is made to the description in the embodiment of fig. 6, which is not repeated herein.

At step 702, the powered component 11b starts a timer after the processor 11a performs the first shutdown operation.

The powered component 11b starts the timer after the processor 11a performs the first power-off operation, that is, after the mobile terminal 10 enters the first power-off state, the powered component 11b starts the timer to start timing.

In step 703, when the timer times out, the power-on component 11b triggers the processor 11a to power on.

When the mobile terminal 10 enters the first power-off state and a time length set by the timer elapses, the power-on component 11b triggers the processor 11a to power on. Optionally, the powered component 11b includes a first register. The powered-on component 11b writes shutdown instruction information for instructing execution of the second shutdown operation in the first register when the timer times out.

In step 704, the processor 11a switches from the first power-down state to the first power-on state under the trigger of the power-on component 11b, acquires the power-off instruction information from the power-on component 11b, and executes the second power-off operation according to the power-off instruction information.

Step 704 is the same as step 604 in the embodiment of fig. 6, and please refer to the description in the embodiment of fig. 6 for details, which is not repeated herein.

In this embodiment of the application, after the mobile terminal enters the first shutdown state capable of performing shutdown and card swiping, the power-on component 11b controls the processor 11a to be powered on after the time duration set by the timer is timed by the timer, and the processor 11a executes the second shutdown operation to enable the mobile terminal to enter the normal shutdown state. Through the mode, the time length for the mobile terminal to enter the first power-off state can be set according to user requirements, and the situation that the mobile terminal consumes the electric quantity in the first power-off state due to the fact that the mobile terminal keeps the first power-off state for too long time is avoided, so that a part of electric quantity is reserved for follow-up use (such as dialing of an emergency call, starting of a power-off alarm clock and the like).

An exemplary embodiment of the present application also provides a chip, namely the first semiconductor chip 11 introduced above, which includes the SE 11c, the processor 11a and the power-on component 11b as mentioned in the previous embodiments.

An exemplary embodiment of the present application also provides a method of controlling SE, which is applied to the first semiconductor chip 11, as shown in fig. 8, and includes the following steps:

at step 801, power-on component 11b receives power from PMU13, receives a first power-on signal from communication unit 12, and triggers processor 11a to power up.

In step 802, the processor 11a receives power supplied by the PMU13 under the trigger of the power-up component 11b and switches from the first power-down state to the first power-up state, acquires SE power-up indication information from the power-up component 11b, and controls the SE 11c to power up according to the SE power-up indication information.

At step 803, SE 11c receives power from PMU13 under the control of processor 11a and switches from the second power-down state to the second power-up state, interacts with communication unit 12 for secure communication data, and performs secure processing on the secure communication data.

For the description of the two embodiments, refer to the description of the corresponding contents above, and will not be described herein again.

An exemplary embodiment of the present application also provides a computer program product, which may be stored in a RAM, a flash memory, a ROM, an Erasable Programmable read-only memory (EPROM), an Electrically Erasable Programmable read-only memory (EEPROM), a register, or any other form of storage medium known in the art, and when the computer program product is executed by the processor 11a, the computer program product implements the method steps of the processor 11a side in the above-described embodiments.

An exemplary embodiment of the present application further provides a computer program product, which may be stored in a RAM, a flash memory, a ROM, an EPROM, an EEPROM, a register, or any other form of storage medium known in the art, and which, when executed by the SE 11c, is adapted to perform the method steps of the SE 11c side in the above-described embodiment.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the embodiments of the present application in further detail, and it should be understood that the above-mentioned embodiments are only specific embodiments of the present application, and are not intended to limit the scope of the embodiments of the present application, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the embodiments of the present application should be included in the scope of the embodiments of the present application.

Claims

1. A system for controlling a Secure Element (SE) comprises the SE, a processor, a power-on component, a Power Management Unit (PMU) and a communication unit; the SE, the processor and the power-on component are positioned in the first semiconductor chip;

the communication unit is used for receiving a communication signal meeting a preset condition and outputting a first power-on signal to the power-on assembly according to the communication signal;

the power-on component is used for acquiring the first power-on signal from the communication unit and triggering the processor to be powered on;

the processor is used for switching from a first power-down state to a first power-on state under the trigger of the power-on component, acquiring SE power-on indication information from the power-on component and controlling the SE to be powered on according to the SE power-on indication information;

the SE is used for switching from a second power-off state to a second power-on state under the control of the processor, interacting safety communication data with the communication unit and carrying out safety processing on the safety communication data;

the PMU is used for supplying power to the processor, the SE, the power-on component and the communication unit.

2. The system of claim 1,

in an aspect that the power-up component is used for triggering the processor to power up, the power-up component is specifically used for outputting a second power-up signal to the PMU;

the PMU is configured to obtain the second power-on signal from the power-on component, and supply power to the processor according to the second power-on signal.

3. The system according to claim 1 or 2,

in aspects where the processor is configured to control the powering up of the SE, the processor is specifically configured to send a third power up signal to the PMU;

the PMU is configured to receive the third power-on signal from the processor and supply power to the SE according to the third power-on signal.

4. The system according to claim 1 or 2,

the PMU is further used for sending a first shutdown signal to the processor when the detected battery power is smaller than a first preset threshold value;

the processor is further configured to receive the first shutdown signal from the PMU, and execute a first shutdown operation according to the first shutdown signal, where the first shutdown operation includes: controlling the processor and the SE to power down.

5. The system of claim 3,

6. The system of claim 4,

the PMU is further configured to output a fourth power-on signal to the power-on component when it is detected that the battery power is less than a second preset threshold, where the second preset threshold is less than the first preset threshold;

the power-on component is further configured to obtain the fourth power-on signal from the PMU and trigger the processor to power on;

the processor is further configured to switch from the first power-down state to the first power-up state under the trigger of the power-up component, acquire power-off indication information from the power-up component, and execute a second power-off operation according to the power-off indication information, where the second power-off operation includes: controlling the processor, the SE, and the power-up component to power down.

7. The system of claim 5,

8. The system of claim 4,

the power-on component is further configured to start a timer after the processor performs the first shutdown operation; when the timer is overtime, triggering the processor to be powered on;

9. The system according to any one of claims 5 to 7,

10. The system according to claim 3, wherein the predetermined condition is that the communication signal includes a predetermined identifier, or the predetermined condition is that the frequency of the communication signal is within a predetermined frequency band.

11. The system according to claim 4, wherein the predetermined condition is that the communication signal includes a predetermined identifier, or the predetermined condition is that the frequency of the communication signal is within a predetermined frequency band.

12. The system according to claim 9, wherein the predetermined condition is that the communication signal includes a predetermined identifier, or the predetermined condition is that the frequency of the communication signal is within a predetermined frequency band.

13. The system according to any one of claims 1, 2, and 5 to 8, wherein the preset condition is that the communication signal includes a preset identifier, or that the frequency of the communication signal is within a preset frequency band.

14. The system of any one of claims 1, 2, 5 to 8, and 10 to 12,

the processor is further configured to load an execution program of the SE from a memory external to the first semiconductor chip into a memory internal to the first semiconductor chip after acquiring the SE power-on instruction information from the power-on component;

and the SE is further configured to load the execution program from a memory inside the first semiconductor chip into a memory inside the SE after switching from the second power-off state to the second power-on state under the control of the processor, and run the execution program to implement a function of interacting secure communication data with the communication unit and performing secure processing on the secure communication data.

15. The system of claim 3,

16. The system of claim 4,

17. The system of claim 9,

18. The system of claim 13,

19. The system of any one of claims 1, 2, 5 to 8, 10 to 12, and 15 to 18, wherein the processor is further configured to:

executing a third shutdown operation after the SE is powered on for a preset time length;

alternatively, the first and second electrodes may be,

starting a timing clock after the SE is powered on, resetting the timing clock when a reset command sent by the SE is received, wherein the reset command is sent to the processor by the SE every time the SE receives a signal from the communication unit, and the third shutdown operation is executed when the timing clock is over time;

wherein the third shutdown operation includes controlling the processor and the SE to power down, maintaining the powered component in a powered state.

20. The system of claim 3, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

21. The system of claim 4, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

22. The system of claim 9, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

23. The system of claim 13, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

24. The system of claim 14, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

25. A method of controlling a secure element SE, the method comprising:

the communication unit receives a communication signal meeting a preset condition and outputs a first power-on signal to a power-on component in the first semiconductor chip according to the communication signal;

the power-on component acquires the first power-on signal from the communication unit and triggers a processor in the first semiconductor chip to be powered on;

the processor is switched from a first power-down state to a first power-up state under the trigger of the power-up component, SE power-up indication information is obtained from the power-up component, and the SE power-up in the first semiconductor chip is controlled according to the SE power-up indication information;

the SE is switched from a second power-off state to a second power-on state under the control of the processor, interacts with the communication unit for safety communication data, and performs safety processing on the safety communication data;

powering, by the PMU, the processor, the SE, the powered component, and the communication unit.

26. The method of claim 25, further comprising:

when the PMU detects that the battery power is smaller than a first preset threshold value, the PMU sends a first shutdown signal to the processor;

the processor receives the first shutdown signal from the PMU, and executes a first shutdown operation according to the first shutdown signal, wherein the first shutdown operation comprises: controlling the processor and the SE to power down.

27. The method of claim 26, further comprising:

when the PMU detects that the battery power is smaller than a second preset threshold value, the PMU outputs a fourth power-on signal to the power-on component;

the power-on component acquires the fourth power-on signal from the PMU and triggers the processor to be powered on;

the processor is switched from the first power-down state to the first power-up state under the trigger of the power-up component, acquires power-off indication information from the power-up component, and executes a second power-off operation according to the power-off indication information, wherein the second power-off operation comprises: controlling the processor, the SE, and the power-up component to power down.

28. The method of claim 26 or 27, further comprising:

the powered-on component starts a timer after the processor performs the first shutdown operation;

when the timer is overtime, the power-on component triggers the processor to be powered on;

29. A chip, comprising a Secure Element (SE), a processor and a power-on component;

the power-on component is coupled with the communication unit and the PMU, and is used for receiving the power supply of the PMU, receiving a first power-on signal from the communication unit and triggering the processor to be powered on;

the processor is coupled to the power-on component, the SE and the PMU and used for receiving power supply of the PMU under the trigger of the power-on component, switching from a first power-down state to a first power-on state, acquiring SE power-on indication information from the power-on component and controlling the SE to be powered on according to the SE power-on indication information;

the SE, coupled to the communication unit, the processor and the PMU, is configured to receive power supplied by the PMU and switch from a second power-down state to a second power-up state under the control of the processor, interact with the communication unit for secure communication data, and perform secure processing on the secure communication data.

30. The chip of claim 29,

in an aspect that the power-up component is configured to trigger the processor to power up, the power-up component is specifically configured to output a second power-up signal to the PMU to instruct the PMU to supply power to the processor.

31. The chip of claim 29 or 30,

in an aspect where the processor is configured to control power-up of the SE, the processor is specifically configured to send a third power-up signal to the PMU to instruct the PMU to supply power to the SE.

32. The chip of claim 29 or 30,

the processor is further configured to receive a first shutdown signal from the PMU, and execute a first shutdown operation according to the first shutdown signal, where the first shutdown operation includes: controlling the processor and the SE to power down.

33. The chip of claim 31,

34. The chip of claim 32,

the power-on component is further configured to obtain a fourth power-on signal from the PMU and trigger the processor to power on;

35. The chip of claim 33,

36. The chip of claim 32,

37. The chip according to any of claims 33 to 35,

38. The chip of any one of claims 29, 30, and 33 to 36,

the processor is further configured to load an execution program of the SE from a memory external to a first semiconductor chip into a memory internal to the first semiconductor chip after acquiring the SE power-on instruction information from the power-on component;

39. The chip of claim 31,

40. The chip of claim 32,

41. The chip of claim 37,

42. The chip according to any one of claims 29, 30, 33 to 36, and 39 to 41, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

43. The chip of claim 31, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

44. The chip of claim 32, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

45. The chip of claim 37, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,

46. The chip of claim 38, wherein the processor is further configured to:

alternatively, the first and second electrodes may be,