CN109804356B - Auto-learning log-likelihood ratio - Google Patents

Abstract

A method for identifying log-likelihood ratio (LLR) values, comprising: background reads are performed at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s), and the stored read result and the identified codeword(s) are used to identify a set of LLR values. The process is repeated to identify a set of LLR values and an updated set of LLR values for each block. The host-requested read is performed and decoded using LLR values from the updated set of LLR values corresponding to the block being read.

Description

Auto-learning log-likelihood ratio

Background

Error correction methods using soft information have been widely adopted to achieve the low level of Uncorrectable Bit Error Rate (UBER) required by clients and enterprise Solid State Drives (SSDs). Error correction methods using soft information typically require testing of sample flash memory devices in a laboratory to identify log-likelihood ratio (LLR) values indicative of the Bit Error Rate (BER) of the device under test. These LLRs are then stored in tables in each SSD, which are used by the memory controller to decode reads to the NAND flash memory chips.

The process of characterizing NAND flash memory chips is expensive and time consuming. In addition, the characteristics of the NAND flash memory chip change over the life of the NAND flash memory device, making accurate characterization difficult and requiring storage of a large number of LLR tables. In addition, the memory space required to store the LLR tables increases the overhead of the SSD.

Therefore, there is a need for a method and apparatus that will allow error correction using soft information that does not require laboratory testing of exemplary NAND flash memory chips, and will provide LLR values that accurately indicate the BER of NAND flash memory chips.

SUMMARY

A method for identifying log-likelihood ratio (LLR) values and for decoding a codeword using the identified LLR values is disclosed. The method comprises the following steps: the method includes programming codewords into the non-volatile memory device in response to receiving a host request write instruction, and performing background reading of at least one of the programmed codewords in a block of the non-volatile memory device at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage. The results of the background reads are stored and at least one background read is decoded to identify the codeword(s). The stored read results and the identified codeword(s) are used to identify a set of LLR values, and the process of performing background read, storage, decoding and identification is repeated to identify a set of LLR values for each block of the non-volatile memory device, and to identify an updated set of LLR values. The host-requested read is performed and decoded using LLR values from the updated set of LLR values corresponding to the block read in the host-requested read.

A non-volatile memory controller, comprising: write circuitry coupled to the plurality of non-volatile memory devices, the write circuitry configured to: the codewords are programmed into each non-volatile memory device in response to receiving a host request write instruction. The read circuit is configured to: background reading of at least one programmed codeword in a block of a non-volatile memory device is performed at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage. The decoder circuit is configured to: at least one background read is decoded to identify the codeword(s). The LLR circuit is configured to: the read result and the identified codeword(s) are used to identify a set of LLR values corresponding to a default threshold voltage. The non-volatile memory controller continues to perform background reads, decode at least one background read, and identify a set of LLR values to identify a set of LLR values for each block of the non-volatile memory device, and to identify an updated set of LLR values during the lifetime of the non-volatile memory system. The read circuit is configured to: performing a host requested read of the non-volatile memory device, and the decoder circuit is configured to: the result of the host requested read is decoded using the LLR values in the updated set of LLR values corresponding to the block read in the host requested read.

Disclosed is a nonvolatile memory system including: a plurality of non-volatile memory devices, a non-volatile memory controller coupled to the non-volatile memory devices, a write circuit, a read circuit, and a log-likelihood ratio (LLR) circuit. The write circuit is configured to: the non-volatile memory device is programmed to store user data in the non-volatile memory device in response to receiving a host request write instruction that includes the user data. The read circuit is configured to: background reading of the representative page is performed at a default threshold voltage within each threshold voltage region required to read the representative page of the group of pages, at one or more threshold voltage offsets less than the default threshold voltage within each threshold voltage region required to read the representative page, at one or more threshold voltage offsets greater than the default threshold voltage within each threshold voltage region required to read the representative page. The decoder circuit is configured to: results from some of the background reads of the representative page are decoded to identify codewords stored in the representative page. The LLR circuit is configured to: the read results and the identified codewords are used to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page. The read circuit is configured to: continuing to perform background reads and decode results from some background reads, and the LLR circuit is configured to: continuing to identify the set of LLR values to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page of each group of pages, and further configured to: the background reads continue to be performed and the updated set of LLR values is identified. The read circuit is configured to: performing a host requested read of the non-volatile memory device, and the decoder circuit is configured to: the result of the host requested read is decoded using LLR values from the updated set of LLR values corresponding to the group of pages of the page read in the host requested read.

The method and apparatus of the present invention allows error correction using soft information obtained during operation of the non-volatile memory system and does not require laboratory testing of sample NAND flash memory chips to generate LLR tables for different time periods during the lifetime of the non-volatile memory device. In addition, by performing LLR calculations on the actual NAND device being used, and by performing background tests as the NAND device ages, the methods and apparatus of the present invention provide LLR values that accurately indicate the probability of error over the life of the non-volatile memory system. This reduces the Bit Error Rate (BER) and extends the lifetime of the NAND flash memory chip. In addition, the number of read errors is reduced, resulting in reduced read latency.

Brief Description of Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate various embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a block diagram illustrating a non-volatile memory system according to an embodiment of the invention.

FIG. 2 is a diagram illustrating a non-volatile memory controller and a non-volatile memory device according to an embodiment of the invention and illustrating communication between the non-volatile memory controller and the non-volatile memory device.

FIG. 3 is a block diagram illustrating a logical organization of a memory according to an embodiment of the invention.

FIG. 4 is a diagram illustrating a NAND array in accordance with an embodiment of the invention.

Fig. 5 is a flow chart illustrating a method for calculating LLRs and for reading a non-volatile memory device and decoding read results according to an embodiment of the present invention.

Fig. 6A is a diagram illustrating a voltage distribution and LLR values of four regions calculating the voltage distribution according to an embodiment of the present invention.

Fig. 6B is a diagram illustrating a voltage distribution and LLR values of six regions calculating the voltage distribution according to an embodiment of the present invention.

Fig. 7 is a flowchart illustrating calculating LLRs for four regions of a voltage distribution according to an embodiment of the present invention.

Fig. 8 is a diagram illustrating portions of an LLR circuit according to an embodiment of the present invention.

Fig. 9A is a diagram illustrating voltage distributions and default threshold voltages of a TLC NAND device according to an embodiment of the present invention.

Fig. 9B is a diagram illustrating calculating LLRs for a TLC NAND device according to an embodiment of the present invention.

Fig. 9C is a diagram illustrating calculating LLRs for a TLC NAND device according to an embodiment of the present invention.

Fig. 10A is a diagram illustrating calculating LLRs for a TLC NAND device in which LLRs are calculated for six regions according to an embodiment of the present invention.

Fig. 10B is a diagram illustrating calculating LLRs for a TLC NAND device in which LLRs are calculated for six regions according to an embodiment of the present invention.

Fig. 10C is a diagram illustrating BRP of a calculated TLC NAND device, according to an embodiment of the invention.

Fig. 11 is a flow diagram illustrating a method of performing a background read upon the occurrence of a durability event, a reserve timer event, and a read disturb event at a shutdown block in accordance with an embodiment of the invention.

Fig. 12 is a flow diagram illustrating a method for performing background reference positioning and computing LLRs, and for reading results and decoding read results, according to an embodiment of the present invention.

Fig. 13 is a flow diagram illustrating a method for performing background reference positioning and computing LLRs, and for reading results and decoding read results, in accordance with an embodiment of the present invention, wherein background reads are performed upon the occurrence of an endurance event, a retention timer event, and a read disturb event at a shutdown block.

FIG. 14 is a flow chart illustrating a method for background reference positioning according to an embodiment of the present invention.

Fig. 15 is a diagram illustrating an exemplary endurance event, retention timer event, and read disturb event over time shown on the horizontal axis according to an embodiment of the present invention.

FIG. 16 is a diagram illustrating an exemplary background read in accordance with an embodiment of the present invention.

Fig. 17 is a diagram illustrating portions of an LLR circuit according to an embodiment of the present invention.

Detailed Description

A non-volatile memory system 1 is shown in fig. 1 to include a non-volatile memory controller 11, the non-volatile memory controller 11 being coupled to a plurality of non-volatile memory devices 20 for storing data. In the present embodiment, the nonvolatile memory device 20 is a NAND device, and the nonvolatile memory system 1 is a Solid State Drive (SSD) including one or more circuit boards to which the host connector receptacle 12, the nonvolatile memory controller 11, and the nonvolatile memory device 20 are attached. The non-volatile memory system 1 may also include one or more volatile memory devices 13, such as Dynamic Random Access Memory (DRAM), attached to the circuit board and the non-volatile memory controller 11.

The nonvolatile memory controller 11 is configured to: read and write instructions are received from the host computer through the host connector receptacle 12 of fig. 1 and program, erase and read operations are performed on the memory cells of the non-volatile memory device 20 to complete the instructions from the host computer. For example, upon receiving a write instruction from a host computer via the host connector receptacle 12, the memory controller 11 is operable to store data in the non-volatile memory system 1 by performing a program operation (and, if desired, an erase operation) on the one or more non-volatile memory devices 20, and upon receiving a read instruction, the non-volatile memory controller 11 is operable to read data from the non-volatile memory system 1 by performing a host-requested read operation on the one or more non-volatile memory devices 20. The term "host-requested reads" as used in this application includes only those reads that are performed in response to instructions received from an external device (e.g., received at host connector receptacle 12), and specifically includes read requests received from a host computer or other external computing device. The host-requested reads do not include background reads performed during background referencing operations or reads performed pursuant to housekeeping operations such as, but not limited to, garbage collection, wear leveling, and block reclamation.

Each non-volatile memory device 20 may be a packaged semiconductor die or "chip" that is coupled to the non-volatile memory controller 11 by conductive paths that couple instructions, data, and other information between each non-volatile memory device 20 and the non-volatile memory controller 11. In the embodiment shown in fig. 2, each nonvolatile memory device 20 includes a register 24, a microcontroller 25, and a memory array 26, and each nonvolatile memory device 20 is coupled to the nonvolatile memory controller 11 through a chip enable signal line (CE #), a command latch enable signal line (CLE), a read enable signal line (RE #), an address latch enable signal line (ALE), a write enable signal line (WE #), a read/busy signal line (R/B), and an input and output signal line (DQ). Upon receiving a write instruction from the host computer, the write circuit 2 is operable to encode the received data into a code word which is sent to the register 24 along with the corresponding program instruction. The microcontroller 25 is operable to execute the requested NAND write instruction and store the codeword in the memory array 26 by programming the cells of the memory array 26. In response to receiving a read instruction from the host computer, the read circuit 9 is operable to send a read instruction to the NAND 20. The microcontroller 25 reads the memory array 26 in response to the read instruction and outputs the read result at the register 24. The read result is sent to a decoder 8, which decoder 8 is operable to decode the read result to obtain the stored codeword.

Referring now to FIG. 3, each non-volatile memory device 20 includes NAND memory cells organized into blocks 22 and pages 23, where each block 22 is made up of NAND strings sharing the same word line group. Each logical page 23 is made up of cells belonging to the same word line. The number of logical pages 23 within a logical block 22 is typically a multiple of 16 (e.g., 64, 128). In the present embodiment, the logical page 23 is the smallest addressable unit for reading from and writing to the NAND memory, and the logical block 22 is the smallest erasable unit. However, it will be appreciated that in embodiments of the present invention, depending on the structure of the NAND array, it may be possible to program less than an entire page.

FIG. 4 shows an exemplary memory array 30 composed of NAND memory cells connected in series to form a NAND string. Each NAND string is isolated from the rest of the array by a select transistor, such as, for example, select transistor 31 and select transistor 32. A plurality of memory cells share a gate voltage (Vg) through a word line and the drain of one memory cell is the source of an adjacent memory cell. For example, memory cells 34-39 of FIG. 4 share word line 0(WL 0). Memory cells 34-39 may be single level cells each storing a single bit of information, or NAND devices storing 2 bits per cell, 3 bits per cell, or 4 bits per cell. The structure of the NAND array may be planar or 3D.

In the embodiment shown in fig. 1, the non-volatile memory controller 11 comprises a read circuit 9, the read circuit 9 being configured to perform a read of the non-volatile memory device 20. A standard READ instruction (e.g., a READ PAGE instruction), which may also be referred to herein as a hard READ instruction, performs a READ of a memory cell at a default threshold voltage within each threshold voltage region required to define a bit of the memory cell.

The threshold voltage shift read is performed by sending a threshold voltage shift read instruction to the NAND device 20 that includes one or more read offset values to be used by the NAND device 20 to perform the read. The read offset value (hereinafter may also be referred to simply as "offset value" or "offset") indicates the amount by which the threshold voltage used to perform the read will be offset from the corresponding default threshold voltage specified by the manufacturer of the NAND device 20. The term "default threshold voltage" as used in this application is the threshold voltage established by the manufacturer of the non-volatile memory device 20 for performing a conventional READ operation, such as a READ instruction or a READPAGE instruction. This is generally equivalent to the threshold voltage of a threshold voltage shift read at offset 0. For an MLC or TLC non-volatile memory device 20, there will be multiple default threshold voltages.

In the present embodiment, NAND device 20 is capable of performing a wide range of threshold voltage shift reads, including but not limited to reads specified by integer offset values such as-2, -1,0, +1, + 2. For multi-level cell (MLC) NAND devices and three-level cell (TLC) NAND devices, reading at more than one threshold voltage is required to identify the value of a particular bit. Thus, a threshold voltage shift read instruction for an MLC NAND or TLC NAND device 20 will include two or more read offset values, one for each threshold voltage region needed to identify the particular bit being read. In response to receiving a threshold voltage shift read instruction that includes a required read offset value, the NAND device 20 is operable to perform a read at a threshold voltage corresponding to the indicated read offset value to generate an output indicative of the read result.

An erased block of NAND 20 may be referred to as a "free block. When data is programmed into a block, the block is called an "open block" until all pages of the block have been programmed. Once all the pages of a block have been programmed, the block is referred to as a "closed block" until it is erased.

The non-volatile memory controller 11 includes a write circuit 2, a memory storage device 4, a state circuit 3 coupled to a read circuit 9, a Background Reference Positioning (BRP) circuit 6 coupled to the state circuit 3 and the read circuit 9, a decoder circuit 8 coupled to the read circuit 9, and a log-likelihood ratio (LLR) circuit 7. The LLR circuit 7 is coupled to the BRP circuit 6, the read circuit 9 and the memory storage 4, and is operable to calculate LLRs used by the decoder circuit 8 to decode a read of the non-volatile memory device 20. For clarity, the various couplings are not shown.

The status circuit 3 is configured to determine usage characteristics of the non-volatile memory device 20. The determined usage characteristics may be stored in the memory storage 4 of the non-volatile memory controller 11. Alternatively, the determined usage characteristics may be stored in one or more non-volatile memory devices 20 or in a separate volatile memory device 13. The term "usage characteristic" as used in the present invention is a value determined during use of the non-volatile memory device, which value indicates the historical usage of the non-volatile memory device up to a particular point in time, which may be, but is not limited to, the number of program and erase cycles or Bit Error Rate (BER) of a block or group of blocks of the non-volatile memory device 20.

The reading circuit 9 is configured to: background reading of at least one programmed codeword in a block of a non-volatile memory device is performed at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage. The decoder circuit 8 is configured to: at least one background read is decoded to identify at least one codeword. The LLR circuit 7 is configured to: the read result and the identified codeword(s) are used to identify a set of LLR values corresponding to a default threshold voltage. The reading circuit 9 is configured to: a host requested read of the non-volatile memory device is performed, and the decoder circuit 8 is configured to: the result of the host requested read is decoded using LLR values from the updated set of LLR values corresponding to the block read in the host requested read.

Fig. 5 illustrates a method 100 according to an embodiment of the invention. In response to a host requesting a write command, the codeword is programmed into the non-volatile memory device 20, as shown by steps 101-102. In the embodiment shown in FIG. 1, a write command including user data is received at host connector receptacle 12 from a host computer. In response to receiving the write instruction, the write circuit 2 is operable to issue a program instruction to the non-volatile memory device 20 to program a codeword comprising user data and ECC bits into the non-volatile memory device 20. Upon receiving the programming instructions and codewords at the non-volatile memory device 20, the microcontroller 25 is operable to store the codewords in the memory array 26 (e.g., as logical pages).

Multiple background reads of the codeword are performed (109). The term "background read" as used in the present invention is any read performed in such a way as not to interfere with host request operations currently pending at the non-volatile memory controller 11, and specifically includes reads performed in such a way as not to delay pending host request reads (e.g., those reads that do not affect latency), and specifically includes reads assigned a priority less than the priority assigned to the host request read (such that any pending host request read is given priority (e.g., the pending host request read is performed first)), and specifically includes reads performed when there are no pending host request reads. It is to be appreciated that host requested write operations and host requested erase operations may be stored by the non-volatile memory controller 11 and executed at a later time without impacting the latency of the SSD 1. Thus, in embodiments of the present invention, a "background read" is a read performed as follows: the execution of the host request read is not delayed regardless of a pending host request write operation or a pending host request erase operation unless the pending host request write operation or the pending host request erase operation is stored close to storage capacity.

In this embodiment, once a codeword for reading is identified, at step 109, a plurality of background reads are performed within each threshold voltage region required to read the codeword, including reads at a default threshold voltage, reads at a threshold voltage offset less than the default threshold voltage, and reads at a threshold voltage offset greater than the default threshold voltage. The results of the background read are then stored. Background reading is used to identify the programmed codeword, as shown by step 110. The code word may be identified by a background read of the decoding step 109.

Referring now to fig. 6A, a Single Level Cell (SLC) non-volatile memory device only requires a read in a single threshold voltage region 14, which extends between the center of the voltage distribution for 1 and the center of the voltage distribution for 0, to identify the value of a bit (whether the cell stores a 1 or a 0). The nonvolatile memory controller 11 may perform a READ at the default threshold voltage 15 by sending a READ command (e.g., READ PAGE) to the nonvolatile memory device 20 to be READ along with the address of the codeword to be READ. In one embodiment, the LLR circuit 7 is operable to communicate with a READ circuit 9, the READ circuit 9 generating and sending a READ PAGE (e.g., 00h-30h) instruction, receiving a READ result (which may be represented by variable R), and storing the READ result in a temporary storage device (e.g., in memory storage device 4, in volatile memory 13, or in register 92). Alternatively, a read at the default threshold voltage may be performed by using a threshold voltage shift read instruction (e.g., a SET FEATURES or Efh instruction) with a sub-signature indicator (e.g., P1) indicating a read retry and a voltage offset of 0. The read result is then sent to a decoder circuit 8, which decoder circuit 8 is operable to decode the read result to obtain the initially stored codeword. The decoded Codeword (CW) is then stored in a temporary storage (e.g., in memory storage 4, volatile memory 13, or in register 90).

In the embodiment shown in FIG. 6A, the one or more reads at threshold voltages less than the default threshold voltage are reads performed at offset-1 (shown as default threshold voltage 16). The reading may be performed by a read circuit 9, the read circuit 9 generating and sending a threshold voltage shift read instruction (e.g., a SET featurs or Efh instruction) with a sub-signature indicator (e.g., P1) indicating a read retry and a voltage offset of-1, receiving the read result R _ N, and storing the read result in a temporary storage (e.g., memory storage 4, volatile memory 13, or register 91).

In the embodiment shown in FIG. 6A, the one or more reads at threshold voltages greater than the default threshold voltage are reads performed at an offset of +1 (shown as default threshold voltage 17). The reading may be performed by a read circuit 9, the read circuit 9 generating and sending a threshold voltage shift read instruction (e.g., a SET featurs or Efh instruction) with a sub-signature indicator (e.g., P1) indicating a read retry and a voltage offset of +1, receiving the read result R _ P, and storing the read result in a temporary storage (e.g., in the memory storage 4, in the volatile memory 13, or in a register 93).

A set of (111) LLR values is identified for each default threshold voltage using the stored read results and the identified CW. The identified set of LLR values is then stored (112). In the example shown in FIG. 6A, the errors identified in reads 15-17 are used to identify the LLR for each region A, B, C and D centered at the default threshold voltage 15.

FIG. 7 illustrates a method 200 for performing steps 109-112 for the SLC NAND distribution shown in FIG. 6A. At step 109, the threshold voltage region 14 is read at the default threshold voltage 15 to obtain the read result R, the threshold voltage region 14 is read at the threshold voltage 16 to obtain the read result R _ N, and the threshold voltage region 14 is read at the threshold voltage 17 to obtain the read result R _ P. R is decoded (202) to obtain a stored codeword CW. While R is decoded to obtain CW, it is to be appreciated that R _ N or R _ P can alternatively be decoded to obtain CW. CW, R _ N, R and R _ P are stored (203). Region Z, which may be, for example, one of regions A, B, C and D shown in fig. 6A, is selected (204), and a logical operation for the selected region is performed (205). In this embodiment, the logical operation includes performing a numerator function to obtain a numerator bit value and performing a denominator function to obtain a denominator bit value. The number of 1's in the child bit value is counted (206) to obtain a child value NUM and the number of 1's in the parent bit value is counted (207) to obtain a parent value DEN. The two values are divided (208) to identify a result X, and the logarithm of the result X is computed as the LLR for the region. The process is repeated (as shown by step 211 and line 213) until LLR values have been calculated for each region.

The following is an example of calculating the LLR (LLR _ a) for region a using the formula:

this may be calculated using a logic function, where-indicates bitwise NOT (NOT), AND where & indicates bitwise AND (AND), AND where the numerator bit value is (— (CW) & R _ N) AND the denominator bit value is (CW & R _ N). The bit count having a value of 1 in the calculated molecular bit values (as shown in step 206) gives a value that can be represented by the logic NUM ═ count (— (CW) & R _ N). The bit count with a value of 1 in the calculated denominator bit values (as shown in step 207) gives a value that can be represented by the logic DEN-count (CW & R _ N). As shown by step 208, the count of step 206 is divided by the count of step 207. The logarithm of the division result of step 208 is calculated, as shown by step 209.

As shown by steps 210, 211, 213, Z is incremented and the process is repeated to calculate LLR _ B for region B using the following equation:

this can be calculated using a logistic function, where the numerator N ═ count (— (CW) & R & (R _ N)) and the denominator DEN ═ count (CW & R & (R _ N)).

The LLR LLR _ C for region C can be calculated using the following equation:

this can be calculated using a logistic function, where the numerator NUM is count (— (CW) & (R) & R _ P) and the denominator DEN is count (CW & (R) & R _ P).

As shown by steps 210, 211, 213, Z is incremented and the LLR _ D for region D may be calculated using the following equation:

this can be calculated using the logic functions NUM ═ count (— (CW) & — (R _ P)) and DEN ═ count (CW & — (R _ P)). In step 211, Z is 3, indicating that all LLR values have been calculated, and thus the process ends (212).

In one embodiment illustrated in fig. 8, memory storage 4 includes logic, shown as registers 90-93, for storing CW, R _ N, and R _ P. Registers 90-93 are coupled to LLR logic 94 for performing the logic operation of step 205 and to one or more counters 95 for counting the number of 1's in the output from the LLR logic operation performed by LLR logic 94. The counter 95 is coupled to the division and logarithm logic 96, the division and logarithm logic 96 being operable to perform steps 208-209 to obtain LLR values 97 that can be stored in the LLR table 10 of fig. 1.

The following is an exemplary calculation of LLR _ a, where reading at the default threshold voltage 15 yields the read result R, codeword CW, R _ N, and R _ P.

CW＝00010101011111000

R＝00110101111110000

R_N＝00110101111110110

R_P＝00110101100010000

In this example, the molecular bit value is (— (CW) & R _ N) ═ 00100000100000110 and the count NUM of 1 in the molecular bit value is 4. The denominator bit value (W & R _ N) 00010101011111000 and the count DEN of 1 in the denominator bit value 8, giving LLR _ a log (4/8).

In embodiments of the present invention, more than one codeword is read in step 109 of FIG. 5 and used to calculate the LLR in steps 110 and 111. In this embodiment, several exemplary pages of each page group are read, and the read results and a plurality of code words CW are identified and stored in step 109. After the read identification errors for each codeword, these errors are combined to calculate LLR values. In the above example using R _ N, R, R _ P to compute four LLR regions, a molecular bit value is computed for each region and a count of 1's in each molecular bit value is determined, and the counts of 1's for each representative page are summed to obtain a molecular error sum. Similarly, the denominator bit values are calculated for each region, and a count of 1's in each denominator bit value is determined, and the counts of 1's for each representative page are summed to obtain a denominator error sum. The resulting LLR expression will include a numerator value N and a denominator value DEN for each of the N pages being read. Thus, for the first page to be read, NUM will be calculated₁And DEN₁For the second exemplary page being read, NUM will be calculated₂And DEN₂And the process continues until all N pages have been read, giving NUM₁、NUM₂…NUM_NAnd DEN₁、DEN₂…DEN_N. The LLR for each region will be LLR ═ log₁₀(NUM₁+NUM₂…+NUM_N/DEN₁+DEN₂…+DEN_N). The greater the number of exemplary pages used to calculate the LLR for each page group, the greater the accuracy of the resulting LLR values. However, as the number of pages increases, the time required to perform steps 109-112 increases. It has been found that using three exemplary pages per page group (N-3) gives good results.

In embodiments of the present invention, a block is divided into logical pages, and a logical page is the minimum amount of data that can be programmed. In this embodiment, each codeword is a logical page or portion thereof. Thus, the set of LLR values used to decode each read for a page will be the set of LLR values for the block that includes the page being read. Specifically, step 109 will perform background reading of one or more representative pages of each block, and step 110 and 111 will identify a set of LLR values for each default threshold voltage region required to read a representative page of blocks.

In one exemplary embodiment where the SSD 1 includes 128 nonvolatile memory devices 20, each nonvolatile memory device 20 including 2048 blocks, the blocks may be assigned block numbers 0 through 262,143. In this embodiment, the LLR table 10 may include a block number and a set of LLR values corresponding to each block number, where the LLR values to be used for decoding are determined by indexing the LLR table with the block number of the page being decoded.

The steps of performing background reads 109 and storing the results, decoding at least one background read to identify codewords 110, and identifying a set of LLR values 111 continue to identify a set of LLR values for each block of the non-volatile memory device. The identified set of LLR values may be stored (112) in the LLR table 10 along with the corresponding block number. Thus, in embodiments where the SSD 1 includes 128 nonvolatile memory devices 20, each nonvolatile memory device 20 including 2048 blocks, the table includes 262,144 sets of LLR values and corresponding block number indices 0 through 262,143.

The process of step 109-. As each updated set of LLR values is identified, it is stored in the LLR table 10 by overwriting any previously stored corresponding set of LLR values. For example, when an updated set of LLR values is identified for a particular block, the previously determined set of LLR values for that block stored in LLR table 10 is overwritten by the updated set of LLR values. Thus, the LLR table 10 will always include the most recently determined set of LLR values for each block.

In one embodiment, steps 109 and 112 are performed only for closed blocks (when the block is closed). In another embodiment, step 109 and 112 are performed only for closed blocks and only upon the occurrence of one or more of a durability event, a reserve timer event, and a read disturb event. Thus, background reads are performed frequently enough to maintain an accurate set of LLR values for each block, but not so frequently as to adversely affect the latency of SSD 1.

In an embodiment of the present invention, when the SSD 1 is assembled and an operation is initiated on the SSD 1 for the first time, no LLR table is stored in the SSD 1. In this embodiment, the non-volatile memory controller 11 is operable to identify characteristics of each non-volatile memory device 20 to which the non-volatile memory controller 11 is coupled, and is operable to determine the number of blocks on each non-volatile memory device 20 in an automated manner (without any user input), and is operable to assign a unique number (block number) to each block. The process of step 109 and 112 is also performed in an automated manner (without user input) during the operation of the SSD 1 by the user of the SSD 1 after the assembly of the SSD 1 to create and update the single LLR table 10. In this embodiment, the values in the LLR table 10 are calculated after the assembly of the SSD 1, after the first initialization of the SSD 1, and the LLR table 10 is constructed as a whole after the first initialization of the SSD 1 (which may be after the SSD 1 has been shipped to the user of the SSD 1).

When no host request read is pending (103, 123), normal operation of the non-volatile memory device continues with step 109 performed in the background and 112 so as not to affect the latency of the non-volatile memory system 1. When a host request read instruction is received and the LLR has been calculated for the block to be read, a host request read is performed (105). The host-requested read may be performed using a threshold voltage shift read instruction at different offset values to obtain hard read results and soft information. The term "soft information" as used in this application is information that indicates the results of one or more reads at threshold voltages less than the default threshold voltage and one or more reads at threshold voltages greater than the default threshold voltage. In the present embodiment, step 105 is performed by the reading circuit 9. The result of the host requesting the read is decoded using LLR values from the updated set of LLR values corresponding to the block read in the host requesting the read (106). Thus, when the non-volatile memory device is an SLC device, each codeword is decoded using an LLR value from the set of LLR values corresponding to the default threshold voltage for performing the host requested read. In this embodiment, step 106 is performed by decoder circuit 8, which decoder circuit 8 will perform decoding using the most recently determined set of LLR values in LLR table 10 (i.e., the initial set of LLR values calculated for the block being read, or the most recently updated set of LLR values for the block being read).

During the early lifetime of SSD 1, reads may be needed for codewords for which LLRs may not have been computed (104, 107). In this case, a conventional READ instruction, such as a READ PAGE instruction (hard READ), is used to perform the READ and a default set of LLR values is used to perform the decoding. Since this is only needed during the early life of SSD 1, reading at the default threshold voltage is less likely to result in a read error, even when using inaccurate LLR values. It has been found that during this period, decoding is successful as long as LLR values close to 0 are not used. In one embodiment, decoding may be performed using any negative number from-6 to-15 for LLR regions to the left of the default threshold voltage, and any positive number from +6 to +15 for LLR regions to the right of the default threshold voltage. In one exemplary embodiment using 2 LLR regions, the default set of LLR values is LLR _ a-6 and LLR _ B +6, at step 108.

Alternatively, the read of step 107 may be performed using a threshold voltage shift read to obtain a hard read result and soft information. In an embodiment using 4 LLR regions, the default set of LLR values is LLR _ a-6, LLR _ B-6, LLR _ C +6, and LLR _ D +6, at step 108. In this embodiment, all host requested reads are performed using a threshold voltage shift read instruction. Thus, no dedicated logic is required to determine whether LLRs have been computed for the block of the page being read.

Thus, in an embodiment where the non-volatile memory device system 1 includes 128 SLC non-volatile memory devices, and 2048 blocks per non-volatile memory device, the system 1 would include 262,144(128x2048) sets of LLR values. In the embodiment of fig. 6A, each set of LLR values will contain four LLR values, requiring storage of 1,048,576(128x2048x4) LLR values (in the case where blocks are not grouped into block groups, as will be described subsequently).

The method 100 calculates a set of LLR values during the lifetime of each non-volatile memory device 20, the LLR values being specific to the non-volatile memory device itself, and the set of LLR values being continuously updated throughout the lifetime span of the non-volatile memory device 20. Thus, an accurate set of LLR values is always available for decoding. In addition, since the set of LLR values is calculated and repeatedly updated for each block and used to decode the codeword stored in that particular block, variations between the error characteristics of different blocks are taken into account over the lifetime of the non-volatile memory system, giving a non-correctable bit error rate (UBER) that is superior to that obtained using prior art methods. In addition, by calculating the LLR values during operation of the nonvolatile memory device 20 and after the nonvolatile memory controller 11 has been sold to a customer and integrated into the nonvolatile memory system 1, the need to test a test chip similar to the nonvolatile memory device 20 in a test laboratory to generate LLR tables for different periods of the lifetime of the nonvolatile memory device 20 is avoided, and the need to store pre-generated LLR tables for different periods of the lifetime of the SSD 1 on the nonvolatile memory system is avoided. Although the above embodiments calculate LLR values for only four regions, it should be appreciated that LLR values may be calculated for more regions. In the example shown in fig. 6B, LLR values are calculated for six regions (shown as regions a-F) centered at each default threshold voltage 15. In this embodiment, reads at two threshold voltages less than the hard read threshold voltage (shown as threshold voltages 18, 16, which may have read offset values of-2, -1) and at two threshold voltages greater than the default threshold voltage (shown as threshold voltages 17, 19, which may have read offset values of +1, +2) are used. Thus, in embodiments where the non-volatile memory system 1 includes 128 SLC non-volatile memory devices, and 2048 blocks per non-volatile memory device, each set of LLR values would contain six LLR values, requiring storage of 1,572,864(128x2048x6) LLR values (in the case where the blocks are not grouped into block groups, as will be described subsequently).

In one alternative embodiment, where a threshold voltage shift read instruction is used to perform all host-requested reads 105, 107 to obtain soft information, the LLR table 10 is automatically generated after initialization of the SSD 1, with all LLR values set to the same default set of LLR values. In an embodiment using 4 LLR regions, the default set of LLR values for each block is LLR _ a-6, LLR _ B-6, LLR _ C +6, and LLR _ D + 6. In an embodiment using 6 LLR regions, the default set of LLR values for each block is LLR _ a-6, LLR _ B-6, LLR _ C-6, LLR _ D +6, LLR _ E +6, and LLR _ F + 6. These initial LLR values are then updated during the lifetime of SSD 1 using method 100.

Multi-level cell (MLC) and Triple Level Cell (TLC) nonvolatile memory devices 20 require reading in more than one threshold voltage region to identify the value of a bit. When the non-volatile memory device 20 is an MLC or TLC device, background reads of a representative page of the block are performed at step 109 at a default threshold voltage within each threshold voltage region required to read the representative page, at one or more threshold voltage offsets less than the default threshold voltage within each threshold voltage region required to read the representative page, and at one or more threshold voltage offsets greater than the default threshold voltage within each threshold voltage region required to read the representative page. In this embodiment, the stored read results and the identified codeword(s) are used to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page, step 111. The process of step 109-. The host-requested read is performed using the most recently updated set of LLR values corresponding to the block read in the host-requested read (105).

In the exemplary embodiment shown in FIG. 9A, the non-volatile memory device 20 is a TLC NAND device that requires a read in each of the threshold voltage regions 1-7 to identify the value of the stored bit. The manufacturer-specified default threshold voltages for read threshold voltage regions 1-7 are shown as default threshold voltages 41-47. Fig. 9B-9C illustrate the method 100 being performed for an exemplary TLC NAND device 20, where the lower page bits are defined by reading at threshold voltage regions 1 and 5 (default threshold voltages 41 and 45), the upper page bits are defined by reading at threshold voltage regions 3 and 7 (default threshold voltages 43 and 47), and the middle page bits are defined by reading at threshold voltage regions 2, 4, and 6 ( default threshold voltages 42, 44, and 46).

9B-9C illustrate background reads of the lower page, where the reads are performed at one threshold voltage less than the default threshold voltage, at the default threshold voltage, and at one threshold voltage greater than the center threshold voltage to allow calculation of four LLR values (e.g., LLR values for regions A-D). Since the lower page read requires a read in threshold voltage regions 1 and 5, each threshold voltage shift read instruction for the lower page will include two threshold voltage shifts, and the threshold voltage shift read instruction may be represented as TVSR (V)_O1,V_O5) Wherein "V" is_O1"is a threshold voltage shift for reading region 1, and" V_O5"is the threshold voltage shift for the read region 5.

In this example, the default threshold voltage for region 1 and the default threshold voltage for region 5 are the default threshold voltages for regions 1 and 5 corresponding to a threshold voltage offset of 0. Threshold voltage region 5 is first selected to calculate the LLR values. In the example shown in FIG. 9B, at step 109, three background reads are performed: a first background read TVSR (0, -1) at offset 0 of region 1 and offset-1 of region 5 (shown as threshold voltages 41, 50) to obtain read result R _5N, a second background read TVSR (0,0) at offset 0 of region 1 and offset 0 of region 5 (shown as threshold voltages 41, 45) to obtain read result R _5, and a third background read TVSR (0, +1) at offset 0 of region 1 and offset +1 of region 5 (shown as threshold voltages 41, 51) to obtain read result R _ 5P. When each of the read results R _5N, R _5, R _5P is received at the nonvolatile memory controller 11, these read results are stored in a temporary storage device. One of the read results R _5N, R _5, R _5P is sent to decoder circuit 8 for decoding to obtain the codeword CW. Step 110-112 is performed to obtain a set of LLR values for threshold voltage region 5, which may be represented by the form LLR _5A, LLR _5B, LLR _5C, LLR _ 5D.

Referring now to fig. 9C, the process is repeated to obtain LLRs for threshold voltage region 1 while maintaining the value of threshold voltage region 5 at the default threshold voltage. Three exemplary page reads are performed: a first background read TVSR (-1,0) at offset-1 of region 1 and offset 0 of region 5 (shown as threshold voltages 55, 45) to obtain read result R _1N, a second background read TVSR (0,0) at offset 0 of region 1 and offset 0 of region 5 (shown as threshold voltages 41, 45) to obtain read result R _1, and a third background read TVSR (+1,0) at offset +1 of region 1 and offset 0 of region 5 (shown as threshold voltages 56, 45) to obtain read result R _ 1P. When each of the read results R _1N, R _1, R _1P is received at the nonvolatile memory controller 11, these read results are stored in temporary storage. Step 110-112 is performed using the codeword CW obtained in calculating the LLR values of region 5 to obtain a set of LLR values for threshold voltage region 1, which may be represented by the form LLR _1A, LLR _1B, LLR _1C, LLR _ 1D.

The following is an exemplary equation that may be used to calculate the 4-region LLR values for the lower page of the TLC NAND for region 1:

LLR _1A ═ log [ bit count ═ (not (CW) AND BRP _ N AND on-coupled bit) ]1/bit count ═ 1 in (CW AND BRP _ N AND on-coupled bit) ]

1/bit count in LLR _1B ═ log [ bit count ═ (NOT (CW) AND BRP AND NOT (BRP _ N) AND on-coupled bit) ] (1 in CW AND BRP AND NOT (BRP _ N) AND on-coupled bit) ]

1/bit count in LLR _1C ═ log [ bit count ═ (NOT (CW) AND NOT (BRP) AND BRP _ P AND on-coupled bit) ] (1 in CW AND NOT (BRP) AND BRP _ P AND on-coupled bit) ]

1/bit count in LLR _1D ═ log [ bit count ═ (NOT (CW) AND NOT (BRP _ P) AND on-coupling bit) ] (1 in CW AND NOT (BRP _ P) AND on-coupling bit) ]

The following is an exemplary equation that may be used to calculate the LLR for the lower page of the TLC NAND for region 5:

the 1/bit count in LLR _5A ═ log [ bit count ═ (NOT (CW)) AND BRP _ N AND NOT (upper coupling bit)) ] (1 in CW AND BRP _ N AND NOT (upper coupling bit)) ]

LLR _5B ═ log [ bit count ═ (NOT (CW)) AND BRP AND NOT (BRP _ N) AND NOT (upper coupling bit) ], 1/bit count ═ 1 in CW AND BRP AND NOT (BRP _ N) AND NOT (upper coupling bit) ] ]

The 1/bit count in LLR _5C ═ log [ bit count ═ (NOT (CW)) AND NOT (BRP) AND BRP _ P AND NOT (upper coupling bit)) ] (1 in CW AND NOT (BRP) AND BRP _ P AND NOT (upper coupling bit)) ]

The 1/bit count in LLR _5D ═ log [ bit count ═ (NOT (CW)) AND NOT (BRP _ P) AND NOT (upper coupling bit) ] (1 in CW AND NOT (BRP _ P) AND NOT (upper coupling bit) ])

In the above example, a single set of LLR values is obtained and updated for each block and stored along with the block number of the exemplary page used to calculate the LLR values.

While using the method 100 to maintain an updated set of LLR values for each block provides superior UBER compared to conventional methods, it has been found that there is often a change in BER within a block, with certain pages of each block having common BER characteristics. Thus, in embodiments of the present invention, the pages of each block are divided into groups of pages, where the pages within each group of pages have similar BER characteristics.

In one embodiment, each block 22 of each non-volatile memory device 20 is divided into groups of pages that include pages having similar error characteristics. The LLR table 10 may include an index identifying each page group, which may be, for example, a number from 1 to 3,145,728(128x2048x12), that will identify both page groups and blocks and the non-volatile memory devices 20 (since all page groups within all non-volatile memory devices 20 of SSD 1 will have unique indices). The page group index is stored in the LLR table 10 along with the corresponding LLR value for each voltage region required to read a page of the page group. When the non-volatile memory device 20 is an SLC device, step 109 comprises: background reading of a representative page of a group of pages is performed at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage. At step 110, one or more codewords are identified (110), and step 111 is performed by using the read results and the codeword(s) identified at step 110 to identify a set of LLR values for each group of pages. At step 106, the results of the host request read are decoded using LLR values from the updated set of LLR values corresponding to the page group of the page being read. In this embodiment, the method 100 may include: an LLR table 10 is generated and each of the identified sets of LLR values is stored (112) in LLR table 10 along with an index identifying the corresponding group of pages. Each time an updated set of LLR values is identified at step 111, the updated set of LLR values is stored in the LLR table 10 by overwriting the corresponding set of LLR values previously stored in the LLR table. Thus, the decoding of step 106 may include indexing the LLR table using index values corresponding to the page population of the page being read.

When the non-volatile memory device 20 is an MLC or TLC device, groups of pages may be identified by dividing the wordlines into topological types (upper, middle, and lower pages) and into categories according to their topological behavior (i.e., the relationship of error characteristics to physical location within the block). In the present embodiment, the topological behavior is classified by assigning different word lines to different classes. The categories may be determined in a flash laboratory during a characterization phase of studying the relationship of topological locations to error behavior. In one illustrative embodiment, the word lines are grouped into the following categories:

firstly, the method comprises the following steps: word line 0 through word line 24.

Secondly, the method comprises the following steps: word line 25 through word line 84.

Thirdly, the method comprises the following steps: word line 85 through word line 119.

Fourthly: word line 120 through word line 127.

It can be seen that different groups of word lines do not necessarily include the same number of word lines or the same number of memory cells. In this embodiment, the word line groups are determined by analyzing characteristics of the NAND devices in a laboratory to identify groupings with similar error behavior. In the present illustrative embodiment, the non-volatile memory device 20 is a TLC NAND device in which each memory cell may store three different bits of information. Since there are three page types in TLC NAND devices, this gives the following page groups:

page group 1: the upper page of wordlines 0-24.

Page group 2: middle page of wordlines 0-24.

Page group 3: the lower page of wordlines 0-24.

Page group 4: the upper page of wordlines 25-84.

Page group 5: middle page of wordlines 25-84.

Page group 6: the lower page of wordlines 25-84.

Page group 7: the upper page of wordlines 85-119.

Page group 8: middle page of wordlines 85-119.

Page group 9: the lower page of wordlines 85-119.

Page group 10: word line 120 minus the upper page of 127.

Page group 11: word line 120 minus the middle page of 127.

Page group 12: word line 120 minus the lower page of 127.

Thus, in an embodiment in which the non-volatile memory device system 1 includes 128 non-volatile memory devices, and 2048 blocks per non-volatile memory device, the system 1 would include 3,145,728(128x2048x12) page groups (in the case where the blocks are not grouped into block groups, as will be described later).

When the non-volatile memory device 20 is an MLC or TLC device, background reads of a representative page of the group of pages are performed at step 109 at a default threshold voltage within each threshold voltage region required to read the representative page, at one or more threshold voltage offsets less than the default threshold voltage within each threshold voltage region required to read the representative page, and at one or more threshold voltage offsets greater than the default threshold voltage within each threshold voltage region required to read the representative page. In this embodiment, the stored read results and the identified codeword(s) are used to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page, step 111. The process of step 109-. The host-requested read is performed using the most recently updated set of LLR values corresponding to the page group of the page read in the host-requested read (105).

In one embodiment, for MLC and TLC non-volatile memory devices, LLR values for each voltage region required to read a page of a group of pages are concatenated and stored in an LLR table such that each concatenated set of LLR values is associated with a single page group index. At step 106, each codeword is decoded using LLR values from the set of LLR values corresponding to the group of pages of the page being read. For example, if a page within the first page group of the second block is being read and decoded (which requires a read in threshold voltage regions 1 and 5) (the lower page), the index of the first page group of the block is identified and used to index the LLR table (e.g., index 2049) to obtain a set of LLR values LLR _1A, LLR _1B, LLR _1C, LLR _1D, LLR _5A, LLR _5B, LLR _5C, LLR _ 5D.

In the above example, 4 LLR regions are calculated for each threshold voltage region. When 6 voltage regions are used to calculate the LLR, as shown in FIGS. 10A-10B, the following additional reads are required: TVSR (0, -2) (shown as reference voltages 41, 49), TVSR (0, +2) (shown as reference voltages 41, 52), TVSR (-2,0) (shown as reference voltages 54, 45), and TVSR (+2,0) (shown as reference voltages 57, 45). The LLR table will include six LLR values for each threshold voltage region required to read each page of the group of pages, which are concatenated and associated with the corresponding page group index. For a group of pages that includes only the lower page, the LLR table of the exemplary embodiment shown in FIGS. 10A-10B would include a set of LLR values for region 1 (LLR _1A, LLR _1B, LLR _1C, LLR _1D, LLR _1E, LLR _1F) and a set of LLR values for region 5 (LLR _5A, LLR _5B, LLR _5C, LLR _5D, LLR _5E, LLR _ 5F).

In an alternative embodiment, in addition to grouping pages, blocks may also be grouped to reduce the number of page groups that need to be managed. For example, the blocks of each non-volatile memory device may be divided into 32 block groups that may correspond to the channels of the non-volatile memory system 1, thereby reducing the number of page groups of each non-volatile memory device 20 to 768 and reducing the number of page groups in the non-volatile memory system 1 to 98,304. In fig. 11, a method 300 is illustrated, the method 300 including identifying a page group for each block (301). The nonvolatile memory controller 11 may identify the page groups by querying the nonvolatile memory devices 20 to determine the type of the nonvolatile memory devices 20 and assigning the page groups based on error characteristics of the pages of the nonvolatile memory devices 20. The number of program and erase cycles is counted 302. In the present embodiment, the status circuit 3 is operable to count the number of program and erase (P/E) cycles per block of each non-volatile memory device 20. The number of reads per block of each non-volatile memory device 20 is counted (306). In the embodiment shown in fig. 1, status circuit 3 is operable to determine the number of READs per BLOCK (BLOCK READ COUNT) and store the number of READs per BLOCK in memory storage 4. In this embodiment, when a block is open (305, 306) and when a block is closed (318, 306), each time a page of each block is read, the number of reads of the block is incremented, and the block read counter is not reset (320) until the block is erased.

When a block is open, the time that the block is open is determined, and if the time that the block is open exceeds a predetermined threshold (e.g., 1 hour), the open block is closed to ensure that the block does not remain open too long. A block may be closed by programming all unprogrammed pages of an open block with dummy data. Further, in embodiments of the present invention, if the block read count exceeds a predetermined open block read count threshold (e.g., 150,000 reads), the block is sent for reclamation and copied and erased to prevent read errors in the open block.

When the block is closed 313, the block retention timer starts 314. In the embodiment shown in FIG. 1, the status circuit 3 includes a block retention timer that begins timing when each block 22 of each non-volatile memory device 20 is turned off. The block retention time for each block 22 indicates the time each closed block has remained closed and will not stop or be reset until the block becomes free 320 (such as when the block is erased).

The LLR operations are performed upon one or more of the endurance event 315, the reserve timer event 316, and the read disturb event 317 occurring at the shutdown block, as shown by steps 309 and 312. In the embodiment shown in fig. 1, the LLR circuit 7 is configured to: determining when a durability event occurs at step 315 by determining whether the block P/E count exceeds a durability threshold, and is configured to: it is determined whether a hold timer event 316 has occurred by determining whether the block hold time exceeds a hold time threshold. When the block read count exceeds the block read threshold, a read disturb event is determined to have occurred 317. In one embodiment, the endurance threshold, retention time threshold, and block read threshold are user programmable so that they can be changed to accommodate the characteristics of different types of NAND devices 20.

Once the page is identified to be read, background reads of representative pages of each group of pages of the closed block are performed by the read circuitry 6 at one or more default threshold voltages, at one or more threshold voltage offsets less than each default threshold voltage, and at one or more threshold voltage offsets greater than each default threshold voltage for the MLC and TLC non-volatile memory devices 20. The code words in the representative page are identified (310), the decoder circuit 8 being configured to: one of the reads of the representative page for each group of pages is decoded to identify at least one codeword in each group of pages, and the LLR circuit 7 is configured to: at least one updated set of LLR values for each group of pages is identified using the read results and the identified codeword(s) in each group of pages (311), and the calculated set of LLR values is stored (312).

As long as the block is closed, the background LLR operation 309-. When the block becomes free 320 (such as when the block is erased), background LLR operations 309 and 312 are no longer performed 312 (as shown by line 322) until the block is closed again 313. The host requested read 318 is performed by read circuitry 9, and decoder circuitry 8 decodes (308) the result of each host requested read using LLR values from the updated set of updated LLR values corresponding to the page group of the page read in the host requested read.

In this embodiment, a single set of LLR values is calculated for each threshold voltage region required to read a page of a group of pages, and the single set of LLR values is updated during the lifetime of SSD 1 by overwriting the LLR values previously stored for that particular group of pages when the updated LLR values are calculated. This may be a single LLR table 10 that is repeatedly updated during the lifetime of the SSD 1. For example, the single LLR table 10 of method 100 may include, for each block of SSD 1, a block index and a single concatenated set of LLR values that includes all sets of LLR values needed to decode the page of the corresponding block. The single LLR table 10 of method 300 includes, for each page group of SSD 1, a page group index and a single concatenated set of LLR values that includes all sets of LLR values needed to decode the page of the corresponding page group. For embodiments using block groups and page groups, a single LLR table 10 will include, for a single page group, a page group index and a single concatenated set of LLR values that includes all sets of LLR values needed to decode the page of the corresponding page group. The method and apparatus of the present invention do not store sets of LLR values for different time instances in the lifetime of a non-volatile memory device as required in prior art systems. Thus, the methods and apparatus of the present invention require less storage space than prior art SSDs that store multiple sets of LLR values for different times in the SSD's lifetime.

In an alternative embodiment where all host-requested reads ( steps 105, 107, 307) are performed using a threshold voltage shift read instruction to obtain soft information (or any other type of read instruction that provides soft information), after assembly of the SSD 1, and upon initialization of the non-volatile memory controller 11, an LLR table is automatically generated (without user input) by querying the non-volatile memory device 20 to identify characteristics of the non-volatile memory device 20 to generate and store a unique page group index for each page group and a default set of LLR values for the page group in the LLR table. In an embodiment using 4 LLR regions, the default set of LLR values for each page group is LLR _ a-6, LLR _ B-6, LLR _ C +6, and LLR _ D +6, where all page groups include the same default set of values when the table is initially generated. In an embodiment using 6 LLR regions, the default set of LLR values for each page group is LLR _ a ═ 6, LLR _ B ═ 6, LLR _ C ═ 6, LLR _ D ═ 6, LLR _ E ═ 6, and LLR _ F ═ 6. In this embodiment, the default set of LLR values is replaced with updated LLR values when generating new LLR values.

In the present embodiment, the host request read of steps 105, 107 and 307 is performed using a threshold voltage shift read instruction. However, it will be appreciated that some non-volatile memory devices 20 may be capable of performing soft reads using other types of instructions. In these embodiments, soft read instructions for the non-volatile memory device 20 of the characteristic type of SSD 1 may be used to generate read output and soft information to be used in the decoding process.

12-16 illustrate embodiments in which background reads are performed and used to calculate LLRs and to identify optimal threshold voltages to be used to perform a host-requested read. Referring now to fig. 12, background reads of the codeword are performed (411) at a plurality of different offsets from each of the default threshold voltages required to perform the background reads, and the read results are stored (412). The codeword is identified (413) and in the embodiment shown in fig. 1, the BRP circuit 6 is configured to: the results of the background read are used to identify the offset that yields the smallest total number of errors for each default threshold voltage. This may include: the error in each background read is identified by decoding the results of each read of step 411 by ECC. In one embodiment, the BRP circuit 6 is operable to receive the result of each read of step 411, store the read result, and is operable to couple the read result to the decoder circuit 8. Decoder circuit 8 is then operable to decode the results of each read from step 411 to obtain a codeword and a number of errors in the read. The codeword identified in step 413 is then stored in a temporary storage (e.g., in memory storage 4 or DRAM 13 or in register 90) along with the read results at the different offsets.

At least one updated set of offsets is identified (414) for each block (or each group of pages) of each non-volatile memory device 20 using the error identified in each read. This may be accomplished by summing the errors for each read at an offset from the threshold voltage to obtain an error sum, and determining the error sum with the smallest number of errors for each threshold voltage. The updated offset values in each updated offset set are then identified as offset values equal to the sum of errors with the smallest number of errors. Since the updated offset values are identified using background reads using a process that may be referred to as a "reference positioning process," the updated offset values may also be referred to hereinafter as "background reference positioning offset values" or "BRP offset values," and the updated offset set may be referred to hereinafter as a "background reference positioning offset set" or "BRP offset set. In the present embodiment, step 414 is performed by the BRP circuit 6.

The stored read results from step 412 and the codeword identified at step 413 are used to identify (416) a set of LLR values for each BRP offset value in the set of BRP offsets for each block (or group of pages) of each non-volatile memory device 20. In this embodiment, step 416 is performed by LLR circuit 7 shown in fig. 1 using the methods discussed in fig. 1-11. However, rather than the LLR distribution being centered at the default threshold voltage, the LLR distribution is centered at the BRP offset value (which would be the threshold voltage used to perform the reads of steps 405 and 407). In the exemplary embodiment shown in fig. 17, the LLR circuit 7 is shown in which the register 92 is not loaded with the read result at the default threshold voltage, but is loaded with the read result at the BRP offset value. Similarly, register 91 is loaded with the result of a read at an offset value (BRP _ N) less than the BRP offset value (which may be a read at BRP offset value-1), and register 93 is loaded with the result of a read at an offset value (BRP _ P) greater than the BRP offset value (which may be a read at BRP offset value + 1). This results in a set of LLR values with a distribution centered at the offset that yields the smallest total number of errors.

When no host request read is pending (as shown by step 403), normal operation of the non-volatile memory device continues with steps 411-416 being performed in the background so as not to affect the latency of the non-volatile memory system 1. When a host request read instruction is received and the LLRs have been calculated for the block (or group of pages) to be read, the host request read is performed using a threshold voltage shift read instruction at the identified offset corresponding to the block (or group of pages) of codewords being read that yields the minimum total number of errors. The host-requested read may be performed using a threshold voltage shift read instruction at an offset value equal to each BRP offset value in the set of BRP offsets corresponding to the block (or group of pages) being read, and at a soft information offset value centered on the BRP offset value (e.g., read at BRP offset-1, at BRP offset 0, and at BRP offset + 1). In this embodiment, step 405 is performed by the read circuit 9.

The codeword is decoded (406) using LLR values from the set of LLR values calculated in step 416. Thus, each codeword is decoded using LLR values from the set of LLR values corresponding to the BRP offset used to perform the host requested read. In this embodiment, step 406 is performed by decoder circuit 8. During the early lifetime of SSD 1, reads may be required for codewords for which LLRs may not have been calculated (404, 407). In this case, a conventional READ instruction, such as a READ PAGE instruction (hard READ), is used to perform the READ and a default set of LLR values is used to perform the decoding. Alternatively, a read is performed using a threshold voltage shift read instruction centered at a BRP offset value to obtain a read result and soft information at the BRP offset value. Since this is only needed during the early life of SSD 1, reading at the default threshold voltage is less likely to result in a read error, even when using inaccurate LLR values. It has been found that during this period, decoding is successful as long as LLR values close to 0 are not used. In one embodiment, decoding may be performed using any negative number from-6 to-15 for LLR regions to the left of the BRP, and any positive number from +6 to +15 for LLR regions to the right of the BRP. In one exemplary embodiment, the default set of LLR values is LLR _ a-6, LLR _ B-6, LLR _ C +6, and LLR _ D +6, at step 408.

In embodiments using groups of pages, the BRP circuit 6 performs background reading of the codeword at an offset from the threshold voltage required to read the codeword to identify the offset that produces the smallest total number of errors, and is configured to: the BRP offset value is set equal to the corresponding offset that yields the minimum total number of errors to identify a single BRP offset for each group of pages and a single set of LLR values for each group of pages when the non-volatile memory device 20 is an SLC device. When the non-volatile memory device 20 is an MLC or TLC non-volatile memory device, there will be more than one BRP offset for each page group at step 414, and step 416 will identify more than one corresponding set of LLR values, which may be concatenated and stored as a combined set of LLR values. Thus, each set of combined LLR values will include all LLR values needed to decode an MLC or TLC codeword. In the embodiment shown in fig. 1, the LLR circuit 7 is configured to: the set of LLR values corresponding to each BRP offset value is identified using errors identified in background reads performed at BRP offset values, errors identified in background reads performed at offsets less than the corresponding BRP offset values, and errors identified in background reads performed at offsets greater than the corresponding BRP offset values.

When no host request read is pending, normal operation of the non-volatile memory device continues with step 411-. When one or more host request read instructions are received at the host connector receptacle 12, the host request read of a codeword stored in the non-volatile memory device 20 is performed using a threshold voltage shift read instruction at an offset value equal to the BRP offset value(s) in the BRP offset set corresponding to the block (or group of pages) being read. In one embodiment, the BRP circuit 6 is configured to: storing each identified offset that yields the smallest total number of errors in the memory storage 4 as a BRP offset value in a BRP table that includes each identified BRP offset value and a corresponding index value (e.g., block number or page group number), and the read circuit 9 is configured to: the BRP offset value to be used in a host request read is identified by indexing the BRP table using an index value corresponding to the block (or group of pages) of the page being read. In one embodiment, step 411-417 is repeated to store the BRP offset value for each block (or group of pages) of the non-volatile memory device 20, and is further repeated to identify an updated BRP offset value. Each time an updated BRP offset value is identified, it may be stored in the BRP table by overwriting any previously saved BRP offset value for the corresponding block (or group of pages). When the non-volatile memory device is an MLC or SLC device, step 411-417 is repeated to store more than one BRP offset value (stored as a BRP offset set) for each block (or group of pages) of the non-volatile memory device 20, and is further repeated to identify updated offset values.

The codeword is decoded (406) using LLR values from the set of LLR values calculated in step 416. Each codeword may be decoded using LLR values from the set of LLR values corresponding to the block of the page being read. In one embodiment, the LLR circuit 7 is configured to: storing a single LLR table 10 in the memory storage 4, the LLR table 10 comprising each of the identified sets of LLR values and a corresponding index value, and the decoder circuit 6 is configured to: the LLR values to be used in a host request read are identified by indexing the LLR table with index values corresponding to the block (or group of pages) of the page being read.

In embodiments of the present invention, step 411-417 of method 400 is performed only for closed blocks, when a particular block is closed, to incrementally update the BRP offset value and LLR value during the lifetime of SSD 1. Step 411-417 may be performed upon the occurrence of a particular event, such as upon the occurrence of a certain period of time or a number of program and erase cycles. In one embodiment, step 411-. Thus, the BRP offset values and LLR values are updated frequently enough to maintain an accurate set of BRP offset values and an accurate set of LLR values, but not so frequently as to adversely affect the latency of SSD 1. In one embodiment illustrated in fig. 13, a method 500 of using page groups in conjunction with BRP calculations 514 and LLR calculations 516 is illustrated. In this embodiment, the steps 301, 313, 320 are performed in the same manner as discussed in the method 300. In one embodiment, the BRP circuit 6 is configured to: it is determined when a durability event 315, a retention timer event 316, or a read disturb event 517 occurs.

When a read request is received from the host (305, 308), the host requested read is performed (507) using a threshold voltage shift read instruction and using an updated set of read offset values corresponding to a page group of the page being read. The read is decoded (508) using LLR values corresponding to the threshold voltage regions and the page group of the page being read. When no LLR has been calculated for the page group of the page being read, a default set of LLR values may be used in the same manner as discussed in method 400.

Background reading of the representative page of each group of pages of the closed block is performed (511) at an offset within each threshold voltage region required to read the representative page of the closed block. Errors in background reads of the representative page are identified and a BRP offset value is identified (514) to identify an updated set of BRP offset values for each group of pages of the closed block. In the SLC case, a single set of LLR values is identified at step 516 since each set of updated BRP offset values will include a single BRP offset value. As long as the block is closed, step 511 + 517 continues to be performed (as shown by line 323) upon endurance, retention timer, and read disturb events to incrementally identify BRP offset values and LLR value sets until BRP offset values and LLR value sets have been identified for all page groups, and step 511 + 517 continues during the operational lifetime of SSD 1 to identify updated BRP offset values and updated LLR value sets. When the block becomes free 319, 323, such as when the block is erased, step 511 and 517 are no longer performed as shown by line 322 until the block is closed again 313.

Fig. 14 illustrates an exemplary background reference positioning operation 600 in accordance with an embodiment of the present invention. The number of representative pages to be used in each background read step is determined (601). The greater the number of pages tested, the greater the accuracy. However, more pages means that each background referencing operation takes more time. Thus, determining the number of representative pages is a trade-off between accuracy and time. In the present embodiment, five representative pages are selected from each page group.

The offset from the threshold voltage required to read the representative page is set 602 to the offset determined in the previous background referencing operation. All threshold voltage offsets are set to zero if no previous background reference positioning operations have been performed. One of the threshold voltages required to read the representative page is then identified for updating 603. In one embodiment, the page to be updated is selected by updating the pages in a predetermined order, where the page to be updated is the next page in the predetermined order (e.g., starting with the representative page having the lowest page number and updating the next lowest page number at subsequent step 603). A background read of the representative page is performed (604) using a threshold voltage shift read instruction at an offset from the identified threshold voltage. In one embodiment, the BRP circuit 6 is operable to perform step 601 and 603 and is operable to perform step 604 by sending a background read instruction to the read circuit 9, the read circuit 9 being operable to send a threshold voltage shift read instruction to the NAND device 20 being read.

An error in the reading of step 604 is identified (605). The total number of errors in each page is counted (606) to obtain a sum of errors indicating the total number of errors in the page. In the embodiment shown in fig. 1, the result of each read operation is received at the read circuit 9 and sent to the decoder 8, the decoder 8 being operable to decode the read result to identify the stored codeword. The identified codeword is compared to the read results by performing one or more logical operations at the BRP circuit 6 to identify the total number of errors in each read.

This process is repeated (608, 616) and the offset values are changed (607) for all representative pages, and the process continues (609, 617) until all representative pages have been read at all offset values for the threshold voltages identified in step 603 (with other threshold voltage offsets remaining at the values determined in step 602 until selected in step 603). After all representative pages have been read at all offset values, the threshold voltage offset that produces the smallest number of errors is determined (610). In one embodiment, step 610 includes: an error sum is determined by summing (606) the errors for each read at the offset voltage, and a threshold voltage offset corresponding to the error sum determined to have the smallest number of errors is identified. The updated threshold voltage offset is stored (611) as an updated BRP offset value for the identified threshold voltage. After the BRP offset value has been updated for the selected threshold voltage, the process is repeated in subsequent reads 604 of the background reference positioning operation 600 at a different identified threshold voltage (603) and using the updated BRP offset stored at step 611 (instead of the corresponding threshold voltage offset from step 602) (618) until all threshold voltages have been updated (612) and the process ends (613). In the present embodiment, the BRP circuit 6 is operable to perform steps 607-612.

In embodiments of the present invention, the BRP circuit 6 and/or LLR circuit 7 are operable to perform the background read of steps 109, 201, 511 and 604 by sending a read instruction to the read circuit 9, the read circuit 9 being operable, upon receipt of the background read instruction, to perform the background read by assigning a lower priority to the background read instruction than to a read instruction generated in response to a read request from the host computing device. In another embodiment, the fetch circuitry 9 is operable to assign a priority value to the read instructions including a high priority value, a medium priority value, and a low priority value, and is operable to assign a high priority to the read instructions generated in response to the read request from the host computing device, and is further operable to prioritize between the background read instructions executed at step 511 and the read instructions for the housekeeping operation by assigning a medium priority value or a low priority value to particular ones of the read instructions. In the exemplary embodiment shown in fig. 10A, 10B, where the TLC nonvolatile memory device 20 is read at step 604, the threshold voltage shift read is performed at read offset values of-2, -1,0, +1, and + 2. Alternatively, more threshold voltage reads may be performed at each step 604.

In this example, the group of pages read at step 604 (identified as exemplary page group 501) is a lower page group that includes only the lower page. Thus, the set of threshold voltages required to read each page in the background read 604 will be the lower page threshold voltages in regions 1 and 5. Thus, each threshold voltage shift read instruction for a lower page will include two threshold voltage offsets, and the threshold voltage shift read instruction may be represented as a BRP_Reading(V_O1,V_O5) Wherein "V" is_O1"is a threshold voltage shift for reading region 1, and" V_O5"is the threshold voltage shift for the read region 5.

In this example, both the threshold voltage offset for region 1 and the threshold voltage offset for region 5 are set to 0 at step 602 based on the updated threshold voltage offset calculated in the previous background reference positioning operation 600. The threshold voltage 45 of region 5 is first selected for updating at step 603. In the example shown in FIG. 10A, at step 404, offset 0 at region 1 and offset-2 at region 5 (shown as reference potential)41, 49) is pressed) to perform a first Background Read (BRP)_Reading(0, -2)) to obtain a first codeword, which is decoded to determine the number of errors in the reading of the page (605), and the number of errors in the reading is summed (606) to obtain a voltage offset error sum S_V5-1. Performing a background read BRP of a second page_Reading(0, -2) (604) to define a second codeword, the second codeword being decoded to determine a number of errors in the reading of the page (as shown in step 605), and the number of errors being summed (606) to obtain a voltage offset error and S, including errors from the reading of the first and second representative pages_V5-1. Performing a background read BRP of a third page_Reading(0, -2) (604) to define a third codeword, which is decoded to determine a number of errors in the reading of the page (as shown in step 605), and the number of errors is summed (606) to obtain a voltage offset error and S including errors from the reading of the first, second, and third representative pages_V5-1. Performing a background read BRP of a fourth page_Reading(0, -2) to define a fourth codeword that is decoded to determine the number of errors in the reading of the page (as shown in step 605), and the number of errors is summed (606) to obtain a voltage offset error and S that includes errors from the reading of the first, second, third, and fourth representative pages_V5-1. Performing a background read BRP of a fifth page_Reading(0, -2) to define a fifth codeword that is decoded to determine the number of errors in the reading of the page (as shown in step 605), and the number of errors is summed (606) to obtain a final voltage offset error sum S_V5-1The final voltage offset error sum S_V5-1Is the sum of all errors in the first, second, third, fourth and fifth codewords. Once all pages have been read (608, 616), the voltage offset is changed (607) by adding one to the voltage offset value used in the previous background read 604 and steps 603-606 are repeated using the voltage offset of the previous step 607 until all pages (608, 616) have been read at all offsets (609, 617). In the exemplary embodiment shown in FIG. 10A, all other biases for voltage region 5The shift repeats steps 604-607 while maintaining the shift in the first voltage region at 0. More specifically, in BRP_ReadingReading (604) five exemplary pages at (0, -1) (shown as threshold voltages 41, 50) to calculate (606) a second voltage offset error sum S_V5-2. On the next iteration, the offset of region 5 is changed to 0, and at BRP_ReadingFive exemplary pages are read (604) at (0,0) (shown as threshold voltages 41, 45) to calculate (606) a third voltage offset error and S_V5-3. On the next iteration, the offset for region 5 is changed to +1 at step 607, and at BRP_ReadingFive exemplary pages are read at (0, +1) (shown as threshold voltages 41, 51) to calculate (606) a fourth voltage offset error sum S_V5-4. On the next iteration, the offset for region 5 is changed to +2 at step 607, and at BRP_ReadingFive exemplary pages are read at (0, +2) (shown as threshold voltages 41, 52) to calculate (606) a fifth voltage offset error sum S_V5-5. At step 610, it is determined that there is a minimum number of errors (this would be the error sum S)_V5-1、S_V5-2、S_V5-3、S_V5-4And S_V5-5Minimum of (d) is shifted. In this example, the second voltage offset error sum S_V5-2Is determined to have a minimum number of errors corresponding to a read offset value of-1, which is stored (611) (e.g., (V)_BRP51) is the first offset value of the updated read offset values for the group of pages. In one embodiment, the updated read offset values are stored by overwriting the corresponding read offset values set at step 602.

The threshold voltage 41 for zone 1 is then identified for updating (603) and reading is performed at different offsets in zone 1 until all five pages to be read have been read at all offsets (as indicated by line 616 and 617), while the threshold voltage bias for all other zones is maintained at the updated threshold offset from step 611, or the value set at step 602 if a particular threshold voltage has not been selected for updating (603). In the example shown in FIG. 10C, step 604 and 607 perform background reads at offsets 41 and 54-57 while maintaining the offset for region 5 at-1 (threshold voltage 50). Furniture setIn particular, in BRP_ReadingFive exemplary pages are read (604) at (-2, -1) (shown as threshold voltages 54, 50) to calculate (604) a first voltage offset error and S_V1-1(ii) a In BRP_ReadingReading (604) five exemplary pages at (-1, -1) (shown as threshold voltages 55, 50) to calculate (606) a second voltage offset error sum S_V1-2(ii) a In BRP_ReadingReading (604) five exemplary pages at (0, -1) (shown as threshold voltages 41, 50) to calculate (606) a third voltage offset error and S_V1-3(ii) a And in BRP_Reading(+1, -1) (shown as threshold voltages 56, 50) five exemplary pages are read to calculate (606) a fourth voltage offset error sum S_V1-4. On the next iteration, the offset for region 1 is changed to +2 at step 607, and at BRP_Reading(+2, -1) (shown as threshold voltages 57, 50) five exemplary pages are read to calculate (606) a fifth voltage offset error sum S_V1-5. At step 610, it is determined to have the smallest number of errors (this would be the error sum S)_V1-1、S_V1-2、S_V1-3、S_V1-4And S_V1-5Minimum of (d) is shifted. In this example, the fourth voltage offset error sum S_V1-4Is determined to have the smallest number of errors (e.g., the smallest value), and is thus compared to S_V1-5The corresponding read offset value is stored (611) (e.g., (V)_BRP1+1)) is the second offset value of the updated read offset values for the group of pages. Since the lower page includes only two reference voltages in this example, all reference voltages have been tested (613). In one embodiment, the results of the calibration process of steps 601-611 are stored in BRP Table 5 as an updated set of voltage offset values for the group of pages under test. In this embodiment, the results are concatenated and stored in the threshold voltage shift parameters of a page group as the most recently determined set of updated threshold voltage offsets for that page group, and may be in VBRP₅₀₁＝(V_BRP1,V_BRP5) (having the value VBRP in this example)₅₀₁(+1, -1)).

In the above example, the number of errors is identified by decoding the results of each read. In another embodiment, the first read is used to identifyStored codewords (or read known codewords) and subsequent read results are compared to the identified codewords to determine the total number of errors in each read, the total number of errors are summed to obtain an error sum S_V1-1、S_V1-2、S_V1-3、S_V1-4And S_V1-5. It has been found that this is faster than decoding each read 604, but requires that the known codewords be stored in at least some of the blocks.

In the event that the data from read 604 is uncorrectable or the determined number of errors (605) exceeds a certain threshold, the closed block may be marked as a "weak block" and subsequent steps 605-607 for that weak block reduce the retention time threshold (by half in one embodiment), the endurance threshold (by half in one embodiment) and the block read threshold (by half in one embodiment). Alternatively, the shutdown block may be marked as a bad block.

Each time an updated read offset value is determined based on the occurrence of a durability event, it is stored in BRP Table 5 as the VBRP for the page group_Durability(which represents the most recently determined endurance read offset value for the page group). Each time an updated read offset value is determined based on the occurrence of a retention timer event or a read disturb event, the updated read offset value is stored as the VBRP of the page group_{RET_RD}. When the next endurance event occurs, the VBRP calculated for the group of pages is stored as VBRP_Durability(e.g., by overwriting the previous VBRP_DurabilityValue). Each time VBRP is calculated_DurabilityWhen, the VBRP_DurabilityVBRP stored as a group of pages_{RET_RD}(e.g., by overwriting the previous VBRP_{RET_RD}Value). Each time an updated threshold voltage offset is determined based on the occurrence of a retention timer event or a read disturb event, the updated threshold voltage offset is stored as the VBRP of the group of pages_{RET_RD}(e.g., by overwriting the previous VBRP_{RET_RD}Value). VBRP stored as a group of pages_{RET_RD}Thus represents the most recently determined updated read offset value for the group of pages, and may come from an endurance event, a retention fixA timer event or a read disturb event, and is a temporary voltage threshold offset value that accounts for changes to the threshold voltage when the block is off.

In one embodiment illustrated in fig. 15-16, the endurance threshold is set to 500P/E cycles such that every 500P/E cycles constitutes an endurance event, and the retention threshold is set to 12 hours such that the retention timer event occurs after every 12 hours that the block is turned off. The read disturb threshold is set to 50,000 reads such that a read disturb event occurs after every 50,000 reads of the block read counter. FIG. 15 shows an exemplary timeline, and FIG. 16 shows an event matrix including the events of FIG. 15 and several subsequent events. In the following example, in the term VBRP (x, y, z), x denotes an endurance threshold value when VBRP is calculated, y denotes a retention time threshold value when VBRP is calculated, and z denotes a block read threshold value when VBRP is calculated. Each arrow in fig. 15 represents a starting point for a background reference positioning operation. At 61, the block is opened and at 62, the block is closed. In this example, the P/E cycle count exceeds 500 when the block is closed 62, so the endurance event 70 is determined to have occurred when the block is closed 62. Perform background reference positioning operations and store the results as VBRP_DurabilityAnd VBRP_{RET_RD}And both. After 12 hours from closing the block 62, the first holdback timer event 71 is determined to have occurred (12 hour holdback timer event). Since VBRP is used for the calculation of reserve timer events and read disturb events_{RET_RD}As a starting reference threshold voltage offset, VBRP from 500P/E event 70 is therefore used_{RET_RD}To calculate a new updated threshold voltage offset, VBRP, (500,12,0), which VBRP (500,12,0) is stored as VBRP_{RET_RD}. VBRP from 12-hour reservation timer event 71 upon occurrence of second reservation timer event 72 (24-hour reservation timer event)_{RET_RD}Is used as the starting reference threshold voltage offset in step 602 and the new updated offset value is stored as VBRP_{RET_RD}(500,24,0). Similarly, upon occurrence of a third retention timer event 73(36 hour retention timer event), (from 24 hour retention timer event)Of member 72) VBRP_{RET_RD}Is used as the starting reference threshold voltage offset in step 602, and the new updated offset value is stored as VBRP_{RET_RD}(500,36,0)。

At the time of the endurance event, VBRP (VBRP) calculated in the most recent endurance event of the page group_Durability) Is used as the starting reference threshold voltage offset in step 602. Thus, upon a second endurance event 74 (at 1,000P/E cycles), VBRP from 500P/E event 70_DurabilityIs used as the starting reference threshold voltage offset in step 602.

Upon occurrence of a retention timer event, the most recently calculated updated threshold voltage offset value is used as the starting reference threshold voltage offset in step 602, which may be an updated VBRP calculated in response to the occurrence of a endurance event, a retention timer event, or a read disturb event. Since each VBRP calculated from the endurance event is stored as a VBRP_{RET_RD}And VBRP_DurabilityBoth, therefore the value VBRP_{RET_RD}Always reflecting the most recently updated threshold voltage offset for the page group. Thus, upon the occurrence of a reserve timer event 75(12 hour reserve timer event), VBRP from 1K P/E event 74_{RET_RD}Is used as the starting reference threshold voltage offset in step 602. Upon occurrence of a second reservation timer event 76(24 hour reservation timer event), VBRP (from 12 hour reservation timer event 75)_{RET_RD}Is used as the starting reference threshold voltage offset in step 602. Similarly, upon occurrence of a third retention timer event 77(36 hour retention timer event), VBRP (from 24 hour retention timer event 76)_{RET_RD}Is used as the starting reference threshold voltage offset in step 602.

Upon occurrence of a read disturb event 79, the most recently calculated updated threshold voltage offset value is used as the starting reference threshold voltage offset in step 602, which may be an updated VBRP calculated in response to the occurrence of a endurance event, a retention timer event, or a read disturb event. Since each VBRP calculated from the endurance event is stored as a VBRP_{RET_RD}And VBRP_DurabilityBoth, therefore the value VBRP_{RET_RD}Always reflecting the most recently updated threshold voltage offset for the page group. Thus, at an exemplary 50,000 read count read disturb event 79, VBRP_{RET_RD}(1K,36,0) is used as the starting threshold voltage offset in step 602 and the resulting VBRP (1K,36,50K) is stored as VBRP_{RET_RD}。

When performing background reference positioning operations for endurance events, it has been found that better results are obtained when the read count is not too high. Thus, in embodiments of the present invention, a limit on the number of read counts is applied when determining whether a background reference positioning operation should be performed. In one such embodiment, when the number of P/E cycles constitutes an endurance event, the calculation of the background reference location steps 603 and 612 is not performed if the read count exceeds a quantity threshold (e.g., 25,000 reads).

When a block is free 63, the previously determined VBRP_{RET_RD}The value is no longer useful for determining the voltage threshold correction. Thus, a background reference location operation immediately following a block erase will use the VBRP (VBRP) calculated in the most recent endurance event of the page group_Durability) As the starting reference threshold voltage offset in step 602, whether the VBRP is a VBRP calculation for a endurance event, a reserve timer event, or a read disturb event. VBRP from 1,000P/E event 74 if the endurance event was not determined to have occurred and the reserve or read disturb event 78 was determined to have occurred at the time the block event 65 was closed_DurabilityIs used as the starting reference threshold voltage in step 602 and the calculated VBRP is stored as VBRP_{RET_RD}。

As previously discussed, after block idles (63), the VBRP previously determined_{RET_RD}The value is no longer useful. Thus, in embodiments of the present invention, the first VBRP is determined after a block is closed and for the closed block_{RET_RD}When a read was previously performed, the read continues to use the VBRP (VBRP) calculated in the most recent endurance event of the page group_Durability) Until the first VBRP is determined after a close block event_{RET_RD}。

Using both background reference positioning and background LLR calculation results in fewer decoding errors and thus fewer read retry operations, thereby providing a non-volatile memory system 1 with reduced latency compared to systems using conventional read operations. Further, the BER is reduced, thereby extending the life of the nonvolatile memory system 1.

In the example shown in FIG. 16, VBRP for the most recently determined updated set of BRP offsets for the page group₅₀₁＝(V_BRP1,V_BRP5) (which has a value of VBRP₅₀₁Expressed in the form (+1, -1)), for a first BRP offset value V_BRP1Calculating a first set of LLR values and offsetting a value V for a second BRP_BRP5A second set of LLR values is calculated. At offset value V for BRP_BRP1In the following example of computing the first set of LLR values, the first LLR value (LLRA _ V)_BRP1) Will indicate the read error in region A, the second LLR value (LLRB _ V)_BRP1) Will indicate the read error in region B, the third LLR value (LLRC _ V)_BRP1) Will indicate an error of the read in region C, and a fourth LLR value (LLRD _ V)_BRP1) An error in the reading in region D will be indicated. Thus, there is one set of LLRs for each reference describing a voltage region, with the LLR distribution centered on the most recently determined BRP offset value for the threshold voltage region.

Since in this example V is_BRP1Is +1 (shown as line 56 in FIGS. 10A-10C), and therefore corresponds to V for the purposes of the calculation_BRP1The read result at offset 0 will be stored as BRP _ N in register 93, the read at +1 will be stored as BRP in register 92 of fig. 17, and the read result at +2 will be stored as BRP _ P in register 93, and the calculated LLRA _ V_BRP1、LLRB_V_BRP1、LLRC_V_BRP1And LLRD _ V_BRP1May be concatenated and stored as a first set of LLR values LLR in LLR table 10₅₀₁_V_BRP1＝(LLRA_V_BRP1,LLRB_V_BRP1,LLRC_V_BRP1,LLRD_V_BRP1)。

Since in this example V is_BRP5Is-1 (shown as line 50 in FIGS. 10A-10C), and thus corresponds to V for the purposes of the calculation_BRP5LLR offset ofSet, the read result at offset-2 will be stored as BRP _ N in register 93, the read at-1 will be stored as BRP in register 92 of FIG. 17, and the read result at 0 will be stored as BRP _ P in register 93, and the calculated LLRA _ V_BRP5、LLRB_V_BRP5、LLRC_V_BRP5And LLRD _ V_BRP5May be concatenated and stored in the LLR table 10 as a second set of LLR values LLR₅₀₁_V_BRP5＝(LLRA_V_BRP5,LLRB_V_BRP5,LLRC_V_BRP5,LLRD_V_BRP5)。

In an alternative embodiment, after the nonvolatile memory controller 11 is initialized, all BRP offset values are set to 0 and all LLR values are set to default values (e.g., -6, +6) to obtain the initial BRP tables 5 and LLR tables 10. In this embodiment, each set of calculated BRP offsets will be an updated set of BRP offsets, and each identified set of LLR values will be an updated set of LLR values.

By performing the test on the actual NAND device being used, and by continuing to perform the background test as the NAND device ages, the method and apparatus of the present invention provides LLR values that accurately indicate the error probability of soft reads. This reduces BER and extends the lifetime of the NAND flash memory chip. In addition, the number of read errors is reduced, resulting in reduced read latency.

In various embodiments, the system of the present invention may be implemented in a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).

As a brief summary, at least the following broad concepts are disclosed herein:

concept 1. a method, comprising:

programming a codeword into each of a plurality of non-volatile memory devices in response to receiving a host request write instruction;

performing background reads of at least one of the programmed codewords in a block of the non-volatile memory device at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage;

decoding at least one of the background reads to identify the at least one codeword;

identifying a set of log-likelihood ratio (LLR) values using the read results and the identified at least one codeword;

continuing to perform at least one of the background read, decoding the background read, and the identifying to identify a set of LLR values for each block of the non-volatile memory device;

further continuing to perform at least one of background reads, decode the background reads, and the identification to identify the updated set of LLR values;

performing a host request read of one of the non-volatile memory devices; and

the result of the host requested read is decoded using LLR values from the updated set of LLR values corresponding to the block read in the host requested read.

Concept 2. the method of concept 1, wherein the background read is performed only on the closed block.

Concept 3. the method of concept 1, wherein the background read is performed only on the closed block and is performed only upon occurrence of one or more of a durability event, a reserve timer event, and a read disturb event at the closed block.

Concept 4. the method of concept 1, further comprising:

storing the result read by the background;

using the results of the background read to identify an offset that yields a minimum total number of errors for each default threshold voltage; and is

Wherein executing the host request read further comprises: the host-requested read is performed using a threshold voltage shift read instruction at an identified offset corresponding to the block of codewords being read that results in a minimum total number of errors.

Concept 5. the method of concept 4, further comprising:

storing each identified offset that yields a minimum total number of errors as a Background Reference Positioning (BRP) value in a BRP table, the BRP table including a block index corresponding to each BRP value indicating a corresponding block number;

continuing to perform at least one of the background read, the storing, the decoding background read, and the identifying the offset that yields the minimum total number of errors to store the BRP value for each block of the non-volatile memory device;

further continuing to perform at least one of background reads, storing, decoding background reads, and identifying an offset that yields a minimum total number of errors to identify an updated offset value;

each time an updated offset value is identified, the updated offset value is stored in the BRP table by overwriting any previously stored BRP values of the corresponding block.

Concept 6. the method of concept 1, wherein each block comprises a plurality of pages divided into page groups;

wherein performing the background read further comprises: performing a background read of a representative page of a group of pages at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage;

wherein identifying the set of LLR values further comprises: identifying a set of LLR values for each group of pages using the read results and the identified at least one codeword; and is

Wherein decoding the result that the host requested to read further comprises: the result of the host request read is decoded using LLR values from the updated set of LLR values corresponding to the group of pages of the page being read.

Concept 7. the method of concept 6, further comprising:

generating an LLR table;

storing each of the identified sets of LLR values in an LLR table along with an index identifying the corresponding group of pages; and is

Wherein each time an updated set of LLR values is identified, the updated set of LLR values is stored in the LLR table by overwriting the corresponding set of LLR values previously stored in the LLR table.

Concept 8 the method of concept 7, wherein decoding the result of the host request read further comprises: the result of the host request read is decoded by indexing the LLR table using the index values corresponding to the page group of the page being read.

Concept 9. the method of concept 4, further comprising:

generating a BRP table, the BRP table including BRP values and corresponding indices corresponding to each page group;

continuing to perform at least one of background reads, storing, decoding background reads, and identifying to identify a set of LLR values for each block of the non-volatile memory device; and

each identified offset that yields the minimum total number of errors is stored in the BRP table as a BRP value for the corresponding group of pages, such that each BRP value in the BRP table is the most recently identified offset that yields the minimum total number of errors corresponding to the group of pages.

Concept 10. the method of concept 1, further comprising:

wherein performing the background read further comprises: performing a background read of the representative page at a default threshold voltage within each threshold voltage region required to read the representative page of the block, at one or more threshold voltage offsets less than the default threshold voltage within each threshold voltage region required to read the representative page, and at one or more threshold voltage offsets greater than the default threshold voltage within each threshold voltage region required to read the representative page;

wherein identifying the set of LLR values further comprises: using the stored read results and the identified at least one codeword to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page;

wherein continuing to perform the background read further comprises: continuing to perform at least one of background reads, decoding the background reads, and the identifying to identify a set of LLR values corresponding to each threshold voltage region required to read a representative page of each block; and is

Wherein continuing to perform the background read further comprises: continuing to perform at least one of the background read, decoding the background read, and identifying to identify an updated set of LLR values corresponding to each threshold voltage region required to read the representative page.

Concept 11. a non-volatile memory controller, comprising:

write circuitry coupled to the plurality of non-volatile memory devices, the write circuitry configured to: programming a codeword to each of a plurality of non-volatile memory devices in response to receiving a host request write instruction;

a read circuit configured to: performing background reads of at least one of the programmed codewords in a block of the non-volatile memory device at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage;

a decoder circuit configured to: decoding at least one of the background reads to identify the at least one codeword;

a log-likelihood ratio (LLR) circuit configured to: identifying a set of LLR values corresponding to a default threshold voltage using the read result and the identified at least one codeword;

wherein the non-volatile memory controller is configured to: continuing to perform at least one of the background read, decoding the background read, and identifying the set of LLR values to identify the set of LLR values for each block of the non-volatile memory device;

wherein the non-volatile memory controller is configured to: further continuing to perform at least one of the background reads, decode the background reads, and identify the set of LLR values to identify the updated set of LLR values;

a read circuit configured to: performing a host requested read of the non-volatile memory device; and

a decoder circuit configured to: the result of the host requested read is decoded using LLR values from the updated set of LLR values corresponding to the block read in the host requested read.

Concept 12 the non-volatile memory controller of concept 11, further comprising:

a Background Reference Positioning (BRP) circuit configured to: using the results of the background read to identify an offset that yields a minimum total number of errors for each default threshold voltage; and is

Wherein executing the host request read further comprises: the host-requested read is performed using a threshold voltage shift read instruction at an identified offset corresponding to the block of codewords being read that results in a minimum total number of errors.

Concept 13 the non-volatile memory controller of concept 12, further comprising:

a BRP table coupled to the BRP circuit and the read circuit, the BRP table including a BRP value and a corresponding index for each block of the non-volatile memory device;

wherein each identified offset yielding a minimum total number of errors is stored as a BRP value in the BRP table by overwriting any previously stored BRP value of the corresponding block.

Concept 14 the nonvolatile memory controller of concept 11, wherein each block comprises a plurality of pages divided into page groups;

wherein the read circuit is configured to: performing background reads of a representative page of a group of pages at one or more default threshold voltages, at one or more threshold voltage offsets less than each default threshold voltage, and at one or more threshold voltage offsets greater than each default threshold voltage;

wherein the decoder circuit is configured to: decoding one of the reads of the exemplary pages of each block to identify at least one codeword in each group of pages;

wherein the LLR circuit is configured to: identifying at least one updated set of LLR values for each block using the read results and the identified at least one codeword in each group of pages; and is

Wherein the read circuit is configured to: performing a host requested read of the non-volatile memory device, and the decoder circuit is configured to: the result of the host requested read is decoded using LLR values from the updated set of LLR values corresponding to the group of pages of the page read in the host requested read.

Concept 15. the non-volatile memory controller of concept 11, wherein the background read is performed only on the shutdown block.

Concept 16. the non-volatile memory controller of concept 14, wherein the background read is performed only on the shutdown block and is performed only upon occurrence of one or more of a endurance event, a reserve timer event, and a read disturb event at the shutdown block.

Concept 17 the non-volatile memory controller of concept 16, wherein:

the non-volatile memory controller is configured to: determining a number of program and erase cycles for each block of a non-volatile memory device, and wherein the non-volatile memory controller is configured to: determining that a endurance event has occurred each time the determined number of program and erase cycles of the closed block reaches the program and erase cycle threshold number;

wherein the non-volatile memory controller is configured to: determining a closed block retention time for each closed block of the non-volatile memory device, and wherein the non-volatile memory controller is configured to: determining that a retention timer event has occurred each time a closure block retention time reaches a threshold retention time; and is

Wherein the non-volatile memory controller is configured to: determining a number of reads per block of a non-volatile memory device, and wherein the non-volatile memory controller is configured to: each time the number of reads of the shutdown block reaches a threshold number of reads, it is determined that a read disturb event has occurred.

Concept 18. a non-volatile memory system, comprising:

a plurality of non-volatile memory devices;

a non-volatile memory controller coupled to a non-volatile memory device, the non-volatile memory controller comprising:

a write circuit configured to: programming a non-volatile memory device to store user data in the non-volatile memory device in response to receiving a host request write instruction including the user data;

a read circuit configured to: performing a background read of the representative page at a default threshold voltage within each threshold voltage region required to read the representative page of the group of pages, at one or more threshold voltage offsets less than the default threshold voltage within each threshold voltage region required to read the representative page, at one or more threshold voltage offsets greater than the default threshold voltage within each threshold voltage region required to read the representative page;

a decoder circuit configured to: decoding results from some of the background reads of a representative page to identify a codeword stored in the representative page;

a log-likelihood ratio (LLR) circuit configured to: using the read results and the identified codewords to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page; and is

Wherein the read circuit is configured to: continuing to perform background reads, decoding results from some of the background reads, and the LLR circuit is configured to: continuing to identify the set of LLR values to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page of each group of pages;

wherein the read circuit is further configured to continue performing background reads, and the LLR circuit is further configured to identify the updated set of LLR values; and is

Wherein the read circuit is configured to: performing a host requested read of the non-volatile memory device, and the decoder circuit is configured to: the result of the host requested read is decoded using LLR values from the updated set of LLR values corresponding to the group of pages of the page read in the host requested read.

Concept 19 the non-volatile memory system of concept 18, wherein the LLR circuit is configured to: storing each of the identified sets of LLR values in an LLR table along with an index identifying the corresponding page, and wherein each time an updated set of LLR values is identified, the LLR circuit is configured to: the updated set of LLR values is stored in the LLR table by overwriting the corresponding set of LLR values previously stored in the LLR table.

Concept 20 the non-volatile memory system of concept 19, wherein the decoder circuit is configured to: LLR values to be used for decoding host requests to read are identified by indexing an LLR table using index values corresponding to the page population of the page being read.

While the invention has been described with reference to specific embodiments thereof, it will be apparent to those skilled in the art that modifications can be made to the described embodiments without departing from the spirit of the invention. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing detailed description.

Claims (20)

1. A method for non-volatile storage, comprising:

programming, at a non-volatile memory controller, a codeword into each of a plurality of non-volatile memory devices in response to receiving a host request write instruction at the non-volatile memory controller;

performing background reads of at least one of the programmed codewords in a block of the non-volatile memory device at the non-volatile memory controller at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage;

decoding, at a decoder circuit of the non-volatile memory controller, at least one of the background reads to identify the at least one codeword;

identifying, at the non-volatile memory controller, a set of log-likelihood ratio (LLR) values using the read results and the identified at least one codeword;

continuing to perform at least one of a background read, decoding the background read, and an identification at the non-volatile memory controller to identify a set of LLR values for each block of the non-volatile memory device;

continuing further to perform at least one of a background read, decode the background read, and an identification to identify an updated set of LLR values;

performing, at the non-volatile memory controller, a host request read of one of the non-volatile memory devices; and

decoding, at the non-volatile memory controller, a result of the host requested read using LLR values from the updated set of LLR values corresponding to the block read in the host requested read.

2. The method of claim 1, wherein the background read is performed only on closed blocks.

3. The method of claim 1, wherein the background read is performed only on closed blocks and is performed only upon occurrence of one or more of a durability event, a reserve timer event, and a read disturb event at a closed block.

4. The method of claim 1, further comprising:

storing the result of the background reading;

using results of the background read to identify an offset that yields a minimum total number of errors for each default threshold voltage; and is

Wherein executing the host request read further comprises: performing the host-requested read using a threshold voltage shift read instruction at an identified offset corresponding to a block of codewords being read that yields a minimum total number of errors.

5. The method of claim 4, further comprising:

storing each identified offset that yields a minimum total number of errors as a Background Reference Positioning (BRP) value in a BRP table, the BRP table including a block index corresponding to each BRP value indicating a corresponding block number;

continuing to perform at least one of background reads, storing, decoding the background reads, and identifying an offset that yields a minimum total number of errors to store a BRP value for each block of the non-volatile memory device;

continuing further to perform at least one of background reads, storing, decoding the background reads, and identifying an offset that yields a minimum total number of errors to identify an updated offset value;

each time an updated offset value is identified, the updated offset value is stored in the BRP table by overwriting any previously stored BRP value of the corresponding block.

6. The method of claim 1, wherein each block comprises a plurality of pages divided into page groups;

wherein performing the background read further comprises: performing a background read of a representative page of a group of pages at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage;

wherein identifying the set of LLR values further comprises: identifying a set of LLR values for each group of pages using the read results and the identified at least one codeword; and is

Wherein decoding the result of the host request read further comprises: the result of the host request to read is decoded using LLR values from the updated set of LLR values corresponding to the group of pages of the page being read.

7. The method of claim 6, further comprising:

generating an LLR table;

storing each of the identified sets of LLR values in the LLR table along with an index identifying a corresponding group of pages; and is

Wherein each time an updated set of LLR values is identified, the updated set of LLR values is stored in the LLR table by overwriting a corresponding set of LLR values previously stored in the LLR table.

8. The method of claim 7, wherein decoding the result of the host request read further comprises: decoding a result of the host request read by indexing the LLR table using an index value corresponding to a page group of the page being read.

9. The method of claim 4, further comprising:

generating a BRP table, wherein the BRP table comprises BRP values and corresponding indexes corresponding to each page group;

continuing to perform at least one of background reads, storing, decoding the background reads, and identifying to identify a set of LLR values for each block of the non-volatile memory device; and

storing each identified offset that produces a minimum total number of errors in the BRP table as a BRP value for the corresponding group of pages, such that each BRP value in the BRP table is the most recently identified offset that produces the minimum total number of errors corresponding to the group of pages.

10. The method of claim 1, further comprising:

wherein performing the background read further comprises: performing a background read of a representative page of a block at a default threshold voltage within each threshold voltage region required to read the representative page, at one or more threshold voltage offsets less than the default threshold voltage within each threshold voltage region required to read the representative page, and at one or more threshold voltage offsets greater than the default threshold voltage within each threshold voltage region required to read the representative page;

wherein identifying the set of LLR values further comprises: using the stored read results and the identified at least one codeword to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page;

wherein continuing to perform the background read further comprises: continuing to perform at least one of background reads, decoding the background reads, and identifying to identify a set of LLR values corresponding to each threshold voltage region required to read a representative page of each block; and is

Wherein continuing to perform the background read further comprises: continuing to perform at least one of a background read, decoding the background read, and identifying to identify an updated set of LLR values corresponding to each threshold voltage region required to read a representative page.

11. A non-volatile memory controller, comprising:

write circuitry coupled to a plurality of non-volatile memory devices, the write circuitry configured to: programming a codeword to each of a plurality of non-volatile memory devices in response to receiving a host request write instruction;

a read circuit configured to: performing background reads of at least one of the programmed codewords in a block of the non-volatile memory device at a default threshold voltage, at one or more threshold voltage offsets less than the default threshold voltage, and at one or more threshold voltage offsets greater than the default threshold voltage;

a decoder circuit configured to: decoding at least one of the background reads to identify the at least one codeword;

a log-likelihood ratio (LLR) circuit configured to: identifying a set of LLR values corresponding to the default threshold voltage using the read result and the identified at least one codeword;

wherein the non-volatile memory controller is configured to: continuing to perform at least one of the background reads, decoding the background reads, and identifying a set of LLR values to identify a set of LLR values for each block of the non-volatile memory device;

wherein the non-volatile memory controller is configured to: further continuing to perform at least one of the background reads, decode the background reads, and identify a set of LLR values to identify an updated set of LLR values;

the read circuit is further configured to: performing a host requested read of the non-volatile memory device; and

the decoder circuit is further configured to: decoding a result of the host requested read using LLR values from the updated set of LLR values corresponding to the block read in the host requested read.

12. The non-volatile memory controller of claim 11, further comprising:

a Background Reference Positioning (BRP) circuit configured to: using results of the background read to identify an offset that yields a minimum total number of errors for each default threshold voltage; and is

Wherein executing the host request read further comprises: performing the host-requested read using a threshold voltage shift read instruction at an identified offset corresponding to a block of codewords being read that yields a minimum total number of errors.

13. The non-volatile memory controller of claim 12, further comprising:

a BRP table coupled to the BRP circuit and the read circuit, the BRP table including a BRP value and a corresponding index for each block of the non-volatile memory device;

wherein each identified offset yielding a minimum total number of errors is stored as a BRP value in the BRP table by overwriting any previously stored BRP value of the corresponding block.

14. The non-volatile memory controller of claim 11, wherein each block comprises a plurality of pages divided into groups of pages;

wherein the read circuit is further configured to: performing background reads of a representative page of a group of pages at one or more default threshold voltages, at one or more threshold voltage offsets less than each default threshold voltage, and at one or more threshold voltage offsets greater than each default threshold voltage;

wherein the decoder circuit is further configured to: decoding one of the reads of the exemplary pages of each block to identify at least one codeword in each group of pages;

wherein the LLR circuit is configured to: identifying at least one updated set of LLR values for each block using the read results and the identified at least one codeword in each group of pages; and is

Wherein the read circuit is further configured to: performing a host requested read of the non-volatile memory device, and the decoder circuit is further configured to: decoding a result of the host requested read using LLR values from the updated set of LLR values corresponding to the group of pages of the page read in the host requested read.

15. The non-volatile memory controller of claim 11, in which the background read is performed only on a shutdown block.

16. The non-volatile memory controller of claim 14, wherein the background read is performed only on a shutdown block and is performed only upon occurrence of one or more of a durability event, a reserve timer event, and a read disturb event at the shutdown block.

17. The non-volatile memory controller of claim 16, wherein:

the non-volatile memory controller is configured to: determining a number of program and erase cycles for each block of the non-volatile memory device, and wherein the non-volatile memory controller is configured to: determining that a endurance event has occurred each time the determined number of program and erase cycles of the closed block reaches the program and erase cycle threshold number;

wherein the non-volatile memory controller is configured to: determining a closed block retention time for each closed block of the non-volatile memory device, and wherein the non-volatile memory controller is configured to: determining that a retention timer event has occurred each time the close block retention time reaches a threshold retention time; and is

Wherein the non-volatile memory controller is configured to: determining a number of reads per block of the non-volatile memory device, and wherein the non-volatile memory controller is configured to: each time the number of reads of the shutdown block reaches a threshold number of reads, it is determined that a read disturb event has occurred.

18. A non-volatile memory system, comprising:

a plurality of non-volatile memory devices;

a non-volatile memory controller coupled to the non-volatile memory device, the non-volatile memory controller comprising:

a write circuit configured to: programming the non-volatile memory device to store user data in the non-volatile memory device in response to receiving a host request write instruction that includes the user data;

a read circuit configured to: performing a background read of a representative page of a group of pages at a default threshold voltage within each threshold voltage region required to read the representative page, at one or more threshold voltage offsets less than the default threshold voltage within each threshold voltage region required to read the representative page, at one or more threshold voltage offsets greater than the default threshold voltage within each threshold voltage region required to read the representative page;

a decoder circuit configured to: decoding results from some of the background reads of a representative page to identify a codeword stored in the representative page;

a log-likelihood ratio (LLR) circuit configured to: using the read results and the identified codewords to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page; and is

Wherein the read circuit is further configured to: continuing to perform the background reads, decoding results from some of the background reads, and the LLR circuit is configured to: continuing to identify the set of LLR values to identify a set of LLR values corresponding to each threshold voltage region required to read the representative page of each group of pages; wherein the read circuit is further configured to continue performing the background read, and the LLR circuit is further configured to identify an updated set of LLR values; and is

Wherein the read circuit is further configured to: performing a host requested read of the non-volatile memory device, and the decoder circuit is further configured to: decoding a result of the host requested read using LLR values from the updated set of LLR values corresponding to the group of pages of the page read in the host requested read.

19. The non-volatile memory system of claim 18, wherein the LLR circuit is configured to: storing each of the identified sets of LLR values in an LLR table along with an index identifying the corresponding page, and wherein each time an updated set of LLR values is identified, the LLR circuit is configured to: storing the updated set of LLR values in the LLR table by overwriting a corresponding set of LLR values previously stored in the LLR table.

20. The non-volatile memory system of claim 19, wherein the decoder circuit is further configured to: the LLR values to be used to decode the host request read are identified by indexing the LLR table using index values corresponding to the page population of the page being read.

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