CN109801667B

CN109801667B - Parallel static memory address line open circuit test method

Info

Publication number: CN109801667B
Application number: CN201811602061.XA
Authority: CN
Inventors: 张锐
Original assignee: CETC 20 Research Institute
Current assignee: CETC 20 Research Institute
Priority date: 2018-12-26
Filing date: 2018-12-26
Publication date: 2020-09-08
Anticipated expiration: 2038-12-26
Also published as: CN109801667A

Abstract

The invention provides a method for testing open circuit of address lines of a parallel static memory, which is provided with the parallel static memoryThe memory has m address lines, n data lines, and the address line from high to low is represented as A_m‑1～A₀The data line is represented as D from high to low_n‑1～D₀(ii) a When testing m address lines, firstly writing decimal numbers into the decimal addresses in sequence; then reading out the corresponding data; subtracting the written data and the read data of the same address respectively, if the result is all 0, the address line has no open circuit phenomenon; otherwise, finding out all addresses with the subtraction value of the written data and the read data not being 0, if k addresses exist, breaking off k address lines, and representing A by what the decimal value i of the original written data of the address with the subtraction value not being 0 is_iThe address line is open. Compared with the existing known method, the method saves about one third of time, effectively shortens the test time and improves the working efficiency.

Description

Parallel static memory address line open circuit test method

Technical Field

The invention relates to a method for testing an SRAM.

Background

In recent years, with the rapid development of computer technology and integrated circuit technology, high-density memory devices based on BGA and QFP packages are used in large numbers on boards. Parallel static memory (SRAM) is widely used in electronic devices due to its advantages of high integration, low manufacturing cost, and convenient use, and these chips are subjected to strict performance tests when shipped from factories, but are easily subjected to pin oxidation, electrical mounting process, etc. to cause device pin cold solder, and lead cracking in harsh environments.

The parallel static memory (SRAM) interface mainly comprises a control line, a data line and an address line, wherein the number of the data line and the address line is large, and the fault probability is high. The conventional inspection means such as visual inspection, X-ray inspection, intelligent image identification and the like are easy to judge the phenomena of overlapping and short circuit of the pins of the memory, but the broken circuit phenomena such as insufficient solder, cracking and the like are difficult to judge and position by the means, and generally the judgment is carried out by reading and writing tests on the memory. The broken data line is easy to locate, generally adopting 'all 0' and 'all 1' method, i.e. firstly writing 'all 0' in the same address, reading out, then writing 'all 1' in the same address, reading out, judging the binary number of the data twice, and if the bit is the same, then the broken data line is broken. However, the above method is not suitable for judging the address line, and the time overhead is too large.

According to the published literature data, at present, Li gang et al provide a method for testing a system RAM in 51 series single chip system design and application skills, the method is to check in two steps, send 'all 0' and 'all 1' to the whole data area in sequence, and then read out and compare in sequence, if the difference is not the same, an error is indicated. Since the method uses accumulation and verification of the block of data, a large amount of data transfer between the CPU and the RAM is required, and the time overhead required for the RAM self-test is very large. An improved method for self-checking a single-chip microcomputer system RAM (random access memory) provided by Chen guard and soldiers and the like has the advantages that a line-by-line scanning method is short in time for judging that an address line of a memory is broken, and only 2 times of writing and 1 time of reading are carried out on the RAM when one address line is detected, namely, the n-bit address line is judged, and the writing and the reading are carried out for 2n times. Although this method has greatly reduced the detection time, the detection efficiency still needs to be further improved.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a method for detecting the open circuit of an address line of a parallel static memory (SRAM), which can improve the efficiency and judge the open circuit of the address line of the memory more quickly.

The technical scheme adopted by the invention for solving the technical problems is as follows: if the parallel static memory has m address lines and n data lines, the address line is expressed as A from high to low_m-1～A₀The data line is represented as D from high to low_n-1～D₀(ii) a When testing m address lines, firstly decimal address 2⁰、2¹、2²、2³……2^m-2、2^m-10 are written with decimal numbers of 0, 1, 2, 3 … …, m-2, m-1 and m in sequence respectively; and then from address 2⁰、2¹、2²、2³……2^m-2、2^m-10, reading out corresponding data; subtracting the written data and the read data of the same address respectively, if the result is all 0, the address line has no open circuit phenomenon; otherwise, finding out all addresses with the subtraction value of the written data and the read data not being 0, if k addresses exist, breaking the k address lines, and showing A by what the decimal value i of the original written data of the addresses with the subtraction value not being 0 is_iThe address line is open.

The invention has the beneficial effects that: the open circuit condition of the m memory address lines is judged, and one or more address lines can be quickly and fixedly opened through m +1 writing operations and m +1 reading operations, so that the open circuit of the one or more address lines is saved by about one third compared with the conventional method, the test time is effectively shortened, and the working efficiency is improved. Meanwhile, the method can be popularized to the address line open circuit detection of various parallel memories.

Detailed Description

The present invention is further illustrated by the following examples, which include, but are not limited to, the following examples.

The invention provides a testing method for the open circuit positioning of address lines of a parallel static memory (SRAM), which is particularly suitable for positioning communication faults of the SRAM in a circuit board card due to cold joint and cracking of chip pins caused by the use of a printed circuit board in an electric fitting and equipment severe environment.

If the parallel static memory has m address lines and n data lines, the address line is expressed as A from high to low_m-1～A₀The data line is represented as D from high to low_n-1～D₀The method can test the number of the address wires to be 1-2ⁿRoot, i.e. the n-th square root of at most 2, so that 1. ltoreq. m.ltoreq.2ⁿIn the following documents, m and n both represent the definition and will not be described.

Testing m address lines to decimal address 2⁰、2¹、2²、2³……2^m-2、2^m-10 are written with decimal numbers of 0, 1, 2, 3 … …, m-2, m-1 and m in sequence respectively; and then from addresses 20, 2¹、2²、2³……2^m-2、2^m-1And 0, corresponding data is read out. Subtracting the written data and the read data of the same address respectively, if the result is all 0, the address line has no open circuit phenomenon; otherwise, the address line has a disconnection phenomenon. Finding out addresses with subtraction value of not 0 between all written data and read data, if k addresses exist, then k address lines are open circuit, and the decimal value i (i is more than or equal to 0 and less than or equal to m) of the original written data of the addresses with subtraction value of not 0 is represented as A_iThe address line is open.

In the embodiment of the invention, the specific implementation process of the invention is described by testing the address line of the SRAM (model CY7C1061AV33) by a processor (model TMS320C 28335). The number of data lines between the processor and the SRAM is 16, and the data lines are represented as D₇～D₀N is 8; the address lines are 10 in total and are denoted by A₉～A₀And m is 10. Setting A₉、A₅、A₁、A₀Is in an open circuit state.

Decimal address 2⁰、2¹、2²、2³……2⁸、2⁹0 are written in order decimal numbers 0, 1, 2, 3 … …, 8, 9, 10, respectively, and then from decimal address 2⁰、2¹、2²、2³……2⁸、2⁹And 0 reading data, and subtracting the read data from the write data at the same address. The write data, read data, and the difference between the write data and the read data in the write address are shown in the following table:

as can be seen from the table, since there are 4 addresses with subtraction value of not 0 between the write data and the read data, it is judged that there is a break of 4 address lines, and the decimal values of the original write data of the addresses with subtraction value of not 0 are 0, 1, 5, and 9, respectively, thus representing A₀、A₁、A₅、A₉The address line is open.

The judgment result is consistent with the actual result, and the method is proved to be capable of quickly and effectively positioning the open circuit state of the address line of the memory.

Claims

1. A method for testing open circuit of address lines of a parallel static memory is characterized by comprising the following steps:

if the parallel static memory has m address lines and n data lines, the address line is expressed as A from high to low_m-1～A₀The data line is represented as D from high to low_n-1～D₀(ii) a When testing m address lines, firstly decimal address 2⁰、2¹、2²、2³……2^m-2、2^m-1And 0 are respectively written with decimal numbers of 0, 1, 2, 3 … …, m-2, m-1 and m in sequence, wherein m is more than or equal to 1 and less than or equal to 2ⁿ(ii) a And then from address 2⁰、2¹、2²、2³……2^m-2、2^m-10 phase readoutResponding to the data; subtracting the written data and the read data of the same address respectively, if the result is all 0, the address line has no open circuit phenomenon; otherwise, finding out all addresses with the subtraction value of the written data and the read data not being 0, if k addresses exist, breaking the k address lines, and showing A by what the decimal value i of the original written data of the addresses with the subtraction value not being 0 is_iThe address line is open.