CN109799871A - A kind of high frequency clock signal driving circuit - Google Patents
A kind of high frequency clock signal driving circuit Download PDFInfo
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- CN109799871A CN109799871A CN201910009440.6A CN201910009440A CN109799871A CN 109799871 A CN109799871 A CN 109799871A CN 201910009440 A CN201910009440 A CN 201910009440A CN 109799871 A CN109799871 A CN 109799871A
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- clock signal
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- mode
- triode
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Abstract
The invention discloses high frequency clock signal driving circuits, it is related to clock circuit field, the circuit includes amplifying circuit, and the amplifying circuit includes the input module and output module of electrical connection, it is characterised in that: the input module receives clock signal and is sent to output module by transmission line.The output module includes load circuit, the load circuit in response to the input module clock signal and export clock signal to clock signal receiving unit from output end.This circuit is able to solve the too long problem for causing timing confusion of clock cabling, and improves the situation of clock signal reflection, promotes the integrality of clock signal.
Description
Technical field
The present invention relates to clock circuit fields, and in particular to a kind of high frequency clock signal driving circuit.
Background technique
With the fast development of the communication technology, the demand to chip is increasing.In chip, clock signal is in chip
Key signal, clock signal integrity design is to need issues that need special attention.
Signal integrity needs emphasis to consider reflection, crosstalk and the timing of signal, and in the chips, the frequency of clock signal is most
Height, cabling also longest, the load of driving is often also very much, and signal integrity body problem is also the most serious.Often due to clock cabling
It is very long, it causes the delay of clock cabling very big, be easy to cause timing chaotic.
Meanwhile when clock signal arrival open-circuited load unit, due to impedance mismatch, reflection easy to form, such as
This reflection is not limited in fruit circuit, can clock signal be distorted.Clock signal distortion, will cause timing confusion etc. and asks
Topic, clock signal integrity have become the whether successful critical issue of chip.
Summary of the invention
In view of the deficiencies in the prior art, the purpose of the present invention is to provide a kind of high frequency clock signal driving electricity
Road is able to solve the too long problem for causing timing confusion of clock cabling, and improves the situation of clock signal reflection, promotes clock
The integrality of signal.
To achieve the above objectives, the embodiment of the present invention provides a kind of high frequency clock signal driving circuit comprising amplification electricity
Road, the amplifying circuit include the input module and output module of electrical connection,
The input module receives clock signal and is sent to output module by transmission line；
The output module includes load circuit, the load circuit in response to the input module clock signal and from
Output end exports clock signal to clock signal receiving unit.
As a preferred embodiment, the clock signal is differential signal, and the amplifying circuit is differential amplification
Circuit, the transmission line of the clock signal include first transmission line and second transmission line.
As a preferred embodiment, the amplifying circuit includes the first triode, the second triode, the first load
Resistance, the second load resistance:
The emitter of first triode and the second triode connects with biasing circuit or ground, the collector of the first triode
Connect with one end of first transmission line, the collector of the second triode connects with one end of second transmission line, the first load resistance
Connect with the other end of first transmission line and phase contact be as the first output end, the second load resistance and second transmission line it is another
End connects and phase contact is as second output terminal, the other end and voltage source of the first load resistance other end, the second load resistance
Connect, the clock signal of difference is inputted from the ground level of the first triode, the second triode.
As a preferred embodiment, the input terminal of the clock signal receiving unit is equipped with differential mode match circuit.
As a preferred embodiment, the differential mode match circuit includes: multiple and clock signal receiving unit one
One corresponding differential mode build-out resistor, the both ends of each differential mode build-out resistor are set on a clock signal receiving unit and connect
Receive two receiving ends of differential clock signal.
As a preferred embodiment, the input terminal of the clock signal receiving unit is additionally provided with common mode matching electricity
Road.
As a preferred embodiment, the common mode match circuit includes: the first common-mode resistance, first common mode
Resistance one end ground connection；
First common mode capacitance, one end are connected with the other end of first common-mode resistance；
Second common-mode resistance, second common-mode resistance one end ground connection；
Second common mode capacitance, second common mode capacitance connect with the second common-mode resistance other end；Meanwhile
The other end of the other end of first common-mode resistance and the second common-mode resistance respectively with clock signal receiving unit
Differential clock signal interface connect.
As a preferred embodiment, the amplifier further includes biasing circuit.
As a preferred embodiment, the biasing circuit includes third triode, third biasing resistor；
The emitter of the collector of the third triode and the first triode, the second triode emitter connect；
The emitter of the third grid tube connects with one end of third biasing resistor, the third biasing resistor it is another
The ground level of end ground connection, the third transistor receives bias voltage.
As a preferred embodiment, the input circuit further includes Dolby circuit.
Compared with the prior art, the advantages of the present invention are as follows:
Transmission line being set to inside amplifying circuit in high frequency clock signal driving circuit of the present invention, and its load circuit
It is responded by the transmission cable, which is not directly used for transmission clock signal to clock signal receiving unit, and
Be for keeping in amplifying circuit load circuit to connect with the telecommunications of its input terminal, it is direct by the amplification characteristic of amplifying circuit
Clock signal is exported in load circuit.Reduce the time delay loss in transmission signal with this configuration, reduces timing confusion and ask
Topic, improves the integrality of clock signal.Simultaneously because output module is set to the position of clock signal receiving unit receiving end,
Clock signal receiving unit can directly receive clock signal, and clock signal distortion is less.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, a letter is made to the corresponding attached drawing of embodiment below
Singly introduce, it should be apparent that, drawings in the following description are some embodiments of the invention, for ordinary skill people
For member, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of conventional clock driving circuit embodiment；
Fig. 2 is the structural schematic diagram of high frequency clock signal driving circuit embodiment of the present invention；
Fig. 3 is the circuit diagram of high frequency clock signal driving circuit embodiment of the present invention；
Fig. 4 is another circuit diagram of high frequency clock signal driving circuit embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described in further detail below in conjunction with attached drawing.
Shown in Figure 2, the embodiment of the present invention provides high frequency clock signal driving circuit, is able to solve clock cabling mistake
The long problem for causing timing confusion, and improve the situation of clock signal reflection, promote the integrality of clock signal.
In order to better understand the above technical scheme, being described in detail With reference to embodiment.
As shown in Fig. 2, the embodiment of the present invention provides a kind of high frequency clock signal driving circuit comprising amplifying circuit is put
Big circuit includes the input module and output module of electrical connection.Input module receives clock signal and is sent to by transmission cable
Output module；The load circuit of output module in response to input module clock signal and from output end export clock signal to when
Clock signal receiving unit.
It should be noted that clock signal receiving unit can be high-speed chip, circuit, electronic device, need through it is too long away from
The unit of circuit, module from transmission line reception clock signal can be used as clock signal receiving unit of the invention.
Carry out the benefit that the embodiment of the present invention will be further explained referring to the prior art.It please also refer to Fig. 1 and Fig. 2.Fig. 1
It is the structural schematic diagram of clock driver circuit embodiment in the prior art.In Fig. 2, after the amplification for completing clock signal, feedback
Circuit transmits clock signal to clock signal receiving unit by transmission line.And since transmission line itself is longer, it is very easy to make
It is chaotic at the timing of clock.
Amplifier is divided into two modules by the embodiment of the present invention, and a module receives clock signal, another module is then set
Transmission line is placed in close to the other end of clock signal receiving unit, wherein output module passes through transmission line response clock signal, when
Clock signal passes through load circuit in amplifying circuit no longer as shown in Figure 1, by being transmitted apart from longer transmission line
It amplifies, is directly transmitted in the delivery outlet of load circuit.That is the clock signal input that can act on amplifying circuit
Circuit can obtain the clock signal being exaggerated in load.The effect of the transmission clock signal of transmission line is changed to load
Circuit completes telecommunications connection in amplifying circuit, that is, reduces the influence of transmission line time delay and impedance.
As a preferred embodiment, the clock signal is differential signal, and the amplifying circuit is differential amplification
Circuit, the transmission line of the clock signal include first transmission line and second transmission line.
Differential transfer is a kind of technology of signal transmission, is different from the way of a traditional piece ground wire of a signal wire, poor
Transmission is divided all to transmit signal in this both threads, the amplitude of the two signals is identical, opposite in phase.Transmission in this both threads
Signal be exactly differential signal.Signal receiving end compares the difference of the two voltages to judge the logic state of transmitting terminal transmission.
On circuit boards, difference cabling must be it is isometric, wide, in close proximity to and same level both threads.
Therefore for longer transmission line, the transmission requirement of differential signal is stringenter.And in the embodiment of the present invention
In, the route that transmission line is electrically connected as feed circuit and input module, length is for the clock that exports in output port
Effect of signals is smaller.Meanwhile after selecting differential signal, the circuit anti-interference ability of the present embodiment is stronger, and timing positions also more
It is accurate to add.
For example, as shown in figure 3, the amplifying circuit includes the first triode Q1, the second triode Q2, the first load
Resistance RN, the second load resistance RP:
The emitter of first triode Q1 and the second triode Q2 connect with biasing circuit or ground, the first triode Q1's
Collector connects with one end of first transmission line, and the collector of the second triode Q2Q2 connects with one end of second transmission line, the
One load resistance RN connects with the other end of first transmission line and phase contact is as the first output end, the second load resistance RP and
The other end of two transmission lines connects and phase contact is as second output terminal, the first load resistance RN other end, the second load resistance
The other end of RP connects with voltage source, and the clock signal of difference is inputted from the ground level of the first triode Q1, the second triode Q2.
Clock signal is inputted in the form of differential signal from Q1, Q2 in Fig. 3, cause collector in triode Q1, Q2,
On-off between emitter-base bandgap grading, and then lead to VCC, RN, first transmission line, Q1, Q3, RS, VCC, RP, second transmission line, Q2, Q3, RS,
The on-off on two lines road, and the on-off on two lines road, so that the voltage in the first output end, second output terminal constantly mentions
It rises, fall to zero, and output end can export clock signal by promotion, the decline of the voltage.Here the voltage conduct exported
Clock signal amplify after differential signal, it is no longer necessary to the remote transmission of first transmission line, second transmission line, in the electricity
Lu Zhong, the connecting line that first transmission line, second transmission line are electrically connected as RN and RW and input terminal, and no longer it is transmission letter
Number transmission line, the biggish influence reduced to clock signal, load resistance RN, RP corresponding to input terminal clock believe
Number, directly clock signal is exported from output end.In this way can be to avoid because being delayed caused by transmission line, the timing for improving circuit is asked
Topic.
As an optional embodiment, the input terminal of the clock signal receiving unit is equipped with differential mode match circuit.
The differential mode match circuit is used to carry out differential mode matching to clock signal receiving unit, eliminates in differential signal that differential mode is unmatched makes an uproar
Sound.
Preferably, as shown in figure 4, the differential mode match circuit includes: multiple one-to-one with clock signal receiving unit
Differential mode build-out resistor Rd, the both ends of each differential mode build-out resistor are connected on a clock signal receiving unit and receive difference
Two receiving ends of clock signal.It not only realizes that differential mode matches by resistance Rd, the overshoot of clock signal can also be reduced.
Further, the input terminal of the clock signal receiving unit is additionally provided with common mode match circuit.For believing clock
Number receiving unit carries out common mode matching, eliminates the unmatched noise of common mode in differential signal.
For example, as shown in figure 4, common mode match circuit includes: the first common-mode resistance, first common-mode resistance one end
Ground connection；
First common mode capacitance, one end are connected with the other end of first common-mode resistance；
Second common-mode resistance, second common-mode resistance one end ground connection；
Second common mode capacitance, second common mode capacitance connect with the second common-mode resistance other end；Meanwhile
The other end of the other end of first common-mode resistance and the second common-mode resistance respectively with clock signal receiving unit
Differential clock signal interface connect.
Common-mode resistance and common mode capacitance can be realized common mode matching.By each load unit, i.e. impedance variations more
Common mode and differential mode match circuit is added in significant position, reflection caused by effectively reducing clock transfer in the process.
As a preferred embodiment, amplifier further includes biasing circuit, is being provided with the first, second triode
Afterwards, it needs to guarantee that the first, second triode can work normally, by the way that biasing circuit is arranged, is capable of providing the first, second three poles
Pipe required voltage, electric current environment.
For example, as shown in figure 4, biasing circuit includes third triode, third biasing resistor；The collection of third triode
The emitter of electrode and the first triode Q1, the second triode Q2 emitter connect；The emitter of third transistor Q3 with
One end of third biasing resistor connects, and the other end ground connection of third biasing resistor, the ground level of the third transistor receives biasing
Voltage.Third triode is in energized state after receiving bias voltage, after collector is in operating voltage, be arranged this
Three triodes make the setting of circuit that the base stage of transistor, emitter and collector be made to be in the base stage of required current potential, transmitting
Pole and collector are in required current potential, guarantee that the setting of circuit makes the base stage of transistor, emitter and collector be in institute
It is required that current potential steady operation.
Further, input circuit further includes Dolby circuit.When clock signal is inputted from input terminal, itself may contain
There is unstable flow-disturbing, the clear of clock signal can preferably be improved by carrying out noise reduction to clock signal first by Dolby circuit
Degree.
On the whole, high frequency clock signal driving circuit provided in an embodiment of the present invention leads to compared in traditional technology
The transmission line of long-distance leads to that clock signal timing is chaotic, integrality declines to a great extent, and is able to solve that clock cabling is too long to be caused
The problem of timing confusion, and preferably improve the situation of clock signal reflection, promote the integrality of clock signal.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of high frequency clock signal driving circuit comprising amplifying circuit, the amplifying circuit include the input mould of electrical connection
Block and output module, which is characterized in that
The input module receives clock signal and is sent to output module by transmission line；
The output module includes load circuit, the load circuit in response to the input module clock signal and from output
End exports clock signal to clock signal receiving unit.
2. circuit as described in claim 1, it is characterised in that: the clock signal is differential signal, and the amplifying circuit is
Differential amplifier circuit, the transmission line of the clock signal include first transmission line and second transmission line.
3. high frequency clock signal driving circuit as claimed in claim 2, which is characterized in that the amplifying circuit includes the one or three
Pole pipe, the second triode, the first load resistance, the second load resistance:
The emitter of first triode and the second triode connects with biasing circuit or ground, the collector of the first triode and
One end of one transmission line connects, and the collector of the second triode connects with one end of second transmission line, the first load resistance and
The other end of one transmission line connects and phase contact is as the first output end, the other end phase of the second load resistance and second transmission line
Connect and phase contact be as second output terminal, the first load resistance other end, the second load resistance the other end connect with voltage source,
The clock signal of difference is inputted from the ground level of the first triode, the second triode.
4. high frequency clock signal driving circuit as claimed in claim 2, it is characterised in that: the clock signal receiving unit
Input terminal is equipped with differential mode match circuit.
5. high frequency clock signal driving circuit as claimed in claim 4, which is characterized in that the differential mode match circuit includes:
The multiple and one-to-one differential mode build-out resistor of clock signal receiving unit, the both ends of each differential mode build-out resistor are connected to
Two receiving ends of differential clock signal are received on one clock signal receiving unit.
6. high frequency clock signal driving circuit as claimed in claim 4, it is characterised in that: the clock signal receiving unit
Input terminal is additionally provided with common mode match circuit.
7. high frequency clock signal driving circuit as claimed in claim 6, which is characterized in that the common mode match circuit includes:
First common-mode resistance, first common-mode resistance one end ground connection；
First common mode capacitance, one end are connected with the other end of first common-mode resistance；
Second common-mode resistance, second common-mode resistance one end ground connection；
Second common mode capacitance, second common mode capacitance connect with the second common-mode resistance other end；Meanwhile
The other end of the other end of first common-mode resistance and the second common-mode resistance difference with clock signal receiving unit respectively
Interface clock signal is divided to connect.
8. high frequency clock signal driving circuit as claimed in claim 3, it is characterised in that: the amplifier further includes biased electrical
Road.
9. high frequency clock signal driving circuit as claimed in claim 8, which is characterized in that the biasing circuit includes the three or three
Grade pipe, third biasing resistor；
The emitter of the collector of the third triode and the first triode, the second triode emitter connect；
The emitter of the third grid tube connects with one end of third biasing resistor, another termination of the third biasing resistor
The ground level on ground, the third transistor receives bias voltage.
10. high frequency clock signal driving circuit as described in claim 1 is it is characterized in that, the input circuit further includes noise reduction
Circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910009440.6A CN109799871A (en) | 2019-01-04 | 2019-01-04 | A kind of high frequency clock signal driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910009440.6A CN109799871A (en) | 2019-01-04 | 2019-01-04 | A kind of high frequency clock signal driving circuit |
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| Publication Number | Publication Date |
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| CN109799871A true CN109799871A (en) | 2019-05-24 |
Family
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|---|---|---|---|
| CN201910009440.6A Pending CN109799871A (en) | 2019-01-04 | 2019-01-04 | A kind of high frequency clock signal driving circuit |
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| CN109120243A (en) * | 2018-07-23 | 2019-01-01 | 中国电子科技集团公司第二十四研究所 | Clock driver circuit |
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2019
- 2019-01-04 CN CN201910009440.6A patent/CN109799871A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201910785U (en) * | 2010-12-24 | 2011-07-27 | 厦门优迅高速芯片有限公司 | PECL (Positive Emitter Coupled Logic) level interface circuit |
| CN203301493U (en) * | 2013-04-28 | 2013-11-20 | 广州展为通讯技术有限公司 | Electrical signal pulse code modulation circuit |
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| US20160056890A1 (en) * | 2014-08-22 | 2016-02-25 | Corning Optical Communications LLC | Active optical cable assemblies and methods for thermal testing thereof |
| WO2017034769A1 (en) * | 2015-08-26 | 2017-03-02 | Qualcomm Incorporated | Systems and methods for rate detection for soundwire\sm extension (soundwire-xl) cables |
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Application publication date: 20190524 |