CN109787630A - Device based on the assessment of atomic clock short-term stability - Google Patents
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Abstract
The invention discloses a kind of devices based on the assessment of atomic clock short-term stability, belong to atomic clock technical field, including cavity bubble system and light source module, A/D sampling unit, optical switch element, detectable signal generation unit, VCXO unit, D/A control unit, logic gate array unit, difference quotient computing unit, gain control unit, relaxation time unit, sampled signal display unit and processor, the processor is communicated by first end and the A/D sampling unit, it is communicated by second end and optical switch element, it is communicated by third end and detectable signal generation unit, it is communicated by the 4th end and VCXO unit, it is communicated by the 5th end and D/A control unit, it is communicated by the 6th end and logic gate array unit, it is communicated by the 7th end and difference quotient computing unit, it is communicated by the 8th end and relaxation time unit.The present invention reaches being capable of the technical effect assessed of the stability short-term to atomic clock.
Description
Technical field
The invention belongs to atomic clock technical field, in particular to a kind of device based on the assessment of atomic clock short-term stability.
Background technique
Atomic clock is a kind of time set, and precision can achieve every 2000 Wan Niancai error 1 second, atomic clock be originally initially by
Physicist creates for exploration of the universe essence.Atomic clock technology can be applied in the navigation system in the whole world.With
The development of atomic clock technology needs to detect the long-term stability and short-term stability of atomic clock output frequency.
For the existing technology assessed based on atomic clock short-term stability, the calibration of atomic frequency is mostly used greatly
The mode of inspection completes assay calibration according to corresponding vertification regulation by metrological service.Temporal frequency measurement criteria has because of it
The characteristic of itself allows to avoid to transmit step by step, carries out remote broadcast and transmission for electromagnetic wave as carrier.But it is difficult
It is assessed with the stability short-term to atomic clock.
In conclusion there is be difficult to atomic clock in the existing technology based on the assessment of atomic clock short-term stability
The technical issues of short-term stability is assessed.
Summary of the invention
The technical problem to be solved by the present invention is to deposit in the existing technology based on the assessment of atomic clock short-term stability
It is being difficult to the technical issues of stability short-term to atomic clock is assessed.
In order to solve the above technical problems, the present invention provides a kind of device based on the assessment of atomic clock short-term stability, institute
Stating the device based on the assessment of atomic clock short-term stability includes cavity bubble system and light source module, the high speed in the light source module
Shutter is ' opening ' state, then the light of light source excitation after high speed Shutter by being directly entered in the cavity bubble system, in original
Under the action of sub- frequency marking principle, the quantum frequency discrimination of quantized system is completed；A/D sampling unit, the A/D sampling unit respectively with institute
It states cavity bubble system and the light source module communicates；Optical switch element, the optical switch element respectively with the cavity bubble system and institute
Light source module is stated to communicate；Detectable signal generation unit, the detectable signal generation unit respectively with the cavity bubble system and described
Light source module communicates；VCXO unit, the VCXO unit and the detectable signal generation unit communicate；D/A control unit, it is described
D/A control unit and the VCXO unit communicate；Logic gate array unit；Difference quotient computing unit；Gain control unit, the increasing
Beneficial control unit and the difference quotient computing unit communicate；Relaxation time unit；Sampled signal display unit, the sampled signal are aobvious
Show that unit and the relaxation time unit communicate；Processor, the processor are provided with first end, second end, third end, the 4th
End, the 5th end, the 6th end, the 7th end, the 8th end, the 9th end, the processor are sampled single by the first end and the A/D
Member communicates, and the processor is communicated by the second end and the optical switch element, and the processor passes through the third end
It is communicated with the detectable signal generation unit, the processor is communicated by the 4th end and the VCXO unit, the place
Reason device is communicated by the 5th end and the D/A control unit, and the processor passes through the 6th end and the logic gate
Array element communicates, and the processor is communicated by the 7th end and the difference quotient computing unit, and the processor passes through institute
It states the 8th end and the relaxation time unit communicates；It is sampling of the signal of the quantum frequency discrimination through the A/D sampling unit, described
The logic gate array unit is sent into after the processing of processor, upper moment light source excitation light penetrates the cavity bubble system, through described
The signal that the sampling of A/D sampling unit generates is high level 1, becomes low level 0 after odd level logic inverter, acts on the light
The high speed Shutter in source module makes its ' pass ' state；After circuiting sequentially, in the defeated of the logic gate array unit
There is 1-0-1 to 0 variation in outlet, is detected by the processor to frequency signal, to obtain corresponding time parameter.
Further, the device based on the assessment of atomic clock short-term stability includes that the logic occurs for the processor
Gate array.
Further, the device based on the assessment of atomic clock short-term stability includes that the processor generates odd level N
A NOT gate, the input terminal of the processor receive the signal from the received A/D sampling of processor.
Further, the device based on the assessment of atomic clock short-term stability includes the output end of the processor through locating
Device feedback is managed to the high-speed optical switch Shutter in the light source of quantized system, to control the on or off of its state.
Further, the device based on the assessment of atomic clock short-term stability includes the external clock end of the processor
The external clock end Input of XTAL and AD9852 accesses the clock signal from voltage controlled crystal oscillator VCXO output, makes DDS's
The stability of IOUT pin output end frequency signal is consistent with external clock reference.
Further, the device based on the assessment of atomic clock short-term stability includes generating odd number by the processor
A NOT gate is serially connected, to generate self-oscillation, so that circuit constitutes a ring oscillator.
Further, the device based on the assessment of atomic clock short-term stability includes the number N of NOT gate in the circuit
For odd number.
Further, when the device based on the assessment of atomic clock short-term stability includes the average transmission of each gate circuit
It is t between delay, the cycle of oscillation that ring oscillator generates is T, if the initial state of certain moment A1 point is 1, passes through 1 transmission delay
After t, A2 point becomes 0, becomes 1 using 1 transmission delay t, A3 point, after the N number of transmission delay Nt of odd number, initial state 1 becomes 0.
The utility model has the advantages that
The present invention provides a kind of device based on the assessment of atomic clock short-term stability, by when the high speed in light source module
Shutter is ' opening ' state, then the light of light source excitation after high speed Shutter by being directly entered in the cavity bubble system, in original
Under the action of sub- frequency marking principle, the quantum frequency discrimination of quantized system is completed.A/D sampling unit respectively with the cavity bubble system and described
Light source module is interconnected；Optical switch element is interconnected with the cavity bubble system and the light source module respectively；Detectable signal
Generation unit is interconnected with the cavity bubble system and the light source module respectively；VCXO unit and the detectable signal generate single
Member is interconnected；D/A control unit and the VCXO unit are interconnected；Gain control unit and the difference quotient computing unit phase
It is intercommunicated；Sampled signal display unit and the relaxation time unit are interconnected；Processor passes through the first end and described
A/D sampling unit is interconnected, and the processor is interconnected by the second end and the optical switch element, the processing
Device is interconnected by the third end and the detectable signal generation unit, and the processor passes through the 4th end and described
VCXO unit is interconnected, and the processor is interconnected by the 5th end and the D/A control unit, the processor
It is interconnected by the 6th end and the logic gate array unit, the processor passes through the 7th end and the difference quotient
Computing unit is interconnected, and the processor is interconnected by the 8th end and the relaxation time unit；The quantum
The signal of frequency discrimination is sent into the logic gate array unit after the sampling of the A/D sampling unit, the processing of the processor, on
Moment light source excitation light penetrates the cavity bubble system, and the signal that the sampling through the A/D sampling unit generates is high level 1, odd
Become low level 0 after several levels logic inverter, act on the high speed Shutter in the light source module, makes its ' pass ' shape
State；After circuiting sequentially, there is 1-0-1 to 0 variation in the output end of the logic gate array unit, pass through the processor
Frequency signal is detected, to obtain corresponding time parameter.To reach can the stability short-term to atomic clock assess
Technical effect.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of schematic diagram 1 of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention；
Fig. 2 is that a kind of signal transmission of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention is shown
It is intended to；
Fig. 3 is a kind of schematic diagram 2 of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention；
Fig. 4 is a kind of microprocessor control of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention
AD9852 modulation circuit functional block diagram processed；
Fig. 5 is a kind of quantized system mirror of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention
The schematic diagram of frequency signal output waveform；
Fig. 6 be it is provided in an embodiment of the present invention it is a kind of based on atomic clock short-term stability assessment device difference quotient curve with
The schematic diagram of absorption curve.
Specific embodiment
The invention discloses a kind of devices based on the assessment of atomic clock short-term stability, by when the high speed in light source module
Shutter is ' opening ' state, then the light of light source excitation after high speed Shutter by being directly entered in the cavity bubble system, in original
Under the action of sub- frequency marking principle, the quantum frequency discrimination of quantized system is completed.A/D sampling unit respectively with the cavity bubble system and described
Light source module is interconnected；Optical switch element is interconnected with the cavity bubble system and the light source module respectively；Detectable signal
Generation unit is interconnected with the cavity bubble system and the light source module respectively；VCXO unit and the detectable signal generate single
Member is interconnected；D/A control unit and the VCXO unit are interconnected；Gain control unit and the difference quotient computing unit phase
It is intercommunicated；Sampled signal display unit and the relaxation time unit are interconnected；Processor passes through the first end and described
A/D sampling unit is interconnected, and the processor is interconnected by the second end and the optical switch element, the processing
Device is interconnected by the third end and the detectable signal generation unit, and the processor passes through the 4th end and described
VCXO unit is interconnected, and the processor is interconnected by the 5th end and the D/A control unit, the processor
It is interconnected by the 6th end and the logic gate array unit, the processor passes through the 7th end and the difference quotient
Computing unit is interconnected, and the processor is interconnected by the 8th end and the relaxation time unit；The quantum
The signal of frequency discrimination is sent into the logic gate array unit after the sampling of the A/D sampling unit, the processing of the processor, on
Moment light source excitation light penetrates the cavity bubble system, and the signal that the sampling through the A/D sampling unit generates is high level 1, odd
Become low level 0 after several levels logic inverter, act on the high speed Shutter in the light source module, makes its ' pass ' shape
State；After circuiting sequentially, there is 1-0-1 to 0 variation in the output end of the logic gate array unit, pass through the processor
Frequency signal is detected, to obtain corresponding time parameter.To reach can the stability short-term to atomic clock assess
Technical effect.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art's every other embodiment obtained belong to what the present invention protected
Range；Wherein "and/or" keyword involved in this implementation, indicate and or two kinds of situations, in other words, the present invention implement
A and/or B mentioned by example, illustrate two kinds of A and B, A or B situations, describe three kinds of states present in A and B, such as A and/or
B, indicate: only including A does not include B；Only including B does not include A；Including A and B.
Meanwhile in the embodiment of the present invention, when component is referred to as " being fixed on " another component, it can be directly at another
On component or there may also be components placed in the middle.When a component is considered as " connection " another component, it be can be directly
It is connected to another component or may be simultaneously present component placed in the middle.When a component is considered as " being set to " another group
Part, it, which can be, is set up directly on another component or may be simultaneously present component placed in the middle.Made in the embodiment of the present invention
Term "vertical", "horizontal", "left" and "right" and similar statement are merely for purposes of illustration, and are not intended to
The limitation present invention.
Referring to Figure 1, Fig. 2 and Fig. 4, Fig. 1 are that a kind of atomic clock short-term stability that is based on provided in an embodiment of the present invention is commented
The schematic diagram 1 for the device estimated；Fig. 2 is a kind of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention
Signal transmits schematic diagram；Fig. 4 is a kind of the micro- of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention
Processor controls AD9852 modulation circuit functional block diagram.The embodiment of the present invention provides a kind of based on the assessment of atomic clock short-term stability
Device, the device based on the assessment of atomic clock short-term stability include cavity bubble system and light source module, A/D sampling unit,
Optical switch element, detectable signal generation unit, VCXO unit, D/A control unit, logic gate array unit, difference quotient computing unit,
Gain control unit, relaxation time unit, sampled signal display unit and processor, now respectively to cavity bubble system and light source die
Block, A/D sampling unit, optical switch element, detectable signal generation unit, VCXO unit, D/A control unit, logic gate array list
Member, difference quotient computing unit, gain control unit, relaxation time unit, sampled signal display unit and processor carry out following detailed
It describes in detail bright:
It is mono- for cavity bubble system, light source module, A/D sampling unit, optical switch element, detectable signal generation unit, VCXO
Member, D/A control unit, logic gate array unit, difference quotient computing unit, gain control unit, relaxation time unit, sampled signal
For display unit:
High speed Shutter in light source module is ' opening ' state, then the light of light source excitation passes through direct after high speed Shutter
Into in the cavity bubble system, under the action of atomic frequency standard principle, the quantum frequency discrimination of quantized system is completed.A/D sampling unit
It is interconnected respectively with the cavity bubble system and the light source module；The optical switch element respectively with the cavity bubble system and institute
Light source module is stated to be interconnected；The detectable signal generation unit is mutually interconnected with the cavity bubble system and the light source module respectively
It is logical；The VCXO unit and the detectable signal generation unit are interconnected；The D/A control unit and the VCXO unit phase
It is intercommunicated；The gain control unit and the difference quotient computing unit are interconnected；The sampled signal display unit and described
Relaxation time unit is interconnected.
Continuing with referring to Fig. 1, the acquisition of atom relaxation time: logic gate array is occurred by processor, it is characterized in that: generating
The N number of NOT gate of odd level, input terminal receive the signal from the received A/D sampling of processor, and output end is anti-through processor
The high-speed optical switch Shutter being fed in the light source of quantized system, to control its state ' opening ' or ' pass '.When according to Fig. 1's
When schematic diagram is started to work, it is assumed that the high speed Shutter in this moment light source module is ' opening ' state, then, light source excitation
Light is directly entered in cavity bubble system after passing through high speed Shutter, under the action of conventional atom frequency marking principle, completes quantized system
Quantum frequency discrimination.Quantum frequency discrimination signal samples through A/D, is sent into logic gate array after processor processing, because light source of upper moment swashs
Encouraging light can be through cavity bubble system, so the signal that generates through A/D sampling of moment is high level ' 1 ', after odd level logic inverter
Become low level ' 0 ', act on the high speed Shutter in light source module, makes its ' pass ' state.It circuits sequentially, in logic gate
The output end of array will appear ' 1 '-' 0 '-' 1 ' ... ' 0 ' variation, by processor to frequency signal detect, we
Obtain corresponding time parameter.
Fig. 3 is referred to, Fig. 3 is a kind of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention
Schematic diagram 2.Odd number NOT gate is generated by microprocessor to be serially connected, can generate self-oscillation, which constitutes a ring
Shape oscillator.It is t, ring oscillator between the mean transit delay of each gate circuit is slow if the number N of NOT gate is odd number in circuit
The cycle of oscillation of generation is T.It is assumed that the initial state of certain moment A1 point is 1, then after 1 transmission delay t, A2 point becomes 0, then passes through
Crossing 1 transmission delay t, A3 point becomes 1 ..., and after the N number of transmission delay Nt of odd number, initial state ' 1 ' becomes ' 0 '.Same reason: just
State ' 0 ' becomes ' 1 '.It is as shown in Figure 2 that signal transmits schematic diagram.According to fig. 2, available formula (1): T0=2Nt.When above-mentioned annular
After oscillator seals in atomic clock system, it can obtain as shown in Figure 3.The signal period that the frequency signal test side of Fig. 3 detects such as
Formula (2): T1=2 (Nt+ Δ t).Wherein, Δ t is the atomic time parameter that we need to know.By formula (1) and
(2), it can be derived from formula (3): Δ t=(T1-T0)/2.Δ t in above formula is extremely important to our further work expansion: root
According to Fig. 1 it is recognised that Δ t is determined by the circuit of quantized system and periphery, and the response time of electronic circuit is very fast
, generally also reach 10nS magnitude or more, so determining that the key of Δ t value should be the quantized system part in Fig. 1.
After the Δ t in the formula that obtains (3), microprocessor just carries out further work: modulating electricity according to conventional atom clock
Road technique does following improvement, in conjunction with Fig. 1, external clock end XTAL and AD9852 (" the detection letter in Fig. 1 of microprocessor
Number generate " in module, " modulation circuit " relative to traditional technology) external clock end Input access from voltage controlled crystal oscillator
The clock signal of VCXO output.Keep the stability of the IOUT pin output end frequency signal of DDS consistent with external clock reference.It is such as defeated
Signal frequency is that the signal frequency of 5.3125MHz or 5.3123MHz so MCLK clock end should be greater than 20MHz out, with expectation
Better phase noise is obtained, after filtered external circuit, purer signal spectrum can be obtained.
FSELECT is keying FM signal input terminal, that is, our modulated square wave signal input part, herein we
The Δ t obtained according to above-mentioned formula (3) is needed to determine the frequency values of square-wave signal here, we are with 5* Δ t time (i.e. 1/ (5*
Δ t) frequency) as our value standard.Such as 1/ (5* Δ t)=79Hz.There are two frequency controls inside the DDS that we use
Frequency value F 0=5.3125MHz, F1=5.3123MHz pre-set is stored in by register processed by way of programming
In register, (i.e. level rising edge or failing edge conversion, the end IOUT of DDS when there is the input of 79Hz square-wave signal at the end FSELECT
The value of F1 or F0 will be read from frequency control register respectively therewith as output, and can ensure that frequency signal is switching
Shi Xiangwei is unchanged.
Fig. 5 is referred to, Fig. 5 is a kind of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention
The schematic diagram of quantized system frequency discrimination signal output waveform.In conjunction with conventional atom clock technical principle, it is added in AD9852 pin FSELECT
To realize that the square wave FM signal frequency of keying frequency modulation decides what kind of speed to switch amount of alignment subcenter frequency on end
The frequency signal of rate or so, due to the presence of the relaxation time of atomic spin, so the keying frequency modulation being added in quantized system is micro-
Wave signal can generate the signal waveform such as Fig. 5 in the A/D sampling end of Fig. 1 after the effect of the frequency discrimination of quantized system.
In the signal waveform of Fig. 5, when conventional circuit design, should be placed on emphasis point in A, B section in figure, because of the area A, B
The exactly region of servo-system progress frequency discrimination signal voltage difference acquisition.In this patent we focus in figure A, B sections it is outer
Concave part, this is the relaxation time t for the atom that we need to solve.
Detailed analysis must be carried out to loop each point signal.According to existing atomic clock technology circuit structure, it is assumed that modulation
Signal is formula (4): S=Asin (2 π ft), then light inspection fundamental wave output is formula (5): S1=ABsin (2 π ft+ φ+φ1), wherein φ
Equal to 0 or 180 degree, φ1It is the phase shift that phase modulation and frequency multiplier circuit introduce.After amplifying by frequency-selecting, signal expression is formula
(6): S2=KaABsin (2 π ft+ φ+φ1+φ2), φ2It is the phase shift of frequency-selective amplifier.Because of the mathematical expression of phase sensitive detection
It is multiplier, after phase-sensitive amplifier, signal is formula (7): S3=KaKpABsin (2 π ft+ φ+φ1+φ2)sin(2π
Ft)=(- 1/2) KaKpAB [cos (4 π ft+ φ+φ1+φ2)-cos(φ+φ1+φ2)], by the filter action of integrator,
AC compounent in phase-sensitive amplifier output will be filtered, and the voltage-controlled voltage finally exported is formula (8): SV=(1/2)
KaKpABcos(φ+φ1+φ2)。
In order to make system worked well and there is maximum gain, it is necessary to phase shifter be added in systems to offset (φ1+
φ2) phase shift.Any reason causes (φ1+φ2) variation, will all cause the change in gain of system, thus generate frequency drift
It moves.Also it is not easy to measurement of this patent to relaxation time τ.According to conventional atom clock technology, in conjunction with Fig. 1, formula (3) and we select
(5* Δ t), in DDS link, (5* Δ t) is generated by processor to the square-wave signal 1/ of keying frequency modulation to the modulating frequency 1/ taken
, then the timing of servo-system acquisition also should generate (we term it synchronization signals) by it, and several signals will be kept
Phase it is adjustable by processor number.(φ in above-mentioned formula (8)1+φ2) extra phase shift will eventually embody synchronization in Fig. 5
The phase change of signal and frequency discrimination signal.Traditional technology can not overcome such problems herein, we pass through in Fig. 1
The information that sampled signal display module can obtain Fig. 5 (wherein contains the (φ in formula (8)1+φ2) extra phase shift), pass through place
Control of the device to relaxation time module is managed, changes the phase of synchronization signal in Fig. 5 particularly to realize to signal display module
The measurement of relaxation time τ in (i.e. Fig. 5).
For processor:
Processor be provided with first end, second end, third end, the 4th end, the 5th end, the 6th end, the 7th end, the 8th end,
9th end, the processor are interconnected by the first end and the A/D sampling unit, and the processor passes through described the
Two ends and the optical switch element are interconnected, and the processor passes through the third end and the detectable signal generation unit phase
Intercommunicated, the processor is interconnected by the 4th end and the VCXO unit, and the processor passes through the described 5th
End and the D/A control unit are interconnected, and the processor is mutual by the 6th end and the logic gate array unit
Connection, the processor are interconnected by the 7th end and the difference quotient computing unit, and the processor passes through described the
Eight ends and the relaxation time unit are interconnected；It is sampling of the signal of the quantum frequency discrimination through the A/D sampling unit, described
The logic gate array unit is sent into after the processing of processor, upper moment light source excitation light penetrates the cavity bubble system, through described
The signal that the sampling of A/D sampling unit generates is high level 1, becomes low level 0 after odd level logic inverter, acts on the light
The high speed Shutter in source module makes its ' pass ' state；After circuiting sequentially, in the defeated of the logic gate array unit
There is 1-0-1 to 0 variation in outlet, is detected by the processor to frequency signal, to obtain corresponding time parameter.
The embodiment of the present invention provides a kind of device based on the assessment of atomic clock short-term stability further include: the processor hair
The raw logic gate array.The processor generates the N number of NOT gate of odd level, and the input terminal of the processor is received from processing
The signal of the received A/D sampling of device.The output end of the processor is fed back through processor to the high speed in the light source of quantized system
Photoswitch Shutter, to control the on or off of its state.The external clock end XTAL of the processor and the external clock of AD9852
End Input accesses the clock signal from voltage controlled crystal oscillator VCXO output, makes the IOUT pin output end frequency signal of DDS
Stability is consistent with external clock reference.Odd number NOT gate is generated by the processor to be serially connected, to generate self-oscillation,
So that circuit constitutes a ring oscillator.The number N of NOT gate is odd number in the circuit.When the average transmission of each gate circuit
It is t between delay, the cycle of oscillation that ring oscillator generates is T, if the initial state of certain moment A1 point is 1, passes through 1 transmission delay
After t, A2 point becomes 0, becomes 1 using 1 transmission delay t, A3 point, after the N number of transmission delay Nt of odd number, initial state 1 becomes 0.
Fig. 6 is referred to, Fig. 6 is a kind of device based on the assessment of atomic clock short-term stability provided in an embodiment of the present invention
The schematic diagram of difference quotient curve and absorption curve.The acquisition of system signal ratio (S/N) parameter and short-term stability assessment is incorporated by reference to figure
1, microprocessor does not modulate the AD9852 chip in detectable signal module at this time, but exports single-frequency, and two frequencies is allowed to post
Frequency values in storage are equal, i.e. F0=F1, but they are not (5.3125MHz) remained unchanged, we pass through in Fig. 1
Processor carries out step motion control to D/A, and the DC level for changing output acts on VCXO, so as to cause because VCXO is as detection
AD9852 chip exterior clock in signaling module changes, and the stepping for further realizing F0=F1 changes.According to existing original
Secondary clock Detection Techniques carry out frequency sweep within the scope of the line width of atom, sample us by A/D and will obtain the absorption curve of atom,
It is calculated in turn by the difference quotient in Fig. 1 and gain control can be with corresponding difference quotient curve, as shown in fig. 6, there is following definition:
Absorption factor:Modulation depth: 2 ε, line width:According to these definition, signal-to-noise ratio S/N theory meter is provided
Calculate formula and system short-term stability assessment formula formula (9):And formula (10):For relevant parameter α, ε, I in formula (9)0, e, Δ f is easily directly or by calculating
It arrives.
It is the gain size in the gain control loop section in Fig. 1 for relevant parameter N in formula (10)；K is in difference quotient curve
Slope value.Wherein:
(1) absorption factor:We are sampled by the frequency sweep of Fig. 1, A/D, and processor records light intensity I in Fig. 6
Minimum point and maximum of points, then being maximized a little as I0, maxima and minima difference be Δ I.
(2) the modulation line width of ε reflection, it is an actual parameter settings, and value range is necessarily less than Atomic absorption song
The line width values of line.ε=0 in frequency sweep, and in actual Closed loop operation (the acquisition link of such as above-mentioned atom relaxation time T, I
Take F0=5.3125MHz, F1=5.3123MHz) take 2 ε=F0-F1=200Hz.
(3) line width:What abscissa identified is the changing value of frequency f in (a) figure of Fig. 6, and actually it remembers
Record the process that D/A in Fig. 1 changes voltage-controlled voltage.Because being D/A and voltage controlled crystal oscillator VCXO output frequency before frequency sweep
Relationship, and record in the processor, and think by D/A export voltage change caused by frequency change in quantized system line width
In range and the rate-adaptive pacemaker of voltage controlled crystal oscillator is linear, thus this can be right directly from the specific voltage value on axis of abscissas
The corresponding frequency of crystal oscillator is answered, according to existing atomic clock technology, this frequency can be total by atom in quantized system of indirect reformer
The frequency values of vibration.According to the scheme of Fig. 1 we handled by difference quotient after can obtain (b) figure in Fig. 6: then A point and B in figure
Point peak-to-peak value, a, b point that will be corresponded in Fig. 6 (a) will remember that 6 (a) abscissa point is entirely processor controlled D/A defeated
Out caused VCXO frequency variation indirect conversion and come, so any point (including a, b point) in abscissa is all by processor
It records.Therefore the frequency interval δ between A point and B pointfFrequency interval f2-f1 between as a point and b point, we are can to know
Road, then line width is calculated as
(4) slope value K.To solve the problems, such as to calculate slope K in practice, we use following methods: passing through processor
The longitudinal axis data of difference quotient curve in Fig. 6 (b) are compared, obtain the maximum value V of Y axis coordinate in difference quotient curveHIt is (B point) and minimum
Value VL(A point), and record this moment corresponding X-axis frequency coordinate HfAnd Lf.They are one-to-one relationships.By above-mentioned
Scheme, in VL-VHIn range, by the judgment method of software select an intermediate value (such as: X-axis one shares 100 points, then selecting
The median point selected is 50), this position to be set to origin (0,0), puts respectively take identical point (example to the left and right side of X-axis respectively according to this
Such as take 20 points), formula (11): V=a+Kx+j are carried out the following processing to this 41 point datas.Wherein K be we require it is oblique
Rate value, a are unknown constants, and j is random error, it indicates the combined influence of many factors not accounted for, it is believed that Ej=
0。
To each point (xi, Vi), formula (12) should be met according to formula (11):: Vi=a+Kxi+j
(i=1,2, n).IfIt is our required estimations, then we always wish each point (xi, Vi) with
Deviation between line V=a+Kx is small as far as possible.In x=xiPlace, (xi, Vi) and straight line V=a+Kx between deviation be formula
(13): Δ Vi=Vi-(a+Kxi) (i=1,2, n).Here there is the deviation of n point, it should comprehensively consider, it is clear that I
Cannot be indicated with algebraical sum because deviation has just and has negative, their algebraical sum will appear positive and negative offset and cannot represent
Real total deviation.If summing again after taking absolute value, it is clear that can be to avoid this disadvantage, but be not easy to make mathematical operation, institute
To indicate total deviation formula (14) using sum of square of deviations:
MakeReach minimum, as a, the estimation of K.Due toIt is a, K's
Non-negative quadratic function, this minimum certainly exist.Known by calculus, is madeReach minimum a, K should meet following agenda
Group formula (15):
After arrangement, formula (16) can be obtained:
If noteFormula (17) can then be obtained:And formula
(18):Here it acquiresIt is exactly slope value K required for us.
(5) gain N.It can be directly configured from Fig. 1 principle, usual value range is 10-30.
The present invention provides a kind of device based on the assessment of atomic clock short-term stability, by when the high speed in light source module
Shutter is ' opening ' state, then the light of light source excitation after high speed Shutter by being directly entered in the cavity bubble system, in original
Under the action of sub- frequency marking principle, the quantum frequency discrimination of quantized system is completed.A/D sampling unit respectively with the cavity bubble system and described
Light source module is interconnected；Optical switch element is interconnected with the cavity bubble system and the light source module respectively；Detectable signal
Generation unit is interconnected with the cavity bubble system and the light source module respectively；VCXO unit and the detectable signal generate single
Member is interconnected；D/A control unit and the VCXO unit are interconnected；Gain control unit and the difference quotient computing unit phase
It is intercommunicated；Sampled signal display unit and the relaxation time unit are interconnected；Processor passes through the first end and described
A/D sampling unit is interconnected, and the processor is interconnected by the second end and the optical switch element, the processing
Device is interconnected by the third end and the detectable signal generation unit, and the processor passes through the 4th end and described
VCXO unit is interconnected, and the processor is interconnected by the 5th end and the D/A control unit, the processor
It is interconnected by the 6th end and the logic gate array unit, the processor passes through the 7th end and the difference quotient
Computing unit is interconnected, and the processor is interconnected by the 8th end and the relaxation time unit；The quantum
The signal of frequency discrimination is sent into the logic gate array unit after the sampling of the A/D sampling unit, the processing of the processor, on
Moment light source excitation light penetrates the cavity bubble system, and the signal that the sampling through the A/D sampling unit generates is high level 1, odd
Become low level 0 after several levels logic inverter, act on the high speed Shutter in the light source module, makes its ' pass ' shape
State；After circuiting sequentially, there is 1-0-1 to 0 variation in the output end of the logic gate array unit, pass through the processor
Frequency signal is detected, to obtain corresponding time parameter.To reach can the stability short-term to atomic clock assess
Technical effect.
It should be noted last that the above specific embodiment is only used to illustrate the technical scheme of the present invention and not to limit it,
Although being described the invention in detail referring to example, those skilled in the art should understand that, it can be to the present invention
Technical solution be modified or replaced equivalently, without departing from the spirit and scope of the technical solution of the present invention, should all cover
In the scope of the claims of the present invention.
Claims (8)
1. a kind of device based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atomic clock short-term stability
The device of assessment includes:
Cavity bubble system and light source module, the high speed Shutter in the light source module is ' opening ' state, then the light of light source excitation is logical
It is directly entered in the cavity bubble system after crossing high speed Shutter, under the action of atomic frequency standard principle, completes the amount of quantized system
Sub- frequency discrimination；
A/D sampling unit, the A/D sampling unit are communicated with the cavity bubble system and the light source module respectively；
Optical switch element, the optical switch element are communicated with the cavity bubble system and the light source module respectively；
Detectable signal generation unit, the detectable signal generation unit respectively with the cavity bubble system and the light source module phase
It is logical；
VCXO unit, the VCXO unit and the detectable signal generation unit communicate；
D/A control unit, the D/A control unit and the VCXO unit communicate；
Logic gate array unit；
Difference quotient computing unit；
Gain control unit, the gain control unit and the difference quotient computing unit communicate；
Relaxation time unit；
Sampled signal display unit, the sampled signal display unit and the relaxation time unit communicate；
Processor, the processor be provided with first end, second end, third end, the 4th end, the 5th end, the 6th end, the 7th end,
8th end, the 9th end, the processor are communicated by the first end and the A/D sampling unit, and the processor passes through institute
It states second end and the optical switch element communicates, the processor passes through the third end and the detectable signal generation unit phase
Logical, the processor is communicated by the 4th end and the VCXO unit, and the processor passes through the 5th end and described
D/A control unit communicates, and the processor is communicated by the 6th end and the logic gate array unit, and the processor is logical
It crosses the 7th end and the difference quotient computing unit communicates, the processor passes through the 8th end and the relaxation time unit
It communicates；The signal of the quantum frequency discrimination is sent into the logic after the sampling of the A/D sampling unit, the processing of the processor
Gate array unit, upper moment light source excitation light penetrate the cavity bubble system, the signal that the sampling through the A/D sampling unit generates
It is high level 1, becomes low level 0 after odd level logic inverter, acts on the high speed Shutter in the light source module,
Make its ' pass ' state；After circuiting sequentially, there is 1-0-1 to 0 variation in the output end of the logic gate array unit, lead to
It crosses the processor to detect frequency signal, to obtain corresponding time parameter.
2. the device as described in claim 1 based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atom
Clock short-term stability assessment device include:
The logic gate array occurs for the processor.
3. the device as claimed in claim 2 based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atom
Clock short-term stability assessment device include:
The processor generates the N number of NOT gate of odd level, and the input terminal reception of the processor is adopted from the received A/D of processor
The signal of sample.
4. the device as claimed in claim 3 based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atom
Clock short-term stability assessment device include:
The output end of the processor is fed back through processor to the high-speed optical switch Shutter in the light source of quantized system, to
Control the on or off of its state.
5. the device as claimed in claim 4 based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atom
Clock short-term stability assessment device include:
The external clock end Input of the external clock end XTAL and AD9852 of the processor are accessed from voltage controlled crystal oscillator VCXO
The clock signal of output keeps the stability of the IOUT pin output end frequency signal of DDS consistent with external clock reference.
6. the device as claimed in claim 5 based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atom
Clock short-term stability assessment device include:
It generates odd number NOT gate by the processor to be serially connected, to generate self-oscillation, so that circuit constitutes a ring
Shape oscillator.
7. the device as claimed in claim 6 based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atom
Clock short-term stability assessment device include:
The number N of NOT gate is odd number in the circuit.
8. the device as claimed in claim 7 based on the assessment of atomic clock short-term stability, which is characterized in that described to be based on atom
Clock short-term stability assessment device include:
It is t between the mean transit delay of each gate circuit is slow, the cycle of oscillation that ring oscillator generates is T, if certain moment A1 point
Initial state be 1, then after 1 transmission delay t, A2 point becomes 0, becomes 1 using 1 transmission delay t, A3 point, odd number is N number of
After transmission delay Nt, initial state 1 becomes 0.
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