CN109786228B - Method for forming alignment mark - Google Patents
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- CN109786228B CN109786228B CN201910059988.1A CN201910059988A CN109786228B CN 109786228 B CN109786228 B CN 109786228B CN 201910059988 A CN201910059988 A CN 201910059988A CN 109786228 B CN109786228 B CN 109786228B
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Abstract
The invention provides a method for forming an alignment mark, which comprises the following steps: forming a plurality of first metal connection posts and at least one second metal connection post on a substrate; forming a patterned oxide layer of a first alignment region and a patterned oxide layer of a second alignment region and a first oxide connection post; forming a third metal connection post on the first oxide connection post and a fourth metal connection post on the oxide layer of the second alignment region, wherein the ratio of the distance from the upper surface of the third metal connection post to the surface of the patterned oxide layer of the first alignment region to the distance between adjacent third metal connection posts is less than 1: 1; and forming a second oxide layer on the patterned oxide layer, the third metal connecting column and the fourth connecting column, and forming a groove on the surface of the second oxide layer to be used as an alignment mark. The alignment mark is formed at the same time of forming the MEMS and CMOS interconnection layers directly, so that materials and time can be saved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming an alignment mark.
Background
CMOS is a part of the digital circuit, Micro Electro Mechanical System (MEMS) is an industrial technology that combines micro electronic technology with mechanical engineering, its operation range is in the micrometer range, nowadays, the micro electro mechanical system (AMR MEMS) manufactured by using Anisotropic Magnetoresistance (AMR) effect of FeN i has high sensitivity, good thermal stability, low material cost, simple preparation process, has already been widely used, it is now possible that MEMS and CMOS can be combined, therefore, the interconnection of MEMS and CMOS is involved, and the interconnection needs alignment mark as an assistant.
In the prior art, there are two methods for forming alignment marks for interconnection of MEMS and CMOS, the first method is that the CMOS itself is divided into multiple layers, each layer has an alignment mark, if an MEMS device is formed on the plane of the CMOS and the MEMS device needs to be aligned with the CMOS, an additional layer of through holes and a layer of metal are required to be connected with the alignment mark of the MEMS device, and an additional metal layer is required to form the MEMS alignment mark. The second method is to directly open the surface of the CMOS to expose the original self alignment mark of the CMOS, and the MEMS will use this alignment mark as a reference to realize the interconnection between the self device and the top metal of the CMOS.
However, in the first method of the prior art, an additional layer of via and a layer of metal are required to be added, and alignment marks of subsequent layers are formed at the same time, and in the second method, an additional non-etching layer is required to be added, and alignment marks of CMOS are opened.
Disclosure of Invention
The invention aims to provide a method for forming an alignment mark, which does not need an additional process to form an MEMS and CMOS interconnection alignment mark and saves cost and time.
In order to achieve the above object, the present invention provides a method of forming an alignment mark, comprising:
providing a substrate;
forming a first metal layer on the substrate, and etching the first metal layer to form a patterned first metal layer, wherein the patterned first metal layer comprises a first alignment region and a second alignment region, the first alignment region comprises a plurality of first metal connection columns, and the second alignment region comprises at least one second metal connection column;
forming a first oxide layer on the patterned first metal layer, etching the first oxide layer to form a patterned oxide layer, wherein the patterned oxide layer comprises a first oxide layer which is formed by removing the first metal connecting column intervals in the first alignment region, a first oxide connecting column on the first metal connecting column, and a first oxide layer which covers the second alignment region, and etching the first oxide layer which covers the second alignment region to expose the second metal connecting column to form a plurality of first through holes;
forming a second metal layer on the patterned oxide layer, etching the second metal layer to form a patterned second metal layer, wherein the patterned second metal layer comprises a second metal layer with a first oxide connecting column interval removed, a third metal connecting column formed on the first oxide connecting column, a part of the second metal layer covering the second alignment area on the first oxide layer, and a fourth metal connecting column which is reserved and corresponds to the second metal connecting column of the second alignment area, and the ratio of the distance from the upper surface of the third metal connecting column to the surface of the patterned oxide layer of the first alignment area to the distance between the adjacent third metal connecting columns is less than 1: 1;
forming a second oxide layer on the patterned second metal layer, the third metal connecting column and the fourth metal connecting column, and forming a groove on the second oxide layer at the position corresponding to the third metal connecting column spacer region to be used as a device alignment mark;
and etching the second oxide layer to expose the fourth metal connecting column and form a second through hole which is used as a through hole for interconnection of devices.
Optionally, in the method for forming the alignment mark, the substrate is a CMOS device, the CMOS device includes a contact hole, and the first metal connection pillar is located on the contact hole.
Optionally, in the method for forming an alignment mark, a thickness of the patterned oxide layer of the first alignment region is smaller than a height of the first metal connection pillar.
Optionally, in the method for forming an alignment mark, the shape and the width of the first metal connection pillar, the first oxide connection pillar and the third metal connection pillar are the same.
Optionally, in the method for forming an alignment mark, a height of the patterned oxide layer of the second alignment region is the same as a sum of heights of the first metal connection pillar and the second oxide connection pillar.
Optionally, in the method for forming an alignment mark, after a plurality of first through holes are formed, the method for forming an alignment mark further includes filling metal into the first through holes.
Optionally, in the method for forming an alignment mark, the alignment mark downwardly corresponds to a middle position of two adjacent third metal connection pillars.
Optionally, in the method for forming the alignment mark, the etching method is dry etching.
Optionally, in the method for forming an alignment mark, a material of the first metal layer and the second metal layer includes aluminum.
Optionally, in the method for forming an alignment mark, the material of the first oxide layer and the second oxide layer includes silicon oxide.
In the method for forming the alignment mark provided by the invention, the whole substrate is divided into a first alignment area and a second alignment area, a plurality of third metal connecting columns are formed in the first alignment area while a contact hole for connection is formed in the second alignment area, a second oxide layer is formed on the substrate and the third metal connecting columns, and a hole is formed between the third metal connecting columns in the first alignment area by the second oxide layer and can be used as the alignment mark. Compared with the prior art method I and the prior art method II, the method can save more materials and time.
Drawings
FIG. 1 is a flow chart of a method of forming an alignment mark according to an embodiment of the present invention;
fig. 2 to 8 are schematic structural diagrams illustrating a method of forming an alignment mark according to an embodiment of the invention;
in the figure: 110-a first metal connection stud, 111-a first metal connection stud, 112-a second metal connection stud, 120-a patterned oxide layer, 121-a patterned oxide layer of a first alignment area, 122-a patterned oxide layer of a second alignment area, 130-a first oxide connection stud, 140-a first via, 150-a second metal layer, 161-a third metal connection stud, 162-a fourth metal connection stud, 170-a second oxide layer, 180-a recess, 190-a second via, 200-a MEMS device.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the present invention provides a method of forming an alignment mark, including:
s11: providing a substrate;
s12: forming a first metal layer on the substrate, and etching the first metal layer to form a patterned first metal layer, wherein the patterned first metal layer comprises a first alignment region and a second alignment region, the first alignment region comprises a plurality of first metal connection columns, and the second alignment region comprises at least one second metal connection column;
s13: forming a first oxide layer on the patterned first metal layer, etching the first oxide layer to form a patterned oxide layer, wherein the patterned oxide layer comprises a first oxide layer which is formed by removing the first metal connecting column intervals in the first alignment region, a first oxide connecting column on the first metal connecting column, and a first oxide layer which covers the second alignment region, and etching the first oxide layer which covers the second alignment region to expose the second metal connecting column to form a plurality of first through holes;
s14: forming a second metal layer on the patterned oxide layer, etching the second metal layer to form a patterned second metal layer, wherein the patterned second metal layer comprises a second metal layer with a first oxide connecting column interval removed, a third metal connecting column formed on the first oxide connecting column, a part of the second metal layer covering the second alignment area on the first oxide layer, and a fourth metal connecting column which is reserved and corresponds to the second metal connecting column of the second alignment area, and the ratio of the distance from the upper surface of the third metal connecting column to the surface of the patterned oxide layer of the first alignment area to the distance between the adjacent third metal connecting columns is less than 1: 1;
s15: forming a second oxide layer on the patterned second metal layer, the third metal connecting column and the fourth metal connecting column, and forming a groove on the second oxide layer at the position corresponding to the third metal connecting column spacer region to be used as a device alignment mark;
s16: and etching the second oxide layer to expose the fourth metal connecting column and form a second through hole which is used as a through hole for interconnection of devices.
First, referring to fig. 2, a substrate is provided, where the substrate is a CMOS device, the CMOS device includes a plurality of contact holes, a first metal layer is formed on the substrate, and a metal may be selected from aluminum, and then the first metal layer is etched to form a plurality of first metal connection pillars 111 and at least one second metal connection pillar 112, where the first metal connection pillars 111 and the second metal connection pillar 112 divide the patterned first metal layer into a first alignment region and a second alignment region. In this embodiment, the 3 first metal connection posts 111 on the left side are used to form the subsequent alignment marks for the CMOS and MEMS alignment, and the 3 first metal connection posts 111 are formed on the contact holes of the CMOS. The second metal connection post 112 on the right is used for subsequent CMOS and MEMS interconnects.
Next, referring to fig. 3, a first oxide layer is formed on the first metal connection post 111, the second metal connection post 112 and the substrate, the first oxide layer is etched to form a patterned oxide layer 120, a portion of the first oxide layer spaced apart from the first metal connection post 111 in the first alignment region is removed, a first oxide connection post 130 on the first metal connection post 111 is formed, and the first oxide connection post 130 and the first metal connection post 111 have the same shape and width. Meanwhile, the first oxide layer of the second alignment region is etched to form a plurality of first via holes 140, and the first via holes 140 are filled with metal, for example, aluminum. Wherein the patterned oxide layer 120 includes: a patterned oxide layer 121 of a first alignment region and a patterned oxide layer 122 of a second alignment region. The first alignment area of the patterned oxide layer 121 has a thickness that is less than the thickness of the first metal connection stud 111, and the second alignment area of the patterned oxide layer 122 has an upper surface aligned with the upper surface of the first oxide connection stud 130.
Next, referring to fig. 4 and 5, a second metal layer 150 is deposited, the second metal layer 150 is etched to form a third metal connection post 161 and a fourth metal connection post 162, the third metal connection post 161 is aligned with the first oxide connection post 130 and has the same shape and width as the first oxide connection post 130, and the fourth metal connection post 162 is positioned above the first via 140 and is aligned with the second metal connection post 112 and has the same shape and width as the second metal connection post 112. During the entire process, the ratio of the distance from the upper surface of the third metal connection post 161 to the surface of the patterned oxide layer 121 of the first alignment region to the distance between adjacent third metal connection posts 161 is less than 1: 1. The above-mentioned ratio relationship can deposit oxide on the surface of the patterned oxide layer 121 of the first alignment region and cover the third metal connection post 161, and the oxide layer of the third metal connection post 161 can have a hole, which can be used as an alignment mark.
Next, referring to fig. 6, a second oxide layer 170 is deposited to cover the third metal connection post 161, the fourth metal connection post 162 and the patterned oxide layer 120, a plurality of holes are formed on the surface of the second oxide layer 170 downward corresponding to the space region of the third metal connection post 161, a plurality of grooves 180 are formed by chemical mechanical polishing, and finally, a plurality of grooves 180 are formed on the entire surface of the second oxide layer 170, and the plurality of grooves 180 can be used as alignment marks for subsequent MEMS and CMOS alignment. Compared with the prior art, the method has the advantages that the interconnection alignment mark is formed while the MEMS and CMOS interconnection layers are manufactured, the process for additionally forming the alignment mark is reduced, and the time and the cost are saved.
Referring to fig. 7 and 8, the MEMS device 200 is a portion of the MEMS device to be interconnected with the CMOS, and is attached to the surface of the second oxide layer 170, and the recess 180 is used as an alignment mark. The second oxide layer 170 on the fourth metal connection pillar 162 is opened using dry etching to form a second via 190, thereby achieving interconnection of the CMOS device and the MEMS device.
In the embodiment of the invention, the etching method can use dry etching, the first oxide layer and the second oxide layer can be made of silicon oxide, and the first metal layer and the second metal layer can be made of aluminum.
In summary, in the method for forming an alignment mark according to the embodiments of the present invention, the entire substrate is divided into the first alignment area and the second alignment area, the plurality of third metal connection pillars are formed in the first alignment area while the contact holes for connection are formed in the second alignment area, the second oxide layer is formed on the substrate and on the third metal connection pillars, the second oxide layer forms the holes between the third metal connection pillars in the first alignment area, and the holes can be used as alignment marks. Compared with the prior art method I and the prior art method II, the method can save more materials and time.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of forming an alignment mark, comprising:
providing a substrate;
forming a first metal layer on the substrate, and etching the first metal layer to form a patterned first metal layer, wherein the patterned first metal layer comprises a first alignment region and a second alignment region, the first alignment region comprises a plurality of first metal connection columns, and the second alignment region comprises at least one second metal connection column;
forming a first oxide layer on the patterned first metal layer, etching the first oxide layer to form a patterned oxide layer, wherein the patterned oxide layer comprises a first oxide layer which removes the first metal connection column interval in a first alignment area, a first oxide connection column on the first metal connection column, and a first oxide layer which covers a second alignment area, and the first oxide layer which covers the second alignment area is etched to expose a second metal connection column to form a plurality of first through holes;
forming a second metal layer on the patterned oxide layer, etching the second metal layer to form a patterned second metal layer, wherein the patterned second metal layer comprises a second metal layer with a first oxide connecting column interval removed, a third metal connecting column formed on the first oxide connecting column, a part of the second metal layer covering the second alignment area on the first oxide layer, and a fourth metal connecting column which is reserved and corresponds to the second metal connecting column of the second alignment area, and the ratio of the distance from the upper surface of the third metal connecting column to the surface of the patterned oxide layer of the first alignment area to the distance between the adjacent third metal connecting columns is less than 1: 1;
forming a second oxide layer on the patterned second metal layer, the third metal connecting column and the fourth metal connecting column, and forming a groove on the second oxide layer at the position corresponding to the third metal connecting column spacer region to be used as a device alignment mark;
and etching the second oxide layer to expose the fourth metal connecting column and form a second through hole which is used as a through hole for interconnection of devices.
2. The method of claim 1, wherein the substrate is a CMOS device having a contact hole therein, and wherein the first metal connection stud is located over the contact hole.
3. The method of claim 1, wherein a thickness of the patterned oxide layer of the first alignment region is less than a height of the first metal connection stud.
4. The method of forming an alignment mark of claim 1 wherein said first metal connection post, said first oxide connection post and said third metal connection post are all the same shape and width.
5. The method of forming an alignment mark of claim 1 wherein a height of the patterned oxide layer of the second alignment region is the same as a sum of heights of the first metal connection post and the first oxide connection post.
6. The method of forming an alignment mark according to claim 1, wherein after forming the plurality of first vias, the method of forming an alignment mark further comprises filling metal into the first vias.
7. The method of claim 1, wherein the alignment mark is downward corresponding to a middle position of two adjacent third metal connection posts.
8. The method of forming an alignment mark according to claim 1, wherein the etching methods are all dry etching.
9. The method of forming an alignment mark of claim 1, wherein the material of the first metal layer and the second metal layer comprises aluminum.
10. The method of forming an alignment mark of claim 1, wherein the material of the first oxide layer and the second oxide layer comprises silicon oxide.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1495540A (en) * | 2002-09-20 | 2004-05-12 | Asml荷兰有限公司 | Alignment system of photoetching system utilizing at least two wavelengths and its method |
| CN1893012A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Three dimensional ic device and alignment methods of ic device substrates |
| US9496230B1 (en) * | 2015-04-30 | 2016-11-15 | International Business Machines Corporation | Light sensitive switch for semiconductor package tamper detection |
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| CN105819395B (en) * | 2015-01-09 | 2017-09-05 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| KR102475449B1 (en) * | 2016-06-09 | 2022-12-08 | 주식회사 디비하이텍 | Wafer with align key and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1495540A (en) * | 2002-09-20 | 2004-05-12 | Asml荷兰有限公司 | Alignment system of photoetching system utilizing at least two wavelengths and its method |
| CN1893012A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Three dimensional ic device and alignment methods of ic device substrates |
| US9496230B1 (en) * | 2015-04-30 | 2016-11-15 | International Business Machines Corporation | Light sensitive switch for semiconductor package tamper detection |
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