CN109783143B

CN109783143B - Control method and control device for pipelined instruction streams

Info

Publication number: CN109783143B
Application number: CN201910075147.XA
Authority: CN
Inventors: 张然; 姚永斌
Original assignee: Guizhou Huaxintong Semiconductor Technology Co ltd
Current assignee: Guizhou Huaxin Information Technology Co ltd
Priority date: 2019-01-25
Filing date: 2019-01-25
Publication date: 2021-03-09
Anticipated expiration: 2039-01-25
Also published as: CN109783143A

Abstract

A control method and control apparatus for a pipelined instruction stream are provided. The control method comprises the following steps: determining whether the current instruction is a single-jump branch instruction, the single-jump branch instruction being an instruction that is only able to jump to a single branch destination address at the time of the jump; if the current instruction is determined to be a single jump branch instruction, accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address corresponding to the current instruction; determining whether the current instruction jumps according to the current branch prediction table, and determining whether a first associated instruction associated with the instruction address jumps according to the advanced branch prediction table; when the current instruction is determined to jump, the first associated instruction is fetched from a branch instruction trace cache, and an operation instruction address corresponding to the first associated instruction is fetched to perform control. Can improve and get and indicate efficiency, reduce the assembly line bubble.

Description

Control method and control device for pipelined instruction streams

Technical Field

The present disclosure relates to a control method and a control apparatus for a pipelined instruction stream.

Background

To improve the efficiency of the processor in executing instructions, pipelining is introduced. At this point, only one instruction is no longer running in the processor, and each stage of the pipeline is running a different instruction at the same time. For example, a typical five-stage pipeline is divided into five stages, namely: 1. fetch (fetch) stage: fetching an instruction from a memory; 2. instruction decode/read register (decode) stage: reading out the value of the register from the register file; 3. execute operation/compute address (execute) phase: performing arithmetic logic operation and calculating the address of a memory; 4. memory (memory) phase: reading/writing data from/to the memory; 5. write-back phase: the data is written back to the register file. The process of program execution is greatly accelerated because pipelining increases the instruction throughput of the processor, i.e., the number of instructions executed per unit time.

The time that the processor waits (i.e., stalls) is called a pipeline bubble (bubble). Branch instructions can introduce bubbles into the processor's pipeline, degrading the processor's performance. The bubbles introduced by the branch instructions into the pipeline of the processor are composed of two parts, namely, the bubbles introduced by jump prediction and the bubbles introduced by address redirection. When a processor that includes pipelining processes a branch instruction, depending on the difference in the true/false decision conditions, the processor may need to perform a jump operation, which interrupts the processing of the instruction in the pipeline because the processor cannot determine what the next instruction of the instruction is until the branch instruction is completely executed (jump prediction introduces a bubble). Sequential instructions that are already in the pipeline are invalid and need to be flushed, and it takes time for the processor to re-pipeline, i.e., the processor must wait for the branch instruction to complete before the next instruction (bubble introduced by address redirection) into the pipeline can be determined. This affects the efficiency of the processor.

Branch instruction prediction techniques are currently introduced. The technology is that a processor predicts the processing result of a branch instruction and obtains a jump address in advance, so that the instruction corresponding to the jump address is loaded on a pipeline, and bubbles introduced by address redirection are relieved to a certain extent.

Disclosure of Invention

At least one embodiment of the present disclosure provides a control method and a control apparatus for a pipeline instruction stream, which can improve instruction fetching efficiency, reduce bubbles introduced by address redirection of a current branch, and reduce bubbles introduced by jump prediction of a next branch, for instruction streams of consecutive jumps.

In a first aspect, the present disclosure provides a control method for a pipelined instruction stream, the control method comprising: determining whether the current instruction is a single-jump branch instruction, the single-jump branch instruction being an instruction that is only able to jump to a single branch destination address at the time of the jump; if the current instruction is determined to be a single jump branch instruction, accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address corresponding to the current instruction; determining whether the current instruction jumps according to the current branch prediction table, and determining whether a first associated instruction associated with the instruction address jumps according to the advanced branch prediction table; when the current instruction is determined to jump, the first associated instruction is fetched from a branch instruction trace cache, and an operation instruction address corresponding to the first associated instruction is fetched to perform control.

With reference to the first aspect, in an implementation manner of the first aspect, the control method further includes: if the first associated instruction is determined to jump, obtaining the operating instruction address corresponding to the first associated instruction comprises obtaining the jump instruction address of the first associated instruction from the branch instruction trace cache; and if it is determined that the first associated instruction does not jump, fetching an operating instruction address corresponding to the first associated instruction comprises fetching a sequential instruction address of the first associated instruction from the branch instruction trace cache.

With reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the determining whether the current instruction is a branch instruction of a single jump includes: predecoding a current instruction prior to fetching the instruction; a determination is made as to whether the current instruction is a single jump branch instruction based on the results of the pre-decoding.

With reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the control method further includes: if it is determined from the results of the pre-decoding that the current instruction is not a single jump branch instruction, the control method is not executed.

With reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the control method further includes: if the first associated instruction cannot be fetched from the branch instruction trace cache upon determining that a jump has occurred to the current instruction, an entry associated with the current instruction is created.

With reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the creating an entry related to the current instruction includes: storing the first associated instruction in the branch instruction trace cache; storing a sequential instruction address of the first associated instruction in the branch instruction trace cache; if the first associated instruction is a single jump branch instruction, storing a jump instruction address of the first associated instruction in the branch instruction trace cache.

With reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the control method further includes: updating the current branch prediction table and a look-ahead branch prediction table based on execution of the current instruction and the first associated instruction.

In a second aspect, the present disclosure provides a control apparatus for pipelined instruction flow, the control apparatus comprising a memory, a processor, and a branch instruction trace cache, wherein the memory is to store program code; the processor is configured to perform the following operations when executing the program code: determining whether the current instruction is a single-jump branch instruction, the single-jump branch instruction being an instruction that is only able to jump to a single branch destination address at the time of the jump; if the current instruction is determined to be a single jump branch instruction, accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address corresponding to the current instruction; determining whether the current instruction jumps according to the current branch prediction table, and determining whether a first associated instruction associated with the instruction address jumps according to the advanced branch prediction table; when the current instruction is determined to jump, acquiring the first associated instruction from the branch instruction trace cache, and acquiring an operation instruction address corresponding to the first associated instruction to execute control; and the branch instruction tracking cache is used for storing the first association instruction and an operation instruction address corresponding to the first association instruction.

With reference to the second aspect, in one implementation manner of the second aspect, if it is determined that the first associated instruction jumps, acquiring the operation instruction address corresponding to the first associated instruction includes the processor acquiring the jump instruction address of the first associated instruction from the branch instruction trace cache; and if it is determined that the first associated instruction does not jump, fetching an operating instruction address corresponding to the first associated instruction comprises the processor fetching a sequential instruction address of the first associated instruction from the branch instruction trace cache.

With reference to the second aspect and the foregoing implementation manner of the second aspect, in another implementation manner of the second aspect, the determining whether the current instruction is a branch instruction of a single jump includes: the processor pre-decodes a current instruction prior to fetching the instruction; the processor determines from the results of the pre-decoding whether the current instruction is a single jump branch instruction.

With reference to the second aspect and its implementations described above, in another implementation of the second aspect, the processor does not perform the operation if it is determined from the results of the pre-decoding that the current instruction is not a single-jump branch instruction.

With reference to the second aspect and the foregoing implementation manner, in another implementation manner of the second aspect, if the processor cannot obtain the first associated instruction from the branch instruction trace cache when determining that the current instruction jumps, the processor establishes an entry related to the current instruction.

With reference to the second aspect and the foregoing implementation manner of the second aspect, in another implementation manner of the second aspect, the establishing, by the processor, an entry related to the current instruction includes: the processor storing the first associated instruction in the branch instruction trace cache; the processor storing a sequential instruction address of the first associated instruction in the branch instruction trace cache; if the first associated instruction is a single-jump branch instruction, the processor stores a jump instruction address of the first associated instruction in the branch instruction trace cache.

With reference to the second aspect and the foregoing implementation manner of the second aspect, in another implementation manner of the second aspect, the processor further updates the current branch prediction table and the advanced branch prediction table according to execution of the current instruction and the first associated instruction.

In a third aspect, the present disclosure provides a control apparatus for a pipelined instruction stream, the control apparatus comprising: an instruction determination unit to determine whether a current instruction is a single-jump branch instruction, the single-jump branch instruction being an instruction capable of jumping to only a single branch destination address at the time of a jump; an access unit for accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address corresponding to the current instruction when the instruction determination unit determines that the current instruction is a single-jump branch instruction; a jump determining unit, configured to determine whether the current instruction jumps according to the current branch prediction table, and determine whether a first associated instruction associated with the instruction address jumps according to the advanced branch prediction table; a fetch unit, configured to fetch the first associated instruction from a branch instruction trace cache and fetch an operation instruction address corresponding to the first associated instruction to perform control when the jump determination unit determines that the current instruction is jumped.

With reference to the third aspect, in an implementation manner of the third aspect, if it is determined that the first associated instruction jumps, acquiring the operation instruction address corresponding to the first associated instruction includes the acquiring unit acquiring the jump instruction address of the first associated instruction from the branch instruction trace cache; and if it is determined that the first associated instruction does not jump, fetching an operating instruction address corresponding to the first associated instruction comprises the fetch unit fetching a sequential instruction address of the first associated instruction from the branch instruction trace cache.

With reference to the third aspect and the foregoing implementation manner of the third aspect, in another implementation manner of the third aspect, the determining whether the current instruction is a branch instruction of a single jump includes: the instruction determination unit pre-decodes a current instruction prior to fetching the instruction; the instruction determination unit determines whether the current instruction is a single-jump branch instruction based on the results of the pre-decoding.

With reference to the third aspect and the foregoing implementation manner, in another implementation manner of the third aspect, if the instruction determination unit determines that the current instruction is not a branch instruction of a single jump according to the result of pre-decoding, the access unit does not access the current branch prediction table and the advanced branch prediction table, the jump determination unit does not perform a jump determination operation, and the fetch unit does not perform a fetch operation.

With reference to the third aspect and the foregoing implementation manner, in another implementation manner of the third aspect, the control device further includes a building unit, and if the obtaining unit cannot obtain the first associated instruction from the branch instruction tracking cache when it is determined that the current instruction jumps, the building unit builds an entry related to the current instruction.

With reference to the third aspect and the foregoing implementation manner of the third aspect, in another implementation manner of the third aspect, the creating unit creating an entry related to the current instruction includes: storing the first associated instruction in the branch instruction trace cache; storing a sequential instruction address of the first associated instruction in the branch instruction trace cache; if the first associated instruction is a single jump branch instruction, storing a jump instruction address of the first associated instruction in the branch instruction trace cache.

With reference to the third aspect and the foregoing implementation manner of the third aspect, in another implementation manner of the third aspect, the creation unit further updates the current branch prediction table and a look-ahead branch prediction table according to execution of the current instruction and the first associated instruction.

According to the control method and the control device for the pipeline instruction stream, aiming at the instruction stream of continuous jump, the jump target instruction of the current single jump branch instruction can be obtained, the subsequent instruction fetching address corresponding to the jump target instruction can be obtained, the instruction fetching efficiency can be improved, bubbles introduced by address redirection of the current branch can be reduced, bubbles introduced by jump prediction of the next branch can be reduced, and therefore pipeline bubbles caused by continuous jump are reduced.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained based on the drawings without inventive efforts.

FIG. 1 is a schematic diagram illustrating a scenario to which embodiments according to the present disclosure are applied;

FIG. 2(a) is a diagram schematically illustrating an execution timing diagram when a processor encounters consecutive jump instructions; FIG. 2(b) is a diagram schematically illustrating an execution timing diagram when a processor encounters consecutive jump instructions after the present jump prediction technique is employed; FIG. 2(c) is a diagram schematically illustrating an execution timing diagram when a processor in a control apparatus for pipelined instruction flow encounters consecutive jump instructions according to an embodiment of the present disclosure;

FIG. 3 is a flow chart of a control method for a pipelined instruction stream according to an embodiment of the present disclosure;

FIG. 4 is a flowchart of one step in a control method for a pipelined instruction stream, according to an embodiment of the present disclosure;

FIG. 5 is a flowchart of a sub-method of establishing an entry associated with a current instruction in a control method for a pipelined instruction stream, according to an embodiment of the present disclosure;

FIG. 6 is a block diagram schematically illustrating one exemplary implementation of a control apparatus for pipelined instruction flow, in accordance with an embodiment of the present disclosure;

FIG. 7 is a block diagram schematically illustrating another exemplary implementation of a control apparatus for pipelined instruction flow, in accordance with an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

The current branch instruction prediction technology introduces jump prediction, stores a target instruction of branch instruction jump into a branch instruction tracking cache, and can quickly read a required instruction from the branch instruction tracking cache when the target instruction hits the branch instruction tracking cache, so that bubbles introduced by address redirection can be relieved, but bubbles related to the jump prediction cannot be reduced.

At least one embodiment of the present disclosure provides a control method and a control device for a pipeline instruction stream, which can obtain, for a continuously skipped instruction stream, a jump target instruction of a current single-skipped branch instruction, and can obtain a subsequent instruction fetch address corresponding to the jump target instruction, thereby improving instruction fetch efficiency, reducing bubbles introduced by address redirection of a current branch, and reducing bubbles introduced by jump prediction of a next branch, thereby reducing pipeline bubbles caused by continuous skipping.

Fig. 1 is a schematic diagram illustrating a scenario 100 to which embodiments according to the present disclosure are applied. In fig. 1, a control device 110 for pipelined instruction flow and an instruction flow 120 with consecutive jumps are shown according to an embodiment of the disclosure. The control device 110 may be any device for processing an instruction stream, e.g. with a processor and a cache, etc., such as a notebook computer, a desktop computer, a tablet computer, etc. As shown in fig. 1, the instruction stream 120 includes two single-jump branch instructions Instr _0 and Instr _ x, and non-branch instructions, i.e., sequential instructions Instr _1, Instr _2, Instr _3, Instr _ x +1, Instr _ x +2, Instr _ x +3, Instr _ t, etc.

When the program runs to the branch instruction Instr _0 of the single jump, the program jumps to the instruction Instr _ x pointed to by the single branch destination address Va _ x to continue execution or sequentially execute the next instruction Instr _1 according to the true/false of the decision condition. When the program runs to the branch instruction Instr _ x of the single jump, the program jumps to the instruction Instr _ t pointed by the single branch destination address Va _ t to continue execution or sequentially execute the next instruction Instr _ x +1 according to the true/false of the decision condition. In the example of FIG. 1, two consecutive jumps occur in instruction stream 120 when a fetch operation is performed, i.e., from Instr _0 to Instr _ x and from Instr _ x to Instr _ t. The branch instructions Instr _0 and Instr _ x may cause the above-mentioned pipeline bubble, i.e. the bubble introduced due to jump prediction and the bubble introduced due to address redirection.

A specific practical example of the control apparatus 110 for a pipelined instruction stream according to an embodiment of the present disclosure is as follows. In the above-mentioned case of the instruction stream 120 where two consecutive jumps occur, when the program runs to the instruction Instr _0 corresponding to the address Va _0, the control apparatus 110 can determine whether the branch instruction Instr _0 of the current single jump jumps and acquire the jump target instruction Instr _ x (if it jumps), and in addition, the control apparatus 110 can also determine whether the jump target instruction Instr _ x (also a branch instruction of the single jump) jumps and acquire a subsequent instruction fetch address corresponding to the jump target instruction Instr _ x, that is, if the jump target instruction Instr _ x jumps, acquire the subsequent instruction fetch address Va _ t corresponding to the jump target instruction Instr _ x; if the jump target instruction Instr _ x does not jump, acquiring a subsequent instruction fetching address Va _ x +1 corresponding to the jump target instruction Instr _ x. Therefore, the control device 110 for a pipeline instruction stream according to the embodiment of the present disclosure can improve instruction fetching efficiency for instruction streams of consecutive jumps, reduce bubbles introduced by address redirection of a current branch, and reduce bubbles introduced by jump prediction of a next branch, thereby reducing pipeline bubbles caused by consecutive jumps.

FIG. 2(a) is a diagram schematically illustrating an execution timing diagram when a processor encounters consecutive jump instructions; FIG. 2(b) is a diagram schematically illustrating an execution timing diagram when a processor encounters consecutive jump instructions after the present jump prediction technique is employed; fig. 2(c) is a diagram schematically illustrating an execution timing when a processor in the control apparatus for pipelined instruction flow encounters consecutive jump instructions according to an embodiment of the present disclosure. Fig. 2(a) - (c) are analyzed in conjunction with the instruction stream 120 shown in fig. 1. As shown in fig. 2(a), the branch instructions Instr _0 and Instr _ x in the instruction stream 120 shown in fig. 1 introduce two kinds of bubbles into the instruction pipeline of the processor, namely, a jump prediction introduced bubble and an address redirection introduced bubble. As shown in fig. 2(b), the present jump prediction technology can store the jump target instruction of the branch instruction in the cache, and when the branch instruction hits in the cache, the required instruction can be quickly read from the cache, so that the bubble introduced by address redirection in the current branch can be reduced. As shown in fig. 2(c), the control method and apparatus for a pipelined instruction stream according to the embodiment of the present disclosure can acquire a jump target instruction Instr _ x of a branch instruction Instr _0 in a first jump, thereby being capable of reducing bubbles introduced by address redirection of a current branch; according to the control method and the control device for the pipeline instruction stream, disclosed by the embodiment of the disclosure, the subsequent instruction fetching address (Va _ x +1 or Va _ t) corresponding to the jump target instruction Instr _ x in the second jump can be obtained, so that bubbles introduced by jump prediction of the next branch can be reduced, and pipeline bubbles caused by continuous jumps can be reduced.

FIG. 3 is a flow chart of a control method 200 for pipelined instruction flow in accordance with an embodiment of the present disclosure. The control method 200 for a pipeline instruction stream is applied to the control apparatus 110 for a pipeline instruction stream shown in fig. 1. The control method 200 is described below in conjunction with the instruction stream 120 of fig. 1.

As shown in fig. 3, the control method 200 includes: at S210, it is determined whether the current instruction Instr _0 is a single-jump branch instruction, which is an instruction that can jump to only a single branch destination address at the time of the jump; at S220, if it is determined that the current instruction Instr _0 is a single-jump branch instruction, accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address Va _0 corresponding to the current instruction Instr _ 0; at S230, determining whether the current instruction Instr _0 jumps according to the current branch prediction table, and determining whether a first associated instruction Instr _ x associated with the instruction address Va _0 jumps according to the advanced branch prediction table; at S240, upon determining that a jump occurs to the current instruction Instr _0, the first associated instruction Instr _ x is fetched from the branch instruction trace cache, and an operation instruction address corresponding to the first associated instruction (Instr _ x) is fetched to perform control.

In the disclosed embodiment, it is determined whether the current instruction Instr _0 is a branch instruction of a single jump. A single jump branch instruction is an instruction that can jump to only a single branch destination address at the time of the jump, i.e., the branch destination address of the branch instruction is only one, rather than multiple. When a jump occurs, the program can only jump to the instruction corresponding to the single branch destination address pointed to by the branch instruction (i.e., the jump target instruction) and continue execution. For example, referring to the instruction stream 120, when the program runs to the branch instruction Instr _0 of the single jump, the program jumps to the instruction Instr _ x corresponding to the single branch destination address Va _ x either to continue execution or to sequentially execute the next instruction Instr _1 according to the true/false of the decision condition.

In the embodiment of the present disclosure, if it is determined that the current instruction Instr _0 is a single-jump branch instruction, the current branch prediction table and the advanced branch prediction table are simultaneously accessed based on the instruction address Va _0 corresponding to the current instruction Instr _ 0. According to one exemplary implementation of the present disclosure, the current branch prediction table stores a series of

values

0 and 1 corresponding to instruction addresses, and these

values

0 and 1 are used to indicate whether a jump will occur in a single branch instruction (e.g., Instr _0) corresponding to each instruction address (e.g., Va _ 0). For example, a value of 0 indicates that no jump will occur to the corresponding single branch instruction, and a value of 1 indicates that a jump will occur to the corresponding single branch instruction. According to one exemplary implementation of the present disclosure, a series of

values

0 and 1 corresponding to instruction addresses are stored in the look-ahead branch prediction table, and these

values

0 and 1 are used to indicate whether a jump target instruction (e.g., Instr _ x) of a single branch instruction (e.g., Instr _0) corresponding to each instruction address (e.g., Va _0) will jump. For example, a value of 0 indicates that no jump will occur to the jump target instruction, and a value of 1 indicates that a jump will occur to the jump target instruction. It is understood that the current branch prediction table and the advanced branch prediction table may also indicate whether a jump occurs in the corresponding instruction in other manners, which is not limited by the present disclosure.

The jump target instruction of a single branch instruction corresponding to an instruction address is also referred to as the first associated instruction associated with the instruction address.

In the embodiment of the present disclosure, it is determined whether the current instruction Instr _0 jumps according to the current branch prediction table, and it is determined whether the first associated instruction Instr _ x associated with the instruction address Va _0 jumps according to the advanced branch prediction table, and when it is determined that the current instruction Instr _0 jumps, the first associated instruction Instr _ x is obtained from a branch instruction trace cache, and an operation instruction address corresponding to the first associated instruction Instr _ x is obtained to perform control. The control method 200 according to the embodiment of the present disclosure can quickly obtain the first associated instruction Instr _ x from the branch instruction trace cache when it is determined that the current instruction Instr _0 jumps for the current branch, that is, the first branch (first jump), so that the instruction fetching efficiency is improved, and bubbles introduced by address redirection in the current branch are reduced (compare with bubbles corresponding to Instr _ x in fig. 2(a) and fig. 2 (c)). The control method 200 according to the embodiment of the present disclosure is capable of determining, for a next branch, that is, a second branch (second jump), a prediction result of a current branch (whether Instr _0 jumps or not), and also capable of determining a prediction result of a next branch (whether Instr _ x jumps or not), and capable of determining an operation instruction address (Va _ x +1 or Va _ t) of the next branch, while determining a prediction result of the current branch (whether Instr _0 jumps or not), which results in reducing bubbles introduced by jump prediction in the next branch (compare fig. 2(a) and fig. 2(c) for Instr _ t).

According to the control method for the pipeline instruction stream, the instruction fetching efficiency can be improved for the instruction stream of continuous jump, bubbles introduced by address redirection of the current branch can be reduced, bubbles introduced by jump prediction of the next branch can be reduced, and therefore pipeline bubbles caused by continuous jump are reduced.

According to an exemplary implementation of the present disclosure, the control method 200 further includes: if the first correlation instruction is determined to jump, acquiring the operation instruction address corresponding to the first correlation instruction comprises acquiring the jump instruction address Va _ t of the first correlation instruction from the branch instruction tracking cache; and if it is determined that the first associated instruction does not jump, fetching the operating instruction address corresponding to the first associated instruction comprises fetching a sequential instruction address Va _ x +1 of the first associated instruction from the branch instruction trace cache.

The determination of the operation instruction address corresponding to the first associated instruction, i.e. the subsequent instruction fetch address of the next branch, which should be one of the jump target instruction of the first associated instruction or the address corresponding to the sequentially executed instruction, according to whether the jump of the first associated instruction occurs, facilitates reducing bubbles introduced by the jump prediction of the next branch.

FIG. 4 is a flowchart of step S210 of a control method 200 for a pipelined instruction stream, according to an embodiment of the present disclosure. As shown in fig. 4, according to one exemplary implementation of the present disclosure, the current instruction is a pre-coded instruction, and the determining whether the current instruction is a single-jump branch instruction (S210) includes: pre-decoding the current instruction before it is fetched (S211); and determining whether the current instruction is a single-jump branch instruction according to the result of the pre-decoding (S212).

According to the above exemplary implementation of the present disclosure, branch instructions of a single jump are pre-coded in a pre-coding stage, instructions are pre-decoded before a current instruction is fetched (before fetching), and instructions that require application of a control method according to an embodiment of the present disclosure are identified.

According to an exemplary implementation of the present disclosure, the control method 200 further includes: if it is determined from the results of the pre-decoding that the current instruction is not a single jump branch instruction, the control method is not executed.

According to the above exemplary implementation of the present disclosure, the control method according to the embodiment of the present disclosure is applied only to a branch instruction of a single jump, and is not applied to an instruction that does not satisfy a condition, so that efficiency can be improved, and power consumption can be reduced.

According to an exemplary implementation of the present disclosure, the control method 200 further includes: if it is determined at step S230 that the current instruction is jumped to, and the first associated instruction cannot be fetched from the branch instruction trace cache at step S240, an entry associated with the current instruction is created. That is, if the branch instruction trace cache does not have historical branch information associated with the current instruction, an entry associated with the current instruction is created to facilitate subsequent pipelining.

FIG. 5 is a flowchart of a sub-method 300 of establishing an entry associated with a current instruction in the control method 200 for pipelined instruction flow according to an embodiment of the present disclosure. As shown in fig. 5, according to an exemplary implementation of the present disclosure, the sub-method 300 of creating an entry associated with the current instruction includes: storing the first associated instruction in the branch instruction trace cache (S310); storing a sequential instruction address of the first associated instruction in the branch instruction trace cache (S320); if the first associated instruction is a single-jump branch instruction, storing a jump instruction address of the first associated instruction in the branch instruction trace cache (S330).

According to the above exemplary implementation of the present disclosure, in the case that there is no historical branch information related to the current instruction in the branch instruction trace cache, an entry related to the current instruction is established in the branch instruction trace cache, so that when the instruction reappears in the subsequent pipeline instruction stream, for the current branch related to the instruction, a finger fetch operation can be performed quickly, a subsequent instruction after the instruction jump (i.e., a jump target instruction, a first associated instruction) is obtained, and for a next branch related to the instruction, a subsequent finger fetch address can be determined quickly, thereby reducing pipeline bubbles.

According to an exemplary implementation of the present disclosure, the control method 200, after establishing the entry associated with the current instruction, also updates the current branch prediction table and the look-ahead branch prediction table based on the execution of the current instruction and the first associated instruction. After the entry related to the current instruction is established in the branch instruction tracking cache, the current branch prediction table and the advanced branch prediction table are correspondingly updated, so that when the instruction reappears in a subsequent pipeline instruction stream, whether the instruction jumps or not and whether the first associated instruction related to the instruction jumps or not can be determined, and therefore pipeline bubbles are reduced.

FIG. 6 is a block diagram schematically illustrating one exemplary implementation of a control device 110 for pipelined instruction flow, according to an embodiment of the present disclosure. The control device 110 may be any device for processing a stream of instructions, such as a notebook computer, desktop computer, tablet computer, or the like. The type of device 110 does not constitute a limitation of the present disclosure. As shown in fig. 6, the control device 110 includes a memory 111, a processor 112, and a branch instruction trace cache 113. The memory 111 is used for storing program codes. The processor 112 is configured to perform the following operations when executing the program code: determining whether the current instruction Instr _0 is a single-jump branch instruction, which is an instruction that can only jump to a single branch destination address at the time of the jump; if the current instruction Instr _0 is determined to be a single-jump branch instruction, accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address Va _0 corresponding to the current instruction; determining whether the current instruction Instr _0 jumps or not according to the current branch prediction table, and determining whether a first associated instruction Instr _ x associated with the instruction address Va _0 jumps or not according to the advanced branch prediction table; upon determining that a jump occurs to the current instruction Instr _0, the first associated instruction Instr _ x is fetched from the branch instruction trace cache, and an operation instruction address corresponding to the first associated instruction Instr _ x is fetched to perform control. The branch instruction trace cache 113 is configured to store the first associated instruction Instr _ x and an operation instruction address corresponding to the first associated instruction Instr _ x.

In the disclosed embodiment, processor 112 determines whether current instruction Instr _0 is a branch instruction of a single jump. A single jump branch instruction is an instruction that can jump to only a single branch destination address at the time of the jump, i.e., the branch destination address of the branch instruction is only one, rather than multiple. When a jump occurs, the program can only jump to the instruction corresponding to the single branch destination address pointed to by the branch instruction (i.e., the jump target instruction) and continue execution. For example, referring to the instruction flow 120 in fig. 1, when the program runs to the branch instruction Instr _0 of the single jump, the program either jumps to the instruction Instr _ x corresponding to the single branch destination address Va _ x to continue execution or sequentially executes the next instruction Instr _1 according to the true/false of the determination condition.

values

0 and 1 corresponding to instruction addresses, and these

values

In the embodiment of the present disclosure, it is determined whether the current instruction Instr _0 jumps according to the current branch prediction table, and it is determined whether the first associated instruction Instr _ x associated with the instruction address Va _0 jumps according to the advanced branch prediction table, and when it is determined that the current instruction Instr _0 jumps, the first associated instruction Instr _ x is obtained from a branch instruction trace cache, and an operation instruction address corresponding to the first associated instruction Instr _ x is obtained to perform control. The control device 110 according to the embodiment of the present disclosure can quickly obtain the first associated instruction Instr _ x from the branch instruction trace cache when it is determined that the current instruction Instr _0 jumps for the current branch, that is, the first branch (first jump), which improves the instruction fetching efficiency and reduces the bubble introduced by address redirection in the current branch (compare fig. 2(a) and fig. 2(c) for Instr _ x). The control apparatus 110 according to the embodiment of the present disclosure is capable of determining, for a next branch, that is, a second branch (second jump), a prediction result (whether Instr _ x jumps) of a current branch while determining a prediction result (whether Instr _0 jumps) of the current branch, and is also capable of determining an operation instruction address (Va _ x +1 or Va _ t) of the next branch, which results in reducing bubbles introduced by jump prediction in the next branch (compare fig. 2(a) and fig. 2(c) for Instr _ t).

According to the control equipment for the pipeline instruction stream, the instruction fetching efficiency can be improved for the instruction stream of continuous jump, bubbles introduced by address redirection of the current branch can be reduced, bubbles introduced by jump prediction of the next branch can be reduced, and therefore pipeline bubbles caused by continuous jump are reduced.

According to an exemplary implementation of the present disclosure, if it is determined that the first associated instruction jumps, obtaining the operation instruction address corresponding to the first associated instruction comprises the processor 112 obtaining a jump instruction address Va _ t of the first associated instruction from the branch instruction trace cache 113; and if it is determined that the first associated instruction does not jump, fetching the operating instruction address corresponding to the first associated instruction comprises the processor 112 fetching the sequential instruction address Va _ x +1 of the first associated instruction from the branch instruction trace cache 113.

According to one exemplary implementation of the present disclosure, the current instruction is a pre-coded instruction, the determining whether the current instruction is a single-jump branch instruction comprises: the processor 112 pre-decodes the current instruction prior to fetching the instruction; the processor 112 determines from the results of the pre-decoding whether the current instruction is a single jump branch instruction.

According to the above exemplary implementation of the present disclosure, branch instructions of a single jump are pre-coded in a pre-coding stage, instructions are pre-decoded before a current instruction is fetched (before fetching), and instructions that require application of a control device according to an embodiment of the present disclosure are identified.

According to an exemplary implementation of the present disclosure, the processor 112 does not perform the operation if it is determined from the results of the pre-decoding that the current instruction is not a single jump branch instruction.

According to the above exemplary implementation of the present disclosure, the control device according to the embodiment of the present disclosure is applied only to a branch instruction of a single jump, and is not applied to an instruction that does not satisfy a condition, so that the efficiency of the control device can be improved, and the power consumption of the control device can be reduced.

According to an exemplary implementation of the present disclosure, if the processor 112 is unable to fetch the first associated instruction from the branch instruction trace cache 113 when it is determined that the current instruction is a jump, the processor 112 creates an entry associated with the current instruction.

That is, if there is no historical branch information associated with the current instruction in branch instruction trace cache 113, processor 112 creates an entry associated with the current instruction to facilitate subsequent pipelining.

According to an exemplary implementation of the present disclosure, the processor 112 creating an entry associated with the current instruction includes: the processor 112 stores the first associated instruction in the branch instruction trace cache 113; the processor 112 stores the sequential instruction address of the first associated instruction in the branch instruction trace cache 113; if the first associated instruction is a single jump branch instruction, the processor 112 stores the jump instruction address of the first associated instruction in the branch instruction trace cache 113.

According to the above exemplary implementation of the present disclosure, in the case that there is no historical branch information related to the current instruction in the branch instruction trace cache 113, the processor 112 establishes an entry related to the current instruction in the branch instruction trace cache 113, so that when the instruction reappears in the subsequent pipeline instruction stream, for the current branch related to the instruction, a fetch operation can be performed quickly, a subsequent instruction after the instruction jump (i.e., a jump target instruction, a first associated instruction) is obtained, and for a next branch related to the instruction, a subsequent fetch address can be determined quickly, thereby reducing pipeline bubbles.

According to an example implementation of the present disclosure, the processor 112 also updates the current branch prediction table and the look-ahead branch prediction table based on the execution of the current instruction and the first associated instruction.

After the processor 112 establishes an entry associated with the current instruction in the branch instruction trace cache 113, the current branch prediction table and the advanced branch prediction table are correspondingly updated, which enables a determination of whether the instruction jumps and a determination of whether the first associated instruction associated therewith jumps when the instruction reappears in a subsequent pipelined instruction stream, thereby reducing pipeline bubbles.

FIG. 7 is a block diagram schematically illustrating another exemplary implementation of a control device 110 for pipelined instruction flow, according to an embodiment of the present disclosure. The control device 110 may be any device for processing a stream of instructions, such as a notebook computer, desktop computer, tablet computer, or the like. The type of device 110 does not constitute a limitation of the present disclosure. As shown in fig. 7, the control device 110 includes an instruction determining unit 114, an access unit 115, a jump determining unit 116, and an obtaining unit 117. The instruction determination unit 114 is configured to determine whether the current instruction Instr _0 is a single-jump branch instruction, which is an instruction that can jump to only a single branch destination address at the time of a jump. The access unit 115 is configured to access a current branch prediction table and a look-ahead branch prediction table based on an instruction address Va _0 corresponding to the current instruction when the instruction determination unit determines that the current instruction Instr _0 is a single-jump branch instruction. The jump determining unit 116 is configured to determine whether the current instruction Instr _0 jumps according to the current branch prediction table, and determine whether the first associated instruction Instr _ x associated with the instruction address Va _0 jumps according to the advanced branch prediction table. The obtaining unit 117 is configured to obtain the first associated instruction Instr _ x from the branch instruction trace cache 130 and obtain an operation instruction address corresponding to the first associated instruction Instr _ x to perform control when the jump determining unit 116 determines that the current instruction Instr _0 jumps.

In the embodiment of the present disclosure, the instruction determination unit 114 determines whether the current instruction Instr _0 is a branch instruction of a single jump. A single jump branch instruction is an instruction that can jump to only a single branch destination address at the time of the jump, i.e., the branch destination address of the branch instruction is only one, rather than multiple. When a jump occurs, the program can only jump to the instruction corresponding to the single branch destination address pointed to by the branch instruction (i.e., the jump target instruction) and continue execution. For example, referring to the instruction flow 120 in fig. 1, when the program runs to the branch instruction Instr _0 of the single jump, the program either jumps to the instruction Instr _ x corresponding to the single branch destination address Va _ x to continue execution or sequentially executes the next instruction Instr _1 according to the true/false of the determination condition.

In the disclosed embodiment, if it is determined that the current instruction Instr _0 is a single-jump branch instruction, access unit 115 accesses the current branch prediction table and the advanced branch prediction table simultaneously based on instruction address Va _0 corresponding to the current instruction Instr _ 0. According to one exemplary implementation of the present disclosure, the current branch prediction table stores a series of

values

0 and 1 corresponding to instruction addresses, and these

values

In the embodiment of the present disclosure, the jump determining unit 116 determines whether the current instruction Instr _0 jumps according to the current branch prediction table, and determines whether the first associated instruction Instr _ x associated with the instruction address Va _0 jumps according to the advanced branch prediction table, and the obtaining unit 117 obtains the first associated instruction Instr _ x from the branch instruction trace cache and obtains the operation instruction address corresponding to the first associated instruction Instr _ x to perform control when the jump determining unit 116 determines that the current instruction Instr _0 jumps. The control device 110 according to the embodiment of the present disclosure can quickly obtain the first associated instruction Instr _ x from the branch instruction trace cache when it is determined that the current instruction Instr _0 jumps for the current branch, that is, the first branch (first jump), which improves the instruction fetching efficiency and reduces the bubble introduced by address redirection in the current branch (compare fig. 2(a) and fig. 2(c) for Instr _ x). The control apparatus 110 according to the embodiment of the present disclosure is capable of determining, for a next branch, that is, a second branch (second jump), a prediction result (whether Instr _ x jumps) of a current branch while determining a prediction result (whether Instr _0 jumps) of the current branch, and is also capable of determining an operation instruction address (Va _ x +1 or Va _ t) of the next branch, which results in reducing bubbles introduced by jump prediction in the next branch (compare fig. 2(a) and fig. 2(c) for Instr _ t).

According to an exemplary implementation of the present disclosure, if it is determined that the first associated instruction jumps, acquiring the operation instruction address corresponding to the first associated instruction includes the acquiring unit 117 acquiring the jump instruction address Va _ t of the first associated instruction from the branch instruction trace cache 130; and if it is determined that the first associated instruction does not jump, fetching the operating instruction address corresponding to the first associated instruction comprises the fetch unit 117 fetching the sequential instruction address Va _ x +1 of the first associated instruction from the branch instruction trace cache 130.

According to one exemplary implementation of the present disclosure, the current instruction is a pre-coded instruction, the determining whether the current instruction is a single-jump branch instruction comprises: the instruction determination unit 114 pre-decodes the current instruction prior to fetching the instruction; the instruction determination unit 114 determines whether the current instruction is a single jump branch instruction based on the results of the pre-decoding.

According to an exemplary implementation of the present disclosure, if instruction determination unit 114 determines from the results of pre-decoding that the current instruction is not a single-jump branch instruction, then access unit 115 does not access the current branch prediction table and the advanced branch prediction table, jump determination unit 116 does not perform a jump determination operation, and fetch unit 117 does not perform a fetch operation.

According to an exemplary implementation of the present disclosure, the control device 110 further includes a creating unit 118, and if the obtaining unit 117 cannot obtain the first associated instruction from the branch instruction trace cache 130 when determining that the current instruction jumps, the creating unit 118 creates an entry related to the current instruction.

That is, if there is no historical branch information associated with the current instruction in branch instruction trace cache 130, build unit 118 builds an entry associated with the current instruction to facilitate subsequent pipelining.

According to an exemplary implementation of the present disclosure, the establishing unit 118 establishes the entry associated with the current instruction including: storing the first associated instruction in the branch instruction trace cache 130; storing a sequential instruction address of the first associated instruction in the branch instruction trace cache 130; if the first associated instruction is a single jump branch instruction, the jump instruction address of the first associated instruction is stored in the branch instruction trace cache 130.

According to the above exemplary implementation of the present disclosure, in the case that there is no historical branch information related to the current instruction in the branch instruction trace cache 130, the establishing unit 118 establishes an entry related to the current instruction in the branch instruction trace cache 130, so that when the instruction reappears in the subsequent pipeline instruction stream, for the current branch related to the instruction, the instruction fetch operation can be performed quickly, the subsequent instruction after the instruction jump (i.e., the jump target instruction, the first associated instruction) is obtained, and for the next branch related to the instruction, the subsequent instruction fetch address can be determined quickly, thereby reducing pipeline bubbles.

According to an example implementation of the present disclosure, the build unit 118 also updates the current branch prediction table and the look-ahead branch prediction table based on the execution of the current instruction and the first associated instruction.

After the build unit 118 builds an entry associated with the current instruction in the branch instruction trace cache 130, the current branch prediction table and the look-ahead branch prediction table are correspondingly updated, which enables a determination of whether the instruction jumps and a determination of whether the first associated instruction associated therewith jumps when the instruction reappears in a subsequent pipelined instruction stream, thereby reducing pipeline bubbles.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present disclosure may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It is noted that, herein, relational terms such as first and third, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the appended claims and their equivalents.

Claims

1. A control method for a pipelined instruction stream, the control method comprising:

determining whether the current instruction is a single-jump branch instruction, the single-jump branch instruction being an instruction that is only able to jump to a single branch destination address at the time of the jump;

if the current instruction is determined to be a single jump branch instruction, accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address corresponding to the current instruction;

determining whether the current instruction jumps according to the current branch prediction table, and determining whether a first associated instruction associated with the instruction address jumps according to the advanced branch prediction table, wherein the first associated instruction is a jump target instruction of the current instruction; and

fetching the first associated instruction from a branch instruction trace cache upon determining that a jump occurs to the current instruction, and fetching an operating instruction address corresponding to the first associated instruction to perform control,

wherein if it is determined that the first associated instruction jumps, obtaining the operating instruction address corresponding to the first associated instruction comprises obtaining the jump instruction address of the first associated instruction from the branch instruction trace cache; and

wherein if it is determined that the first associated instruction does not jump, fetching an operating instruction address corresponding to the first associated instruction comprises fetching a sequential instruction address of the first associated instruction from the branch instruction trace cache.

2. The control method according to claim 1,

the current instruction is a pre-coded instruction, the determining whether the current instruction is a single-jump branch instruction comprising:

predecoding a current instruction prior to fetching the instruction; and

a determination is made as to whether the current instruction is a single jump branch instruction based on the results of the pre-decoding.

3. The control method according to claim 2, further comprising: if it is determined from the results of the pre-decoding that the current instruction is not a single jump branch instruction, the control method is not executed.

4. The control method according to claim 1, further comprising: if the first associated instruction cannot be fetched from the branch instruction trace cache upon determining that a jump has occurred to the current instruction, an entry associated with the current instruction is created.

5. The control method of claim 4, wherein said creating an entry associated with the current instruction comprises:

storing the first associated instruction in the branch instruction trace cache;

storing a sequential instruction address of the first associated instruction in the branch instruction trace cache; and

if the first associated instruction is a single jump branch instruction, storing a jump instruction address of the first associated instruction in the branch instruction trace cache.

6. The control method according to claim 5, further comprising: updating the current branch prediction table and a look-ahead branch prediction table based on execution of the current instruction and the first associated instruction.

7. A control apparatus for a pipelined instruction stream, the control apparatus comprising a memory, a processor and a branch instruction trace cache, wherein,

the memory is used for storing program codes;

the processor is configured to perform the following operations when executing the program code:

when the current instruction is determined to jump, acquiring the first associated instruction from the branch instruction trace cache, and acquiring an operation instruction address corresponding to the first associated instruction to execute control; and is

The branch instruction trace cache is used for storing the first association instruction and an operation instruction address corresponding to the first association instruction,

wherein if it is determined that the first associated instruction jumps, obtaining the operating instruction address corresponding to the first associated instruction comprises the processor obtaining the jump instruction address of the first associated instruction from the branch instruction trace cache; and

wherein if it is determined that the first associated instruction does not jump, fetching an operating instruction address corresponding to the first associated instruction comprises the processor fetching a sequential instruction address of the first associated instruction from the branch instruction trace cache.

8. The control device of claim 7, wherein the current instruction is a pre-coded instruction, the determining whether the current instruction is a single-jump branch instruction comprising:

the processor pre-decodes a current instruction prior to fetching the instruction; and

the processor determines from the results of the pre-decoding whether the current instruction is a single jump branch instruction.

9. The control apparatus of claim 8 wherein the processor does not perform the operation if it is determined from the results of pre-decoding that the current instruction is not a single jump branch instruction.

10. The control device of claim 7, wherein the processor creates an entry associated with the current instruction if the processor fails to fetch the first associated instruction from the branch instruction trace cache upon determining that a jump occurred to the current instruction.

11. The control device of claim 10, wherein the processor building an entry associated with the current instruction comprises:

the processor storing the first associated instruction in the branch instruction trace cache;

the processor storing a sequential instruction address of the first associated instruction in the branch instruction trace cache; and

if the first associated instruction is a single-jump branch instruction, the processor stores a jump instruction address of the first associated instruction in the branch instruction trace cache.

12. The control apparatus of claim 11 wherein the processor further updates the current branch prediction table and a look-ahead branch prediction table based on execution of the current instruction and the first associated instruction.

13. A control apparatus for pipelined instruction flow, the control apparatus comprising:

an instruction determination unit to determine whether a current instruction is a single-jump branch instruction, the single-jump branch instruction being an instruction capable of jumping to only a single branch destination address at the time of a jump;

an access unit for accessing a current branch prediction table and a look-ahead branch prediction table based on an instruction address corresponding to the current instruction when the instruction determination unit determines that the current instruction is a single-jump branch instruction;

a jump determining unit, configured to determine whether the current instruction jumps according to the current branch prediction table, and determine whether a first associated instruction associated with the instruction address jumps according to the advanced branch prediction table, where the first associated instruction is a jump target instruction of the current instruction; and

a fetch unit configured to fetch the first associated instruction from a branch instruction trace cache and fetch an operation instruction address corresponding to the first associated instruction to perform control when the jump determination unit determines that the present instruction jumps,

wherein, if it is determined that the first associated instruction jumps, obtaining the operation instruction address corresponding to the first associated instruction comprises the obtaining unit obtaining the jump instruction address of the first associated instruction from the branch instruction trace cache; and

wherein if it is determined that the first associated instruction does not jump, fetching an operating instruction address corresponding to the first associated instruction comprises the fetch unit fetching a sequential instruction address of the first associated instruction from the branch instruction trace cache.

14. The control device of claim 13, wherein the current instruction is a pre-coded instruction, the determining whether the current instruction is a single-jump branch instruction comprising:

the instruction determination unit pre-decodes a current instruction prior to fetching the instruction; and

the instruction determination unit determines whether the current instruction is a single-jump branch instruction based on the results of the pre-decoding.

15. The control apparatus according to claim 14, wherein if the instruction determination unit determines from the result of predecoding that the current instruction is not a single-jump branch instruction, the access unit does not access the current branch prediction table and the advanced branch prediction table, the jump determination unit does not perform a jump determination operation, and the fetch unit does not perform a fetch operation.

16. The control apparatus according to claim 13, wherein said control apparatus further comprises a building unit that builds an entry associated with the current instruction if said fetch unit fails to fetch said first associated instruction from said branch instruction trace cache upon determining that a jump has occurred to the current instruction.

17. The control device of claim 16, wherein the establishing unit establishes the entry associated with the current instruction comprises:

storing the first associated instruction in the branch instruction trace cache;

18. The control apparatus of claim 17, wherein the build unit is further to update the current branch prediction table and a look-ahead branch prediction table based on execution of the current instruction and the first associated instruction.