CN109769294A - A kind of synchronous method based on FDD-LTE system - Google Patents
A kind of synchronous method based on FDD-LTE system Download PDFInfo
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- CN109769294A CN109769294A CN201711098041.9A CN201711098041A CN109769294A CN 109769294 A CN109769294 A CN 109769294A CN 201711098041 A CN201711098041 A CN 201711098041A CN 109769294 A CN109769294 A CN 109769294A
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Abstract
The present invention relates to a kind of synchronous method for being based on FDD-LTE (frequency division duplex LTE) system, this method passes through research FDD-LTE system physical layer key technology, selective analysis synchronization signal and its characteristic design the synchronous method of low complex degree, low consumption of resources.Entire synchronizing process is divided into filtering, primary synchronization signal detection, offset estimation and compensation, secondary synchronization signal detection, calculates five stages of data frame head.Synchronization signal is extracted by low-pass filter first；Primary synchronization signal detection uses the algorithm of time domain cross-correlation, while having carried out the down-sampled improvement of delay；It is then based on primary synchronization signal and carries out offset estimation, the signal received is compensated；After carrying out 1bit quantization to secondary synchronization signal, by sequence of parity separate detection；The frame head that data frame is finally calculated according to synchronization signal detection result, completes entire synchronizing process.It is synchronous in frequency that the synchronous method can quick and precisely obtain the time, suitable for FDD-LTE system.
Description
Technical field
The present invention relates to a kind of synchronous method for being based on FDD-LTE (frequency division duplex LTE) system.LTE is organized by 3GPP
The wireless communication standard of proposition, using the advanced Radio Transmission Technology such as OFDM, MIMO.LTE has peak rate height, Yong Huyan
It the advantages that small, the availability of frequency spectrum is high, wide coverage late, is widely used in military project and civilian aspect.FDD-LTE is LTE standard
Under one mode.
Background technique
LTE system is used as multiple access technology using OFDM (frequency division multiple access), and largely uses MIMO (multiple-input and multiple-output)
And adaptive technique, while improving cell capacity, system delay is also reduced, and greatly enhance peak value speed
Rate and system performance.Compared with TDD-LTE system, FDD-LTE system uplink and downlink use different frequency range sending and receiving data, have
Better stability.
After the starting of receiver terminal equipment, first have to carry out is exactly synchronizing process, it is the basis of wireless communication.Root
According to LTE standard, data are received and dispatched in the form of frame structure, and time synchronization is exactly the frame head and OFDM for searching out data frame
The beginning of first data of symbol.OFDM technology is very sensitive to frequency shift (FS) simultaneously, and Frequency Synchronization is exactly to transport to signal
Point counting analysis, extracts frequency offset and compensates to data.Synchronizing process needs to carry out primary synchronization signal detection and auxiliary same
Signal detection is walked, forefathers propose the algorithm based on auto-correlation and cross-correlation to primary synchronization signal detection, and have segmentation relevant
It improves；The improvement for proposing 1bit quantization is detected to secondary synchronization signal.The present invention is based on these theory and methods, it is made that further
It improves.
The synchronous method based on FDD-LTE system that the present invention realizes, primary synchronization signal detection are calculated using time domain cross-correlation
Method, while offset estimation and compensation are carried out using the primary synchronization signal detected, auxiliary synchronous detection is using quantization and sequence of parity
The algorithm combined is separated, can quick and precisely realize that the time is synchronous in frequency.Simultaneously during realization, 16 times are used
Be delayed the technologies such as down-sampled, binary tree pipeline organization, state machine decomposition, simplifies calculating process.
Summary of the invention
The object of the present invention is to provide a kind of synchronous method based on FDD-LTE system, by primary synchronization signal and
Secondary synchronization signal is detected, and it is synchronous with frequency to can be realized transmitting terminal and destination time.With establish synchronization time it is short,
Accuracy is high, complexity is low, is easy to the features such as hardware realization.
The present invention is realized using following technological means:
1. a kind of synchronous method based on FDD-LTE system, this method is by filtering, primary synchronization signal detection, offset estimation
With compensation, secondary synchronization signal detection, calculating five part of data frame head composition, it is implemented as follows:
1.1 calculate the time domain data of primary synchronization signal in MATLAB, are stored in FPGA after 16 times down-sampled；Filtering
Two-way I, Q data afterwards, carry out delay and 16 times down-sampled, then carry out cross-correlation meter with 64 points of main synchronizing sequences being locally stored
It calculates, completes complex multiplication, the operation such as add up, seek amplitude, obtain one group of cross-correlation sequence, and calculate sequence peaks, and then sentence
Disconnected primary synchronization signal position out；
1.2 using primary synchronization signal obtained in the above process carry out offset estimation, by the main synchronizing sequence received with
Local sequence carries out conjugate multiplication, obtains new sequence；32 point datas and rear 32 point data carry out conjugate multiplication again before new sequence
With it is cumulative, extract frequency shift (FS)；The secondary synchronization signal received is compensated according to frequency shift (FS), makes auxiliary synchronous detection more
Add accurate；
1.3, according to gained primary synchronization signal position in 1.2, extrapolate the position of secondary synchronization signal, secondary synchronization signal are become
It changes to frequency domain and obtains 62 point datas；According to formula is generated, required scrambler sequence is being locally stored；Use scrambler sequence dual sequence
Descrambling obtains new sequence, then new sequence and local reference sequences is carried out cross-correlation, calculates the subscript i0 of maximum value；Root
Scrambler sequence is generated according to obtained i0 to descramble auxiliary synchronous odd sequence, then new sequence and local reference sequences are carried out mutually
It closes, calculates the subscript i1 of maximum value；By comparing the size of i0 and i1, time slot where secondary synchronization signal is determined；
After 1.4 complete primary and secondary synchronization signals detection, the frame head of next frame is calculated according to frame structure, has been to guarantee to export
Whole data frame realizes the synchronization of system.
2. in aforementioned 1.2, by being analyzed to main synchronous detection algorithm and to PFGA hardware feature, further describing
It is as follows:
It is down-sampled that 2.1 pairs of data for receiving carry out 16 times of delays, relative to directly carrying out down-sampled, each data
It can participate in calculating；
2.2 computing cross-correlations use binary tree pipeline processing architecture；
When 2.3 cross-correlation sequence peaks detect, using threshold value and the method that combines of traversal maximum value；
3. in aforementioned 1.3, conjugate multiplication and cumulative is same to use the processing structure based on binary tree assembly line, calculates three
When angle function value, using CORDIC IP kernel, with the mode solution trigonometric equation of iteration；
4. in aforementioned 1.4, carrying out 1bit quantization, while antithesis to secondary synchronization sequences according to the generation formula of secondary synchronization signal
Sequence and odd sequence separate detection, entire detection process use state machine control.
A kind of synchronous method based on FDD-LTE system of the present invention, it is advantageous that:
1. being filtered first using filter to the data received, the data unrelated with detection are got rid of；Main synchronization
Delay in detection is down-sampled and peak-value detection method, greatly reduces operation times；1bit quantization in auxiliary synchronous detection and
Sequence of parity method for separating and detecting, it is space-saving while avoiding complex multiplication.Algorithm is carried out in entire synchronizing process
It simplifies and optimizes, quick and precisely.
2. the method for the present invention more focuses on the simplification in terms of hardware realization.Use state machine decomposition technique, state machine are divided into
Different brackets, high level state machine are responsible for controlling low level state machine, complete the switching of task, low level state machine
It is responsible for basic calculating and logic to realize, so that whole process is clear；Using binary tree pipeline organization, give full play to
The advantage of FPGA hardware resource reduces time delay；Using cache module, loss of data when link obstructions is prevented.
Detailed description of the invention
Fig. 1 is synchronization scheme process；
Fig. 2 is filter input and output pin figure；
Fig. 3 is main synchronization signal detection block diagram；
Fig. 4 binary tree pipeline processing architecture；
Fig. 5 is offset estimation and compensation entire block diagram；
Synchronization signal detection state flow chart supplemented by Fig. 6；
Fig. 7 is to calculate data frame head program flow diagram；
Specific embodiment
Implementation of the invention is described further below in conjunction with Figure of description:
Fig. 1 is synchronization scheme flow chart.Synchronization signal only takes up the 1.08MHz bandwidth among frequency band, first has to by low
Bandpass filter is filtered, and extracts the data of needs；Primary synchronization signal is generated using ZC sequence in frequency domain, and ZC sequence has excellent
Good auto-correlation and cross correlation, and ZC sequence detects use to it by being still ZC sequence after FFT or IFFT
Time domain cross correlation algorithm；Since above-mentioned steps can detecte the primary synchronization signal to receiving end, so offset estimation is based on master together
Signal is walked, is compensated by frequency deviation value is calculated, and to data；The auxiliary synchronous sequence of formula is generated according to secondary synchronization signal
Column only 0 and 1 composition, so carrying out 1 bit quantization to secondary synchronization sequences, then is detected.
Fig. 2 is filter block diagram.Part among synchronization signal band occupancy respectively accounts for half in zero-frequency or so, so needing
A low-pass filter is designed, to filter out other unwanted data.Totally 62 data, zero-frequency or so respectively account for synchronizing sequence
31 subcarriers, subcarrier spacing 15KHz, so needing to retain the data in 15 × 31=465KHz, i.e. cutoff frequency is
465KHz.The FDATool tool being first turned in MATLAB, be arranged filter parameter, select low-pass filter, window function metht,
Rectangular window, sample frequency 15.36MHz.After the completion of design, the analysis of system automatically generated filter characteristic and filter coefficient,
Filter can be adjusted according to characteristic, while filter coefficient being exported in COE file.In FPGA, FIR is selected
IP kernel imports COE file, selects input pin and output pin, completes the entire design of filter.
Fig. 3 is main synchronization signal detection block diagram.By filtered data, 16 times of delays of progress first are down-sampled, this mould
Block includes 63 delay units, and the delay parameter of each unit is set as 16 clock cycle, and delay unit is made of cascade,
Each data can enter time delay module, not will cause the loss of data.Become 64 point datas after 1024 point datas are down-sampled, then
Cross-correlation is done with local 64 points of main synchronizing sequences.Cross-correlation module is made of multiplier and adder, uses binary tree assembly line
Processing structure, as shown in Figure 4.The serial computing of script is changed to parallel computation, when reducing processing by binary tree pipeline organization
Prolong.Peak detection is carried out to cross-correlation sequence, the method combined using threshold value and traversal maximum value, first according to cross-correlation sequence
Column as a result, one suitable threshold value of setting, finite number only near peak value according to being greater than threshold value, to be greater than the data of threshold value into
Row traversal, searches out maximum value, as peak value, determines primary synchronization signal position further according to peak value subscript.
Fig. 5 is offset estimation and compensation entire block diagram.Since the above process can extract receiving end primary synchronization signal, and
And the primary synchronization signal of known standard, so frequency offset estimation procedure is based on primary synchronization signal.The time-domain signal model received is r
(t)=s (t) e- j2 π f κ, t, can be obtained after samplingEnable ε=fn/f0, thenIt will receive
Primary synchronization signal obtained with standard signal conjugate multiplication
Y (n) is divided into two parts again conjugate multiplication and to sum again, is obtained
Frequency deviation isIt is to the formula that signal compensatesIt enables
ThenIt is divided into I, Q two-way due to receiving end data, so
Final
It in the above process, needs to find out phase argument according to complex values, while needing to calculate sine and cosine according to angle value,
The CORDIC IP kernel that FPGA is provided, simplifies these trigonometric function operations.The computing function packet that CORDIC IP kernel may be implemented
Vector Rotation, sin, cos, sinh, cosh, ArcTan, ArcTanh and square root are included, is needed to function, internal serial or simultaneously
Row is realized, pipeline series and input and output pin are configured.
In synchronous phase, the purpose of offset estimation and compensation is mainly modified the secondary synchronization signal received, makes
The detection of secondary synchronization signal is more accurate.According to the position of frame structure and primary synchronization signal, secondary synchronization signal can be calculated
Position, after extracting secondary synchronization signal, formula (3) compensates it, and acquired results are sent into auxiliary synchronous detection module.
Synchronization signal detection state process supplemented by Fig. 6.For compensated secondary synchronization signal, FFT transform is first carried out, is extracted
1024 point datas of frequency domain out, are detected in frequency domain.Entire detection process use state machine is controlled, and logic is more clear
Task clear, that each state is completed in Fig. 6 are as follows: (1) original state: initialization wait state waits secondary synchronization signal frequency domain sequence
Column are ready to；(2) even sequence descrambles: descrambling to auxiliary synchronous even sequence, obtains the sequence that length is 31.(3) it calculates mutual
It closes: the sequence and the local sequence progress cross-correlation of two dimension after descrambling is completed, j=31 indicates one group using two state switchings
Cross correlation value calculating finishes；(4) cross-correlation sequence: cooperating with Last status, realizes that the multiplication of two-dimensional array, i=31 indicate
31 groups of cross correlation value calculating finish, and obtain cross-correlation sequence；(5) sequence peaks calculate: it is maximum to find cross-correlation sequence in (4)
Value, records the position i of maximum value0；(6) odd sequence descrambles: descrambling to auxiliary synchronous odd sequence；(7) cross correlation value is calculated: with
(3) (4) process is similar；(8) sequence peaks calculate: cross-correlation sequence in traversal (7) records the position i of maximum value1；(9) it ties
Beam: according to correlation theory in agreement, if i0<i1, then the secondary synchronization sequences detected are located at the 0th time slot, if i0>i1, then detect
Secondary synchronization sequences be located at the 10th time slot；Flag bit flag sets 1 simultaneously, and expression completes auxiliary synchronization detection process.
Fig. 7 is to calculate data frame head program flow diagram.According to the above process, the position and master according to primary synchronization signal are obtained
Time slot can calculate the data frame head of next frame in conjunction with FDD-LTE system data frame structure where synchronization signal.It is receiving
Data enter after synchronization module, need to start simultaneously two counters, and one is used to record the data amount check for participating in operation, separately
One enters main synchronization detection process, provides the benchmark of frame head calculating.After the completion of main synchronous detection, counter 2 believes main synchronization
Number position write-in pss_location variable in.After time slot where determining synchronization signal, if synchronization signal is located at the 0th
Gap, pss_location is apart from 19 × 7 × 1024=136192 data of next frame head；If synchronization signal is located at the 10th time slot,
Pss_location is apart from 9 × 7 × 1024=64512 data of next frame head.When counter 1 count down to specified data, control
Synchronization module processed carries out data input, and the data exported at this time are complete data frame.
Finally it should be noted that: above embodiments are only to illustrate technical solution of the present invention under particular system, and
It is non-that it is limited；The present invention is suitable for FDD-LTE system, system bandwidth 10MHz；It is all in technical solution of the present invention, institute
The part modification made or equivalent replacement, should all cover within the scope of the present invention is claimed.
Claims (4)
1. a kind of synchronous method based on FDD-LTE system, this method is designed by filter, primary synchronization signal detects, frequency deviation is estimated
Meter and compensation, secondary synchronization signal detection, calculating five part of data frame head composition, are implemented as follows:
1.1 calculate the time domain data of primary synchronization signal in MATLAB, 16 times it is down-sampled after inside deposit FPGA；It is filtered
Two-way I, Q data, carry out delay and 16 times are down-sampled, then carry out cross-correlation calculation with 64 points of main synchronizing sequences being locally stored,
Complete complex multiplication, the operation such as add up, seek amplitude, obtain one group of cross-correlation sequence, and calculate sequence peaks, and then judge
Primary synchronization signal position；
1.2 carry out offset estimation using primary synchronization signal obtained in the above process, by the main synchronizing sequence received and local
Sequence carries out conjugate multiplication, obtains new sequence；32 point datas and rear 32 point data carry out conjugate multiplication again and tire out before new sequence
Add, extracts frequency shift (FS)；The secondary synchronization signal received is compensated according to frequency shift (FS), keeps auxiliary synchronous detection more smart
Really；
1.3, according to gained primary synchronization signal position in 1.2, extrapolate the position of secondary synchronization signal, secondary synchronization signal are transformed to
Frequency domain obtains 62 point datas；According to formula is generated, required scrambler sequence is being locally stored；Use scrambler sequence dual sequence solution
It disturbs, obtains new sequence, then new sequence and local reference sequences are subjected to cross-correlation, calculate the subscript i0 of maximum value；According to
Obtained i0 generates scrambler sequence and descrambles to auxiliary synchronous odd sequence, then new sequence and local reference sequences are carried out mutually
It closes, calculates the subscript i1 of maximum value；By comparing the size of i0 and i1, time slot where secondary synchronization signal is determined.
After 1.4 complete primary and secondary synchronization signals detection, the frame head of next frame is calculated according to frame structure, to guarantee that output is complete
Data frame realizes the synchronization of system.
2. the synchronous method according to claim 1 based on FDD-LTE system, it is characterised in that: in aforementioned 1.2, pass through
It analyzes, is further described below to main synchronous detection algorithm and to PFGA hardware feature:
2.1 pairs of data 16 times of delays of progress received are down-sampled, and down-sampled relative to directly carrying out, each data can join
With calculating；
2.2 computing cross-correlations use binary tree pipeline processing architecture；
When 2.3 cross-correlation sequence peaks detect, using threshold value and the method that combines of traversal maximum value.
3. the synchronous method according to claim 1 based on FDD-LTE system, it is characterised in that: in aforementioned 1.3, conjugation
Mutually multiply and accumulate, it is same to use the processing structure based on binary tree assembly line, when calculating trigonometric function value, use CORDIC IP
Core, with the mode solution trigonometric equation of iteration.
4. the synchronous method according to claim 1 based on FDD-LTE system, it is characterised in that: in aforementioned 1.4, according to
The generation formula of secondary synchronization signal carries out 1bit quantization, while dual sequence and odd sequence separate detection to secondary synchronization sequences, whole
A detection process use state machine control.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113556150A (en) * | 2021-05-26 | 2021-10-26 | 青岛鼎信通讯股份有限公司 | Frame detection method for power line carrier communication |
| CN114885412A (en) * | 2022-04-13 | 2022-08-09 | 广州万码科技有限公司 | LTE frame offset value calculation method, device, system, equipment and storage medium |
-
2017
- 2017-11-09 CN CN201711098041.9A patent/CN109769294A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113556150A (en) * | 2021-05-26 | 2021-10-26 | 青岛鼎信通讯股份有限公司 | Frame detection method for power line carrier communication |
| CN114885412A (en) * | 2022-04-13 | 2022-08-09 | 广州万码科技有限公司 | LTE frame offset value calculation method, device, system, equipment and storage medium |
| CN114885412B (en) * | 2022-04-13 | 2024-03-08 | 广州万码科技有限公司 | LTE frame offset value calculation method, device, system, equipment and storage medium |
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