CN109755314A

CN109755314A - Superjunction devices and its manufacturing method

Info

Publication number: CN109755314A
Application number: CN201711090001.XA
Authority: CN
Inventors: 肖胜安
Original assignee: Sanrise Technology Co ltd
Current assignee: Shenzhen Shangyangtong Technology Co ltd
Priority date: 2017-11-08
Filing date: 2017-11-08
Publication date: 2019-05-14
Anticipated expiration: 2037-11-08
Also published as: CN109755314B

Abstract

The invention discloses a kind of superjunction devices, the p-type column of super-junction structure is made of the p-type epitaxial layer for filling in the trench, and N-type column is made of the N-type epitaxy layer between each p-type column, and super-junction structure is located in electric current flowing area, transition region and termination environment；Protection ring oxidation film is looped around the side in electric current flowing area；It include the top area that a n-type doping concentration reduces in the N-type epitaxy layer at the oxidation film epitaxial layer interface of the N-type epitaxy layer of protection ring oxidation film and termination environment; n-type doping concentration by reducing top area enhances the having lateral depletion ability of the N-type column at oxidation film epitaxial layer interface; the uniformity of the electric-field intensity distribution at oxidation film epitaxial layer interface is improved, the ability that lateral voltage is born in termination environment is improved.The invention also discloses a kind of manufacturing methods of superjunction devices.

Description

Superjunction devices and its manufacturing method

Technical field

The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of superjunction (super Junction) the manufacturing method of device.

Background technique

Super-junction structure is exactly alternately arranged N-type column and p-type column composed structure.If replaced with super-junction structure vertical double It spreads in MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device N-type drift region, provide conduction path by N-type column in the on-state, p-type column does not provide conduction path when conducting；It is cutting Only reversed bias voltage is born by PN column under state jointly, is formed superjunction Metal-Oxide Semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).Super node MOSFET can be reversed Under breakdown voltage and traditional VDMOS device unanimous circumstances, by using the epitaxial layer of low-resistivity, and make the conducting of device Resistance is greatly reduced.

In existing superjunction devices, in electric current flowing area, there are alternately arranged p-type column and N-type column, with the P-N column of strip For the structure of i.e. alternately arranged p-type column and N-type column, there is a gate structure such as polysilicon gate above each N column, this is more Crystal silicon grid can partially cover the P column on periphery, can not also cover, and have a p-type trap (PWell) above each P column, in P Have a N+ source region in type trap, there is a contact hole, source metal is connected by contact hole with source region, source metal pass through by The contact zone P+ of one high concentration is connected with the area P, that is, p-type trap, and source metal is the front metal layer for forming source electrode.

Electric current flowing area and bear voltage terminal area between, there are a transition region, have in transition region one and The p-type trap in electric current flowing area connected p-type ring region has contact hole in the p-type ring region, also have under contact hole one it is highly concentrated The contact zone P+ of degree；Therefore p-type ring, passes through P+ contact area, the contact hole of p-type ring region, front metal layer, that is, source electrode, device Source region and device stream with device are realized in contact hole and the contact zone P+ of source contact hole bottom in the source region in electric current flowing area P-type trap in dynamic area is connected.Termination environment is for horizontally bearing the voltage between source region and drain region, in general superjunction In MOSFET element, which is mainly made of alternately arranged P-N column, or in the outside of alternately arranged P-N column, also There is a N+ cut-off region.Between source region and drain region plus when reverse bias, carrier therein is mutual in this alternately arranged area P-N It mutually exhausts, forms a depletion region for bearing this lateral voltage.In order to improve the competitiveness of device, need using minimum Terminal size, the transverse electric field intensity of such P-N column will increase, so that the design of device terminal is more important.

Summary of the invention

Technical problem to be solved by the invention is to provide a kind of superjunction devices, the receiving that can improve device terminal is laterally electric The ability of pressure improves the reliability of device.For this purpose, the present invention also provides a kind of manufacturing methods of superjunction devices.

In order to solve the above technical problems, the intermediate region of superjunction devices provided by the invention is electric current flowing area, termination environment It is surrounded on the periphery in the electric current flowing area, transition region is between the electric current flowing area and the termination environment；Include:

N-type epitaxy layer is formed with multiple grooves in the N-type epitaxy layer；It is filled in the trench by p-type epitaxial layer simultaneously P-type column is formed, N-type column is formed by the N-type epitaxy layer between each p-type column, by multiple alternately arranged N-type columns With the super-junction structure of p-type column composition；The super-junction structure is located at the electric current flowing area, the transition region and the terminal Qu Zhong.

Protection ring oxidation film is looped around the side in the electric current flowing area and exposes the electric current flowing area and by institute State transition region all cover, the protection ring oxidation film also extend into the termination environment surface and by the termination environment completely or only The outermost circumferential portion of the termination environment is exposed.

Institute at the oxidation film epitaxial layer interface of the N-type epitaxy layer of the protection ring oxidation film and the termination environment Stating includes top area that a n-type doping concentration reduces in N-type epitaxy layer, and the N-type by reducing the top area is mixed Miscellaneous concentration enhances the having lateral depletion ability of the N-type column at the oxidation film epitaxial layer interface, makes the oxidation film extension The uniformity of electric-field intensity distribution at bed boundary improves, and improves the ability that lateral voltage is born in the termination environment.

A further improvement is that the N-type net doping of the top area is folded by the n-type doping impurity of the N-type epitaxy layer The first p-type implanted dopant is added to form.

A further improvement is that the doping concentration of the top area is the N-type extension of the top area bottom The 80%~95% of the doping concentration of layer.

A further improvement is that the depth bounds of the top area are 2 microns~3 microns.

A further improvement is that the implanted dopant of the first p-type implanted dopant is B or BF2, Implantation Energy 5Kev ~100Kev, implantation dosage 8E10cm^-2~3E11cm^-2。

A further improvement is that the injection zone of the first p-type implanted dopant passes through lithographic definition；Alternatively, described The injection technology of one p-type implanted dopant is injection comprehensively.

A further improvement is that being formed with p-type trap, shape in the selection area of the electric current flowing area and the transition region Selection area at the p-type trap passes through lithographic definition；The top of each p-type column is all formed with one in the electric current flowing area A p-type trap and each p-type trap extend to the surface of the N-type column of corresponding p-type column two sides.

It is formed on the surface of the super-junction structure in the electric current flowing area by gate oxidation films and polysilicon gate superposition shape At planar gate structure, the forming region of the polysilicon gate passes through photoetching process and defines, and each polysilicon gate covering corresponds to The p-type trap and channel is used to form by the surface for the p-type trap that the polysilicon gate covers.

The polysilicon gate two sides in the electric current flowing area are respectively formed by source region, and the source region passes through with described Polysilicon gate and the protection ring oxidation film are that comprehensive second of N-type ion of autoregistration condition is injected to be formed, described second The injection of secondary N-type ion is simultaneously in the termination environment except protection ring oxidation film overlay area or outside forms terminal the Two N-type injection regions.

Interlayer film is covered on the polysilicon gate, the 2nd N of the source region, the protection ring oxidation film and the terminal Type injection region surface；The contact hole of the interlayer film is formed through in the interlayer film, the contact hole passes through photoetching work Skill definition.

Front metal layer be formed on the surface of the interlayer film of the contact hole, grid and source electrode by it is described just Face metallic layer graphic is formed, and the forming region of the grid and the source electrode is defined by photoetching process；The electric current flowing Each source region and the corresponding p-type trap in area are connected to the source electrode, the transition by the identical contact hole in top The p-type trap in area is connected to the source electrode, the contact hole that the polysilicon gate passes through top also by the contact hole at top It is connected to grid.

A further improvement is that forming the region JFET in the electric current flowing area, the region JFET passes through with described Protection ring oxidation film is that the comprehensive first time N-type ion of autoregistration condition is injected to be formed；The first time N-type ion injection is same When in the termination environment except protection ring oxidation film overlay area or outside formed the first N type injection region of terminal.

A further improvement is that the bottom of the contact hole described in the electric current flowing area passes through the source region, to disappear Influence except the source region injected comprehensively to the contact hole and the contact of the p-type trap of bottom.

A further improvement is that it is total to be formed with polysilicon at the top of the protection ring oxidation film for being located at the transition region Line, the polysilicon bus and the polysilicon gate are formed simultaneously using identical technique, each polysilicon gate and described more The connection of crystal silicon bus contact, and each polysilicon gate with the polysilicon bus by being connected and by being formed in the polycrystalline Contact hole at the top of silicon bus is connected to the grid.

In order to solve the above technical problems, in the manufacturing method of superjunction devices provided by the invention, the middle area of superjunction devices Domain is electric current flowing area, and termination environment is surrounded on the periphery in the electric current flowing area, and transition region is located at the electric current flowing area and institute It states between termination environment；Include the following steps:

Step 1: providing N-type epitaxy layer, the forming region that first time photoetching process defines groove is carried out, later to institute It states N-type epitaxy layer progress dry etching and forms multiple grooves.

Filling p-type epitaxial layer forms p-type column in the trench, by the N-type epitaxy layer group between each p-type column At N-type column, the super-junction structure being made of multiple alternately arranged N-type columns and the p-type column；The super-junction structure is located at institute It states in electric current flowing area, the transition region and the termination environment.

Step 2: carrying out second of photoetching process defines p-type trap in the electric current flowing area and the transition region Forming region carries out P-type ion later and injects to form the p-type trap.

The top of each p-type column is all formed with the p-type trap in the electric current flowing area and each p-type trap prolongs Reach the surface of the N-type column of corresponding p-type column two sides.

Step 3: carrying out the injection region that third time photoetching process defines the first p-type implanted dopant in the termination environment Domain；The first p-type implanted dopant is injected into subsequent protection epoxy by the injection for carrying out the first p-type implanted dopant later Change the top area of the N-type epitaxy layer at the oxidation film epitaxial layer interface of the N-type epitaxy layer of film and the termination environment In, reduce the n-type doping concentration of the top area, the n-type doping concentration by reducing the top area makes the oxygen The having lateral depletion ability enhancing for changing the N-type column at film epitaxial layer interface, makes the electric field at the oxidation film epitaxial layer interface The uniformity of intensity distribution improves, and improves the ability that lateral voltage is born in the termination environment.

Step 4: carrying out the first oxide growth on the N-type epitaxy layer surface for being formed with the p-type trap, the is carried out Four mask technique defines the etch areas of first oxidation film, performs etching to form guarantor to first oxidation film later Retaining ring oxidation film, the electric current flowing area is exposed and all covers the transition region by the protection ring oxidation film, described Protection ring oxidation film also extends into the termination environment surface and by the termination environment completely or only by the most peripheral of the termination environment Part is exposed, and the protection ring oxidation film is looped around the side in the electric current flowing area.

Comprehensive first time N-type ion, which is carried out, as autoregistration condition using the protection ring oxidation film is infused in the electric current stream The region JFET is formed in dynamic area, while in the termination environment except protection ring oxidation film overlay area or outside is formed The first N-type of terminal injection region.

Step 5: sequentially forming the first layer polysilicon of gate oxidation films and N-type heavy doping, it is fixed to carry out the 5th photoetching process Justice goes out the forming region of polysilicon gate, performs etching to form polysilicon gate to the first layer polysilicon later, each polycrystalline Si-gate is planar gate structure, the P that each polysilicon gate covers the corresponding p-type trap and covered by the polysilicon gate The surface of type trap is used to form channel.

Comprehensive second of N-type ion note is carried out using the polysilicon gate and the protection ring oxidation film as autoregistration condition Enter the polysilicon gate two sides in the electric current flowing area and be respectively formed source region, while being covered in the protection ring oxidation film In the termination environment except region or outside forms the second N-type of terminal injection region.

Step 6: deposit interlayer film, carries out the forming region that the 6th photoetching process defines contact hole, later to described Interlayer film performs etching the opening to form the contact hole；Metal is filled in the opening of the contact hole forms the contact Hole.

Step 7: carry out front metal deposit to form front metal layer, carry out the 7th photoetching process define grid and The forming region of source electrode performs etching the front metal layer to form the grid and the source electrode later, the electric current stream Each source region and the corresponding p-type trap in dynamic area are connected to the source electrode, the mistake by the identical contact hole in top The p-type trap crossed in area is connected to the source electrode, the contact that the polysilicon gate passes through top also by the contact hole at top Hole is connected to grid.

Step 1: provide N-type epitaxy layer, the N-type epitaxy layer that is injected into of comprehensive first p-type implanted dopant is carried out In top area, reduce the n-type doping concentration of the top area.

Step 2: carrying out the forming region that first time photoetching process defines groove, the N-type epitaxy layer is carried out later Dry etching forms multiple grooves.

Step 3: carrying out second of photoetching process defines p-type trap in the electric current flowing area and the transition region Forming region carries out P-type ion later and injects to form the p-type trap.

Step 4: carrying out the first oxide growth on the N-type epitaxy layer surface for being formed with the p-type trap, the is carried out Third photo etching technique defines the etch areas of first oxidation film, performs etching to form guarantor to first oxidation film later Retaining ring oxidation film, the electric current flowing area is exposed and all covers the transition region by the protection ring oxidation film, described Protection ring oxidation film also extends into the termination environment surface and by the termination environment completely or only by the most peripheral of the termination environment Part is exposed, and the protection ring oxidation film is looped around the side in the electric current flowing area.

At the oxidation film epitaxial layer interface of the N-type epitaxy layer of the protection ring oxidation film and the termination environment, lead to The n-type doping concentration for crossing the top area that reduction is superimposed with the first p-type implanted dopant makes the oxidation film epitaxial layer The having lateral depletion ability of the N-type column of interface enhances, and makes the electric-field intensity distribution at the oxidation film epitaxial layer interface Uniformity improves, and improves the ability that lateral voltage is born in the termination environment.

Step 5: sequentially forming the first layer polysilicon of gate oxidation films and N-type heavy doping, it is fixed to carry out fourth lithography technique Justice goes out the forming region of polysilicon gate, performs etching to form polysilicon gate to the first layer polysilicon later, each polycrystalline Si-gate is planar gate structure, the P that each polysilicon gate covers the corresponding p-type trap and covered by the polysilicon gate The surface of type trap is used to form channel.

Step 6: deposit interlayer film, carries out the forming region that the 5th photoetching process defines contact hole, later to described Interlayer film performs etching the opening to form the contact hole；Metal is filled in the opening of the contact hole forms the contact Hole.

Step 7: carry out front metal deposit to form front metal layer, carry out the 6th photoetching process define grid and The forming region of source electrode performs etching the front metal layer to form the grid and the source electrode later, the electric current stream Each source region and the corresponding p-type trap in dynamic area are connected to the source electrode, the mistake by the identical contact hole in top The p-type trap crossed in area is connected to the source electrode, the contact that the polysilicon gate passes through top also by the contact hole at top Hole is connected to grid.

The present invention has done special setting to the surface doping of the N-type epitaxy layer of termination environment, mainly on the top of N-type epitaxy layer Portion region increases a P in the N-type epitaxy layer at the oxidation film epitaxial layer interface of protection ring oxidation film and N-type epitaxy layer Type injects the first p-type implanted dopant to be formed, and the N-type net dopant concentration of the top area of N-type epitaxy layer can in this way reduced, oxygen The reduction for changing the doping concentration of the N-type epitaxy layer of the top area at film epitaxial layer interface can make the top region for the N-type column to be formed Domain is easier to be easier to be unfolded in top area by having lateral depletion namely exhausting for the P-N column of termination environment, the top region of N-type column The enhancing of the having lateral depletion ability in domain can then make the electric field strength at oxidation film epitaxial layer interface change more slow, electric-field strength The uniform performance of degree distribution is improved, so can finally improve the ability of the receiving lateral voltage of device terminal and improve device Total receiving reverse biased ability, improve the reliability of device.Especially in the total impurities of p-type column relative to N-type column Total impurities it is inadequate when, this N-type epitaxy layer top area inject p type impurity, to reduce N-type epitaxy layer top The impurity concentration in region is to enhance the effect of the having lateral depletion of the top area of N-type column with regard to more obvious.

In addition, the present invention has carried out special setting by protection ring oxidation film, protection ring oxidation film can be by electric current flowing area Expose and all cover transition region, and termination environment is wholly or largely covered；Join protection epoxidation film it is special Setting, which can be used, is infused in electric current flowing area by the comprehensive first time N-type ion of autoregistration condition progress of protection ring oxidation film The middle formation for forming the region JFET in the region JFET namely the present invention does not need individually a photoetching process to be used to be defined, Namely the present invention can reduce photoetching corresponding to the region JFET.

Meanwhile the injection of the first time N-type ion corresponding to the region JFET of the invention is in JFET injection, due to protection Termination environment all covering and can wholly or largely be covered transition region by epoxidation film, the injection of first time N-type ion from Son will not be injected into transition region and in the interior zone of termination environment, if being filled with JFET in the interior zone of termination environment The N-type ion of injection can then be substantially reduced the breakdown voltage i.e. BVds of device；And if being filled with JFET injection in transition region N-type ion, then can reduce the power of resisting voltaic impingement i.e. EAS of device, thus the present invention can reduce the region JFET institute it is right The Performance And Reliability of device is set to be maintained under conditions of the photoetching answered.In addition, the present invention can also be with polysilicon gate and protection Epoxidation film be autoregistration condition carry out comprehensive second of N-type ion injection i.e. source be infused in it is described more in electric current flowing area Crystal silicon grid two sides equally can be achieved with using autoregistration when being respectively formed source region namely present invention formation source region, not need individually It is defined using a photoetching process, so present invention saves the primary photoetching for defining source region.The present invention can also realize The autoregistration of the region JFET and source region is injected namely the present invention can be reduced Twi-lithography technique, can make the performance of device and reliable Property be maintained, can reduce cost of manufacture, shorten the production cycle.

Detailed description of the invention

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

Fig. 1 is the top view of existing superjunction devices；

Fig. 2 is the diagrammatic cross-section of existing superjunction devices；

Fig. 3 is the diagrammatic cross-section of superjunction devices of the embodiment of the present invention；

Fig. 4 A- Fig. 4 I is the section signal of device in each step of manufacturing method of first embodiment of the invention superjunction devices Figure.

Specific embodiment

As shown in Figure 1, being existing superjunction devices top view；General super junction device structure all includes electric current flowing area, cross Institute is surrounded on to the termination environment and the transition region between electric current flowing area and termination environment, termination environment for bearing reverse bias voltage The periphery in electric current flowing area is stated, 1st area Tu1Zhong indicates that electric current flowing area, 2nd area indicate transition region, and 3rd area indicate termination environment.

1st area includes the super-junction structure being made of alternately arranged p-type column 22 and N-type column 23, p-type column 22 and N in Fig. 1 Type column 23 is all in strip structure.N-type column 23 exists in providing conduction path, p-type column 22 and N-type column 23 when superjunction devices is connected Common receiving reverse biased is exhausted when superjunction devices is reverse-biased mutually.

2nd area and 3rd area are located at the terminal of superjunction devices, collectively as the terminal protection structure for indicating superjunction devices.In device 2nd area and 3rd area described in when conducting do not provide electric current, outermost to device from the surface of 1 area periphery unit for undertaking in reverse-biased The voltage of the end surfaces substrate voltage is lateral voltage and the voltage voltage from 1 area periphery cell surface to substrate is longitudinal electricity Pressure.

There is at least one p-type ring 25 in 2nd area, is a p-type ring 25, p-type backgate of the p-type ring 25 generally with 1st area in Fig. 1 That is p-type trap links together；In the prior art, generally there is the field plate dielectric film with certain inclination angle in 2nd area, in 2nd area also With for slowing down surface field field plate 24 jumpy, field plate 24 is polycrystalline field plate piece or Metal field plate and p-type column 22；The Metal field plate can also be not provided in 2nd area.

3rd area include the super-junction structure being made of alternately arranged p-type column 22 and N-type column 23, the P type column 22 in 3rd area Tu1Zhong With N-type column 23 respectively by 1st area p-type column 22 and N-type column 23 extension extend, it is identical to be alternately arranged direction.In other knots In structure, the p-type column 22 and N-type column 23 in 3rd area also can end to end ring type structures.

3 Qu Zhongyou Metal field plates can also be not provided with the Metal field plate in 3rd area；There can be p-type ring 25 can also in 3rd area Not have, p-type ring when p-type ring 25 at this is (suspension) not being connected with the p-type back-gate connection in electric current flowing area；3 The outermost end in area has terminal to end ring 21, and the terminal cut-off ring 21 is added again by the injection region N+ or the injection region N+ to be formed thereon Medium or medium plus metal constitute.

As shown in Fig. 2, being the diagrammatic cross-section of existing superjunction devices；The intermediate region of existing superjunction devices is electric current flowing Area i.e. 1st area, termination environment i.e. 3rd area are surrounded on the periphery in the electric current flowing area, transition region i.e. 2nd area be located at the electric current flowing area and Between the termination environment；Existing superjunction devices includes:

N-type epitaxy layer 2, the N-type epitaxy layer 2 carry out dry etching and form multiple grooves 41,42,43；In the groove Filling by p-type epitaxial layer and forms p-type column 51 in 41,42,43, and 52,53, by described between each p-type column 51,52,53 N-type epitaxy layer 2 forms N-type column, the superjunction knot being made of multiple alternately arranged N-type columns and the p-type column 51,52,53 Structure.P-type column 51,52,53 corresponds to the p-type column 22 in Fig. 1；The N-type column 2 corresponds to the N-type column 23 in Fig. 1.

The N-type epitaxy layer 2 is formed on the surface of semiconductor substrate 1, and the semiconductor substrate 1 uses N-type heavy doping Structure.

P-type trap 6 is formed in the selection area of the electric current flowing area and the transition region.

Terminal deielectric-coating, which is formed with, on 2 surface of the N-type epitaxy layer of termination environment is generally terminal oxidation film 7, existing skill Usually the transition region is exposed for terminal oxidation film 7 in art, specifically can be with reference to shown in the dotted line frame T1 of Fig. 2；Exist in this way Contact hole in the technique in subsequent touch hole in the contact hole 12b and electric current flowing area at 6 top of the p-type trap of transition region 12a can be formed using identical technique.

It is formed on the surface of the super-junction structure in the electric current flowing area and is superimposed by gate oxidation films 8 and polysilicon gate 9 The forming region of the planar gate structure of formation, the polysilicon gate 9 is defined by photoetching process, and each polysilicon gate 9 covers The corresponding p-type trap 6 and channel is used to form by the surface for the p-type trap 6 that the polysilicon gate 9 covers.

In superjunction devices, the N-type epitaxy layer 2 of N-type column and super-junction structure bottom generally as device drift region, in electricity N-type column, that is, drift region the surface between each p-type trap 6 in stream flow region needs to be formed using photoetching and injection technology The region JFET reduces the conducting resistance of entire device for reducing the dead resistance at this.

9 two sides of the polysilicon gate in the electric current flowing area are respectively formed by source region 10, described in existing device The side of source region 10 and corresponding 9 autoregistration of the polysilicon gate, but it is described between the side of two neighboring polysilicon gate 9 Source region 10 needs interval, and the p-type trap 6 for being just able to achieve contact hole 12a and bottom in this way realizes good contact, therefore prior art Described in source region 10 need to be defined using photoetching.In general, be located at termination environment on the outside of by N+ district's groups at 10 He of cut-off region The source region 10 is formed simultaneously using identical technique.

Interlayer film 11 is formed on the surface of super-junction structure；The interlayer film is formed through in the interlayer film 11 11 contact hole 12a, 12b, the contact hole 12a, 12b are defined by photoetching process.

Grid and source electrode are graphically formed by front metal layer 14, and the forming region of the grid and the source electrode passes through light Carving technology definition；Each source region 10 and the corresponding p-type trap 6 in the electric current flowing area pass through the identical contact in top Hole 12a is connected to the source electrode, and the p-type trap 6 in the transition region is connected to the source also by the contact hole 12b at top Pole, the polysilicon gate 9 are connected to grid by the contact hole at top.

In each contact hole 12a, the bottom of 12b is formed with the contact zone P+, by connecing described in the contact zone P+ reduction Contact resistance between contact hole 121a, 121b and the p-type trap 6.

The back side of semiconductor substrate 1 after being thinned is formed with metal layer on back 15 and is drawn by the metal layer on back 15 Drain electrode.

Embodiment superjunction devices of the invention:

As shown in figure 3, being the diagrammatic cross-section of superjunction devices of the embodiment of the present invention；In superjunction devices of the embodiment of the present invention Between region be electric current flowing area i.e. 1st area, termination environment i.e. 3rd area are surrounded on the periphery in the electric current flowing area, and transition region i.e. 2nd area are located at Between the electric current flowing area and the termination environment；The structure of the top view of superjunction devices equally can be with reference to shown in Fig. 1.This hair Bright embodiment superjunction devices includes:

N-type epitaxy layer 2 is formed with multiple grooves 41,42,43 in the N-type epitaxy layer 2；In the groove 41,42,43 Middle filling is by p-type epitaxial layer and forms p-type column 51, and 52,53, by the N-type epitaxy layer between each p-type column 51,52,53 2 composition N-type columns, the super-junction structure being made of multiple alternately arranged N-type columns and the p-type column 51,52,53.

It, will for the groove and p-type column in 1st area of clearer difference, 2nd area and 3rd area in superjunction devices of the embodiment of the present invention Groove in each region separately marks, specifically: groove 41 is the groove formed in 1st area, and groove 42 is the ditch formed in 2nd area Slot, groove 43 are the groove formed in 3rd area；P-type column 51 is the p-type column formed in 1st area, and p-type column 52 is the p-type formed in 1st area Column, p-type column 53 are the p-type column formed in 1st area.Width between different grooves can be set to different, Wp1 expression in Fig. 4 The width of groove 41 is also the width of subsequent p-type column 51；Wp2 indicates the width of groove 42, is also the width of subsequent p-type column 52, Wp3 indicates the width of groove 43, is also the width of subsequent p-type column 53；Wn1 indicates that the width of the N-type column in 1st area, Wn2 indicate 2 The width of N-type column in area, Wn3 indicate the width of the N-type column in 3rd area.

In superjunction devices of the embodiment of the present invention, it is described in detail so that superjunction devices is super node MOSFET as an example: the N Type epitaxial layer 2 is formed on the surface of semiconductor substrate 1, and the semiconductor substrate 1 uses the structure of N-type heavy doping；Preferably, The N-type epitaxy layer 2 is silicon epitaxy layer, and the semiconductor substrate 1 is silicon substrate namely usually said silicon wafer or silicon wafer. The drain region of super node MOSFET is generally formed in the back side of half conductive substrate 1, therefore directlys adopt the semiconductor substrate 1 of heavy doping, In present invention method, resistivity 0.001ohmcm~0.003ohmcm of the semiconductor substrate 1；The N-type Resistance 1ohmcm~2ohm.cm of epitaxial layer 2, with a thickness of 30 microns~70 microns, preferably 40 microns~60 microns；P-N Columnar region, that is, super-junction structure region: the height of super-junction structure is when the source and drain breakdown voltage BVds of respective devices is 600V~700V The depth of 35 microns~45 microns namely groove 41,42,43 is 35 microns~45 microns.In superjunction devices of the embodiment of the present invention, Guarantee there is certain thickness between the groove groove 41,42,43 and the semiconductor substrate 1 of high concentration that be such as more than 5 micro- Rice buffer layer, with retainer member have preferable power of resisting voltaic impingement, buffer layer generally directly be located at groove 41,42, The N-type epitaxy layer 2 of 43 bottoms forms.

It is formed with p-type trap 6 in the selection area of the electric current flowing area and the transition region, forms the p-type trap 6 Selection area pass through lithographic definition；The top of each p-type column 51 is all formed with the p-type in the electric current flowing area Trap 6 and each p-type trap 6 extend to the surface of the N-type column of corresponding 51 two sides of p-type column.

The first oxidation film 7, protection ring oxidation film 7 are formed on 2 surface of the N-type epitaxy layer for being formed with the p-type trap 6 By to first oxidation film 7 carry out chemical wet etching formed, the protection ring oxidation film 7 by the electric current flowing area expose with And the transition region is all covered；The protection ring oxidation film 7 also extends into the termination environment surface and by the termination environment Completely or only the outermost circumferential portion of the termination environment is exposed, the protection ring oxidation film 7 is looped around the electric current flowing area Side.

The region JFET is formed in the electric current flowing area, the region JFET by being with the protection ring oxidation film 7 The comprehensive first time N-type ion of autoregistration condition is injected to be formed；The first time N-type ion injection is simultaneously in the protection ring In the termination environment except 7 overlay area of oxidation film or outside forms the first N-type of terminal injection region.

9 two sides of the polysilicon gate in the electric current flowing area are respectively formed by source region 10, and the source region 10 passes through It injects to be formed with comprehensive second of N-type ion that the polysilicon gate 9 and the protection ring oxidation film 7 are autoregistration condition, Second of N-type ion injection is simultaneously in the termination environment except 7 overlay area of protection ring oxidation film or outside Form the second N-type of terminal injection region 10.The second N-type of terminal injection region is also indicated with label 10 in Fig. 3 and source region 10 is to adopt It is formed simultaneously with same process and is adulterated for N+.The second N-type of terminal injection region 10 can be used to prevent the surface transoid of termination environment, Preferably improve the stability of the breakdown characteristics of device.The 2nd N type injection region 10 of terminal can also be formed in the most peripheral of device Termination environment, also become cut-off region.

Interlayer film 11 is covered on the polysilicon gate 9, the source region 10, the protection ring oxidation film 7 and the terminal Second N-type injection region, 10 surface；Contact hole 121a, the 121b of the interlayer film 11 are formed through in the interlayer film 11, The contact hole 121a, 121b are defined by photoetching process.

Front metal layer 14 has been formed on the contact hole 121a, the surface of the interlayer film 11 of 121b, grid It is graphically formed with source electrode by the front metal layer 14, the forming region of the grid and the source electrode is fixed by photoetching process Justice；Each source region 10 and the corresponding p-type trap 6 in the electric current flowing area are connected by the identical contact hole 121a in top It is connected to the source electrode, the p-type trap 6 in the transition region is connected to the source electrode, institute also by the contact hole 121b at top It states polysilicon gate 9 and grid is connected to by the contact hole at top.

The bottom of the contact hole 121a described in the electric current flowing area passes through the source region 10, to eliminate comprehensive injection The source region 10 to the contact hole 121a, the influence of 121b and the contact of the p-type trap 6 of bottom.In the transition region It is middle need successively to perform etching the interlayer film 11 and the protection ring oxidation film 7 opening to form the contact hole 121b and The over etching amount of the N-type epitaxy layer 2 of contact hole 121b bottom described in the transition region is more than or equal to 0 angstrom namely described Contact hole 121b only needs to expose the top surface of the p-type trap 6 of bottom, and the contact control 121a then needs the bottom of across The source region 10 in portion.

In each contact hole 121a, the bottom of 121b is formed with the contact zone P+, by described in the contact zone P+ reduction Contact resistance between contact hole 121a, 121b and the p-type trap 6.

Preferably, polysilicon bus 9a, institute are formed at the top for the protection ring oxidation film 7 for being located at the transition region It states polysilicon bus 9a and the polysilicon gate 9 to be formed simultaneously using identical technique, each polysilicon gate 9 and described more Crystal silicon bus 9a is connected, and the polysilicon bus 9a is connected to the grid by the contact hole 121c at top.The present invention In embodiment superjunction devices, each polysilicon gate 9 is not directed through contact hole and is connected to the grid, but by by each institute It states polysilicon gate 9 and is connected to the polysilicon bus 9a, contact hole 121c and company are being connected to by the polysilicon bus 9a It is connected to the grid.In this way, the contact hole connected with grid is not set up directly on the top of the polysilicon gate 9, but it is arranged At the top of the polysilicon bus 9a, it can guarantee that device reliability is not influenced by contact hole technique.

The back side of the semiconductor substrate 1 after being thinned is formed with metal layer on back 15 and by the metal layer on back 15 draw drain electrode.

From the foregoing, it will be observed that being designed in the embodiment of the present invention by the structure to the protection ring oxidation film 7, can be realized The autoregistration of the region JFET and the source region is injected, to can be reduced Twi-lithography technique.

In device of the embodiment of the present invention shown in Fig. 3, the second N-type of terminal injection region 10 has been superimposed the first N type of terminal note Enter area, and ends ring 21 as cut-off region, cut-off region namely terminal shown in FIG. 1.

In device architecture above, the contact hole 121b in transition region needs to penetrate interlayer film 11 and protection ring oxidation film 7, the SI of bottom is touched, the thickness of entire deielectric-coating is greater than the medium film thickness in electric current flowing area, this is wanted in technical process It adjusts and etches Sio2 etch rate/Si etch rate selection ratio when deielectric-coating in contact hole etching etches, this general ratio When value ensures that transition region deielectric-coating etching is completed in 10~20 ranges, the SI etch amount in electric current flowing area should not mistake Greatly, in superjunction devices of the embodiment of the present invention, since it is desired that electric current flowing area contact hole is penetrated N+ i.e. source region 10, Si etch amount Itself is needed about(being adjusted according to the dosage and energy of N+ injection), it is micro- 1 in 7 thickness of protection ring oxidation film When within rice, this selection is just able to satisfy requirement than being greater than 3.5.

In the embodiment of the present invention, in the oxidation of the N-type epitaxy layer 2 of the protection ring oxidation film 7 and the termination environment Include the top area that a n-type doping concentration reduces in the N-type epitaxy layer 2 at film epitaxial layer interface, passes through reduction The n-type doping concentration of the top area increases the having lateral depletion ability of the N-type column 2 at the oxidation film epitaxial layer interface By force, the uniformity of the electric-field intensity distribution at the oxidation film epitaxial layer interface is improved, the termination environment is improved and bears laterally The ability of voltage.

Preferably, the N-type net doping of the top area is superimposed the first P by the n-type doping impurity of the N-type epitaxy layer 2 Type implanted dopant 61 forms.The doping concentration of the top area is mixing for the N-type epitaxy layer 2 of the top area bottom The 80%~95% of miscellaneous concentration.The depth bounds of the top area are 2 microns~3 microns.The first p-type implanted dopant 61 Implanted dopant be B or BF2, Implantation Energy be 5Kev~100Kev, implantation dosage 8E10cm^-2~3E11cm^-2.Described The injection zone of one p-type implanted dopant 61 passes through lithographic definition；Alternatively, the injection technology of the first p-type implanted dopant 61 is Injection comprehensively.

The embodiment of the present invention has done special setting to the surface doping of the N-type epitaxy layer 2 of termination environment, mainly outside N-type Prolong N type epitaxial layer 2 of the top area of layer 2 i.e. at the oxidation film epitaxial layer interface of protection ring oxidation film 7 and N-type epitaxy layer 2 In increase a p-type and inject the first p-type implanted dopant 61 to be formed, the N-type of the top area of N-type epitaxy layer 2 can be made in this way Net dopant concentration reduces, and the reduction of the doping concentration of the N-type epitaxy layer 2 of the top area at oxidation film epitaxial layer interface can make The top area of the N-type column 2 of formation is easier more to be held by having lateral depletion namely exhausting for the P-N column of termination environment in top area Easily expansion, the enhancing of the having lateral depletion ability of the top area of N-type column 2 can then make the electric field strength at oxidation film epitaxial layer interface Change more slow, electric-field intensity distribution uniform performance is improved, so the receiving that can finally improve device terminal is horizontal To voltage ability and improve device total receiving reverse biased ability, improve the reliability of device.Especially in p-type column Total impurities it is inadequate relative to the total impurities of N-type column 2 when, this N-type epitaxy layer 2 top area inject p-type it is miscellaneous Matter 61, the impurity concentration to the top area for reducing N-type epitaxy layer 2 is to enhance the having lateral depletion of the top area of N-type column 2 Effect with regard to more obvious.

The source and drain breakdown voltage (BVds) of device of the embodiment of the present invention is than without using termination environment p-type implanted dopant 61 Device has the advantage that

The BVds of device of the embodiment of the present invention can improve 10V~30V；And the conducting resistance of device is not lost.

The consistency of device of embodiment of the present invention BVds is improved significantly: since the ability that device terminal bears breakdown mentions Height, so that the easily designed breakdown voltage as termination environment of device is higher than the breakdown voltage in electric current flowing area, to greatly improve The consistency of device Bvds, also improves the power of resisting voltaic impingement of device.

And if terminal breakdown voltage is lower than charge flow region breakdown voltage, the breakdown of device is occurred often in close to Si/ The region at the interface SiO2, the SiO2 in the interface Si/SiO2 corresponds to protection ring oxidation film 7, Si corresponds to the institute of the termination environment N-type epitaxy layer 2 is stated, carrier aggregation is amenable at the interface Si/SiO2 in this way, so that the breakdown voltage of device is unstable Fixed, EAS ability is poor；And when the breakdown of termination environment is higher than charge flow region, since super node MOSFET can be guaranteed by design Breakdown of the device in electric current flowing area occurs in Si body, can greatly improve the stability of device BVDs, and be easily obtained EAS ability.

In addition, the embodiment of the present invention has carried out special setting by protection ring oxidation film 7, the meeting of protection ring oxidation film 7 will be electric It flows flow region to expose and all cover transition region, and termination environment is wholly or largely covered；Join protection epoxidation It is that autoregistration condition carries out comprehensive first time N type ion implanting that the special setting of film 7, which can be used with protection ring oxidation film 7, The formation that the region JFET in the region JFET namely the present invention is formed in electric current flowing area does not need individually to use a photoetching work Skill is defined namely the embodiment of the present invention can reduce photoetching corresponding to the region JFET.

Meanwhile in the injection of the first time N-type ion corresponding to the region JFET of the embodiment of the present invention i.e. JFET injection, by Can transition region all be covered and wholly or largely be covered termination environment, first time N type ion in protection ring oxidation film 7 The ion of injection will not be injected into transition region and in the interior zone of termination environment, if infused in the interior zone of termination environment The N-type ion for having entered JFET injection, then can be substantially reduced the breakdown voltage i.e. BVds of device；And if be filled in transition region The N-type ion of JFET injection, then can reduce the power of resisting voltaic impingement i.e. EAS of device, so the embodiment of the present invention can subtract The Performance And Reliability of device is set to be maintained under conditions of photoetching corresponding to few region JFET.In addition, the embodiment of the present invention It can also be that autoregistration condition carries out the comprehensive i.e. source injection of second of N-type ion injection with polysilicon gate and protection ring oxidation film 7 It is equally adopted when being respectively formed source region namely formation source region of the embodiment of the present invention polysilicon gate two sides in electric current flowing area It can be achieved with autoregistration, do not need individually to define using a photoetching process, so defining source present invention saves primary The photoetching in area.The embodiment of the present invention can also realize autoregistration injection namely the energy of the embodiment of the present invention in the region JFET and source region Twi-lithography technique is reduced, the Performance And Reliability of device can be made to be maintained, cost of manufacture can be reduced, shortens the production cycle.

The manufacturing method of first embodiment of the invention superjunction devices:

The manufacturing method of first embodiment of the invention superjunction devices is to manufacture superjunction device of the embodiment of the present invention as shown in Figure 3 It is illustrated for part, is in each step of manufacturing method of first embodiment of the invention superjunction devices as shown in Fig. 4 A to Fig. 4 I The diagrammatic cross-section of device；In the manufacturing method of first embodiment of the invention superjunction devices, the intermediate region of superjunction devices is electricity Flow region i.e. 1st area is flowed, termination environment i.e. 3rd area are surrounded on the periphery in the electric current flowing area, and transition region i.e. 2nd area are located at the electric current Between flow region and the termination environment；The structure of the top view of superjunction devices equally can be with reference to shown in Fig. 1.The present invention first is real A method is applied to include the following steps:

Step 1: as shown in Figure 4 A, providing N-type epitaxy layer 2, carries out first time photoetching process and defines groove 41,42, 43 forming region carries out dry etching to the N-type epitaxy layer 2 later and forms multiple grooves 41,42,43.

As shown in Figure 4 B, the filling p-type epitaxial layer formation p-type column 51 in the groove 41,42,43,52,53, by each institute The N-type epitaxy layer 2 stated between p-type column 51,52,53 forms N-type column, by multiple alternately arranged N-type columns and the P The super-junction structure that type column 51,52,53 forms.

It, will for the groove and p-type column in 1st area of clearer difference, 2nd area and 3rd area in first embodiment of the invention method Groove in each region separately marks, specifically: groove 41 is the groove formed in 1st area, and groove 42 is the ditch formed in 2nd area Slot, groove 43 are the groove formed in 3rd area；P-type column 51 is the p-type column formed in 1st area, and p-type column 52 is the p-type formed in 1st area Column, p-type column 53 are the p-type column formed in 1st area.Width between different grooves can be set to different, Wp1 expression in Fig. 4 A The width of groove 41 is also the width of subsequent p-type column 51；Wp2 indicates the width of groove 42, is also the width of subsequent p-type column 52, Wp3 indicates the width of groove 43, is also the width of subsequent p-type column 53；Wn1 indicates that the width of the N-type column in 1st area, Wn2 indicate 2 The width of N-type column in area, Wn3 indicate the width of the N-type column in 3rd area.

In first embodiment of the invention method, it is described in detail so that the superjunction devices of production is super node MOSFET as an example: The N-type epitaxy layer 2 is formed on the surface of semiconductor substrate 1, and the semiconductor substrate 1 uses the structure of N-type heavy doping；Compared with Good to be, the N-type epitaxy layer 2 is silicon epitaxy layer, and the semiconductor substrate 1 is silicon substrate namely usually said silicon wafer or silicon wafer Disk.The drain region of super node MOSFET is generally formed in the back side of half conductive substrate 1, therefore directlys adopt the semiconductor lining of heavy doping Bottom 1, in first embodiment of the invention method, resistivity 0.001ohmcm~0.003ohmcm of the semiconductor substrate 1； Resistance 1ohmcm~2ohm.cm of the N-type epitaxy layer 2, with a thickness of 30 microns~70 microns, preferably 40 microns~60 Micron；P-N columnar region, that is, super-junction structure region: super-junction structure when the source and drain breakdown voltage BVds of respective devices is 600V~700V Height be 35 microns~45 microns namely the depth of groove 41,42,43 is 35 microns~45 microns.The present invention first is implemented In example method, it is ensured that there is certain thickness between the groove groove 41,42,43 and the semiconductor substrate 1 of high concentration Such as it is more than 5 microns of buffer layer, there is preferable power of resisting voltaic impingement with retainer member, buffer layer is generally directly to be located at ditch The N-type epitaxy layer 2 of 41,42,43 bottom of slot forms.

In first embodiment of the invention method, carrying out the first time photoetching process further includes before in the N-type extension The step of 2 surface of layer form first medium film 3, successively to 3 He of first medium film after the first time photoetching process The N-type epitaxy layer 2 carries out dry etching and forms multiple grooves 41,42,43.

As shown in Figure 4 B, the p-type epitaxial layer is filled in the groove 41,42,43 carries out chemical mechanical grinding later (CMP) technique removes the p-type epitaxial layer on 2 surface of N-type epitaxy layer, is only filled with the p-type epitaxial layer in correspondence The groove 41,42,43 in and form the p-type column 51,52,53；The first medium film 3 is ground in the chemical machinery It is removed after the completion of grinding process or part retains.

In first embodiment of the invention method, the composition material of the first medium film 3 and corresponding process energy material Expect following option:

The first option are as follows: the first medium film 3 is single oxidation film for example more than the oxidation film of 1 micron thickness, The oxidation film can be in etching groove as hard mask, and groove leaves after being formed there are also certain thickness oxidation film, such as thick The oxidation film in 0.1 micron~0.2 micron thickness is spent, fills and completes in extension, during carrying out CMP, the oxidation film conduct The protective layer of N-type epitaxy layer 2 when CMP causes electric leakage or quality to ask so that the silicon at this will not form defect in a cmp process Topic.

Second of option are as follows: the first medium film 3 is one layer by one layer of 0.1 micron~0.15 micron thick oxidation film Thick 0.1 micron~0.2 micron of SIN film and one thickness of top be greater than 1 micron~oxidation film composition, as multi-layer film structure； Uniformity can be preferably controlled in the production process in this way: for example after the completion of etching groove, at least maintaining part SIN film It stays on the oxidation film under it, is removed before epitaxial growth, then the SIN film, the uniformity of oxidation film before such epitaxial growth Good, the uniformity for carrying out the CMP of extension can also improve.Further improvement to above-mentioned multi-layer film structure is first layer oxidation Film is formed by thermal oxide, in this way further improvement uniformity.

Step 2: as shown in Figure 4 C, it is fixed in the electric current flowing area and the transition region to carry out second of photoetching process Justice goes out the forming region of p-type trap 6, carries out P-type ion later and injects to form the p-type trap 6.

The top of each p-type column 51 is all formed with the p-type trap 6 and each P type in the electric current flowing area Trap 6 extends to the surface of the N-type column of corresponding 51 two sides of p-type column.In first embodiment of the invention method, in 2nd area The p-type trap 6 is then formd, which covers 2 each p-type columns 52.

It further include that annealing process, the lehr attendant are carried out to the p-type trap 6 after the completion of the P-type ion injection of the p-type trap 6 The temperature of skill is 1000 DEG C or more, the time is 30 minutes or more.

In first embodiment of the invention method, the process conditions of the p-type trap 6 need to meet wanting for device threshold voltage It asks, the device for threshold voltage requirements at 2 volts~4 volts, B30-100KEV, the technique item of 3-10E13/cm2 can be used Part, i.e. implanted dopant are boron (B), and Implantation Energy is 30Kev~100Kev, implantation dosage 3E13cm^-2~10E13cm^-2；Together When to guarantee that device when breakdown voltage occurs, not occur Punchthrough (Punch through) at channel, otherwise will cause Element leakage is big, and breakdown voltage is lower.

Step 3: as shown in Figure 4 D, it is miscellaneous that progress third time photoetching process defines the injection of the first p-type in the termination environment The injection zone of matter 61；The first p-type implanted dopant 61 is injected in the injection for carrying out the first p-type implanted dopant 61 later The N to the oxidation film epitaxial layer interface of subsequent protection ring oxidation film 7 and the N-type epitaxy layer 2 of the termination environment In the top area of type epitaxial layer 2, reduce the n-type doping concentration of the top area, by the N for reducing the top area Type doping concentration enhances the having lateral depletion ability of the N-type column 2 at the oxidation film epitaxial layer interface, makes the oxidation The uniformity of electric-field intensity distribution at film epitaxial layer interface improves, and improves the ability that lateral voltage is born in the termination environment.

Preferably, the doping concentration of the top area is the doping of the N-type epitaxy layer 2 of the top area bottom The 80%~95% of concentration.The depth bounds of the top area are 2 microns~3 microns.The first p-type implanted dopant 61 Implanted dopant is B or BF2, and Implantation Energy is 5Kev~100Kev, implantation dosage 8E10cm^-2~3E11cm^-2。

Step 4: as shown in Figure 4 E, carrying out the first oxidation on 2 surface of the N-type epitaxy layer for being formed with the p-type trap 6 Film 7 is grown, and carries out the etch areas that fourth lithography technique defines first oxidation film 7, later to first oxidation Film 7 performs etching to form protection ring oxidation film 7, and the electric current flowing area is exposed and will be described by the protection ring oxidation film 7 Transition region all cover, the protection ring oxidation film 7 also extend into the termination environment surface and by the termination environment completely or only The outermost circumferential portion of the termination environment is exposed, the protection ring oxidation film 7 is looped around the side in the electric current flowing area.It is described The structure around the electric current flowing area of protection ring oxide layer 7 can be understood with reference to Fig. 1.

Preferably, thermal oxidation technology of first oxidation film 7 using temperature higher than 800 DEG C is formed, in this way can be in Si- Dangling bonds and unstable interfacial state are reduced in the interface SiO2, further increase the ability that voltage is born in terminal area, improve device The consistency of the breakdown voltage of part.The thickness of first oxidation film 7 needs big according to device BVds, that is, source and drain breakdown voltage Small to be set, general BVds is bigger, and the thickness needs of first oxidation film 7 are thicker, what general 600V or more device needed The thickness of first oxidation film 7 is more than 0.6 μm.

It is that the comprehensive first time N-type ion of autoregistration condition progress is infused in the electric current with the protection ring oxidation film 7 The region JFET is formed in flow region, while in the termination environment except 7 overlay area of protection ring oxidation film or outside Form the first N-type of terminal injection region.In first embodiment of the invention method, due to there is protection ring oxidation film 7 by transition region and end Petiolarea is protected, therefore JFET injection can carry out in the case where no photoetching, save the cost of photoetching process, because If being filled with JFET for terminal area, device BVds can significantly be caused to decline, if JFET is injected into the region of transition region, The power of resisting voltaic impingement of device can be reduced.

In first embodiment of the invention method, the technique of the corresponding first time N-type ion injection in the region JFET Condition is phosphorus (phos), 30-100Kev 1-4E12/cm2, namely: implanted dopant is phosphorus, Implantation Energy be 30Kev~ 100Kev, implantation dosage 1E12cm^-2~4E12cm^-2；Alternatively, the corresponding first time N type ion in the region JFET Injection by Implantation Energy be 30Kev~60Kev and Implantation Energy be 1Mev~1.5Mev inject twice be composed, high energy The injection of amount can further lower the ratio conducting resistance of device, and charge balance is improved around p-type trap 6, improve device Bvds, carry out experimental verification it is available: for 600V device, Bvds can improve 10V~20V.

Step 5: as illustrated in figure 4f, sequentially forming the first layer polysilicon of gate oxidation films 8 and N-type heavy doping, the 5th is carried out Secondary photoetching process defines the forming region of polysilicon gate 9, performs etching to form polysilicon to the first layer polysilicon later Grid 9, each polysilicon gate 9 are planar gate structure, and each polysilicon gate 9 covers the corresponding p-type trap 6 and by described more The surface for the p-type trap 6 that crystal silicon grid 9 cover is used to form channel.

In first embodiment of the invention method can, by thermal oxide formed gate oxidation films 8, later use depositing technics shape At the first layer polysilicon.Gate oxidation films 8 are heat oxide films, the thickness of the gate oxidation films 8 of the MOSFET of general 500V~700V Degree isFirst layer polysilicon with a thickness of

5th photoetching process defines the forming region of polysilicon bus 9a (BUS) simultaneously, later to described the The polysilicon bus 9a, the polysilicon bus 9a it can be located at the institute of the transition region simultaneously when one layer of polysilicon performs etching The top of protection ring oxidation film 7 is stated, each polysilicon gate 9 and the polysilicon bus 9a are connected.

It can also are as follows: the 5th photoetching process defines the forming region of polysilicon field plate simultaneously, later to described the One layer of polysilicon can be formed simultaneously the polysilicon field plate when performing etching, the polysilicon field plate is located at the protection epoxidation The top of film 7, each polysilicon field plate and the polysilicon gate 9 are isolated.

It as shown in Figure 4 G, is that autoregistration condition carries out comprehensive the with the polysilicon gate 9 and the protection ring oxidation film 7 9 two sides of the polysilicon gate that secondary N-type ion is infused in the electric current flowing area are respectively formed source region 10, while described In the termination environment except 7 overlay area of protection ring oxidation film or outside forms the second N-type of terminal injection region 10, in Fig. 4 G The second N-type of terminal injection region is also indicated with label 10 and source region 10 is formed simultaneously using same process.The second N-type of terminal note Enter the surface transoid that area 10 can be used to prevent termination environment, preferably improves the stability of the breakdown characteristics of device.The 2nd N of terminal Type injection region 10 can also be formed in the termination environment of the most peripheral of device, also become cut-off region.

Preferably, the implanted dopant of corresponding second of N-type ion injection of the source region 10 is arsenic, phosphorus, Huo Zhewei The combination of arsenic and phosphorus, the process conditions of arsenic injection when including arsenic injection in second of N-type ion injection are as follows: Implantation Energy is 30Kev~100Kev, implantation dosage 3E15cm^-2~5E15cm^-2。

Step 6: as shown at figure 4h, depositing interlayer film 11, carries out the 6th photoetching process and defines contact hole 121a, The forming region of 121b, 121c perform etching the interlayer film 11 to form contact hole 121a, the 121b later, 121c's Opening；As shown in figure 3, filling metal in the contact hole 121a, in the opening of 121b, 121c forms the contact hole 121a, 121b,121c.In Fig. 3, the contact hole of different zones is marked with different labels respectively, and the contact hole 121a corresponds to 1st area The middle contact hole for drawing source region 10 and p-type trap 6, the contact hole 121b correspond in 2nd area the contact hole for drawing p-type trap 6, institute Contact hole 121c is stated corresponding to the contact hole at the top of polysilicon bus 9a.As shown in figure 3, in first embodiment of the invention method, The step of metal is filled in the contact hole 121a, the opening of 121b, 121c includes: deposit Ti-TiN barrier layer and is moved back Fiery (Anneal), the process conditions of annealing are 630 DEG C~720 DEG C of short annealings；Contact hole is filled out in deposit tungsten (W) later It is full of, for 0.6 micron of opening, W thickness can be set as 4000 angstroms；Plasma dry is carried out later returns quarter for surface Metal completely removes.It is bigger in the size of all contact holes, for example, depth-width ratio be less than or equal to 0.5, can use AlCu or When ALSiCu realization is filled up completely, it is only necessary to deposit Ti-TiN, be carved without W deposit and corresponding return, namely directly adopt AlCu used by front metal layer 14 or ALSiCu carries out the filling of contact hole.

In first embodiment of the invention method, interlayer film 11 is the combination of the oxidation film and bpsg film that undope.Such as Fig. 4 I It is shown, it further include that progress P+ ion implanting exists after the contact hole 121a, the opening formation of 121b, 121c, before metal filling The step of contact zone P+ 13, is formed on the bottom of each contact hole 121a, 121b, 121c, reduces institute by the contact zone P+ 13 State contact hole 121a, the contact resistance between 121b, 121c and the p-type trap 6.Preferably, the contact zone P+ 13 here P-type injection impurity be B, BF2 or B and BF2 combination, general Implantation Energy exists in 30Kev~80Kev, implantation dosage 1E15cm^-2~3E15cm^-2, the power of resisting voltaic impingement of device can be improved by optimizing the injection condition.

Preferably, as shown at figure 4h, the contact hole 121a is carried out, when the etching of the opening of 121b, 121c, in the electricity It needs to carry out over etching to the N-type epitaxy layer 2 of the bottom the contact hole 121a in stream flow region and over etching amount needs completely The bottom of the foot contact hole 121a passes through the source region 10, needs in the transition region successively to the interlayer film 11 and institute It states protection ring oxidation film 7 and performs etching the bottom contact hole 121b described in the opening to form the contact hole 121b and the transition region The over etching amount of the N-type epitaxy layer 2 in portion, which is more than or equal to 0 angstrom namely the contact hole 121b, only to be needed the p-type of bottom The top surface of trap 6 exposes, and the contact control 121a then needs the source region 10 across bottom.

General interlayer film 11 with a thickness ofSince contact hole 121b realizes subsequent front metal layer The connection in 6 region of protection ring p-type trap in 14 source electrodes formed and transition region ensure that the device terminal structure of same size at this Technique is able to bear voltage same as prior art in invention first embodiment method.

Since the contact hole 121a in electric current flowing area breaks through the N+ i.e. range of source region 10, will not exist because of source region 10 The exterior domain of polysilicon gate 9 it is comprehensive injection and cause the contact problems between p-type trap 6 and metal, ensure that electrology characteristic Normally.

Step 7: depositing to form front metal layer 14 as shown in figure 3, carrying out front metal, the 7th photoetching process is carried out The forming region of grid and source electrode is defined, later the front metal layer 14 is performed etching to form the grid and the source Pole, each source region 10 and the corresponding p-type trap 6 in the electric current flowing area are connected by the identical contact hole 121a in top It is connected to the source electrode, the p-type trap 6 in the transition region is connected to the source electrode also by the contact hole 121b at top, respectively The polysilicon gate 9 with the polysilicon bus 9a by being connected and the contact by being formed at the top of the polysilicon bus 9a Hole 121c is connected to the grid.

The material of the front metal layer 14 can be ALSi, AlSiCu, can there is barrier layer, and barrier layer can be Ti/TIN, or Person TIN.The overall thickness of the front metal layer 14 is generally at 4 μm~6 μm.

Later, the semiconductor substrate 1 is carried out back thinning, then overleaf deposit metal layer on back 15 forms electric leakage Pole.

Such a super-junction MOSFET device is formed.

In manufacturing process on first embodiment of the invention method is corresponding, by using seven photoetching, including ditch Slot photoetching, that is, first time photoetching, p-type trap photoetching be second of photoetching, the photoetching of the first p-type implanted dopant 61 i.e. third time photoetching, Protection ring oxidation film photoetching, that is, fourth lithography, polycrystalline photoetching i.e. the 5th time photoetching, contact hole photoetching i.e. the 6th time photoetching and just Face metal lithographic i.e. the 7th time photoetching, compared to the prior art namely first embodiment of the invention method saves JFET injection Photoetching is injected in photoetching and source.So first embodiment of the invention method reduces manufacturing cost.

The source and drain breakdown voltage (BVds) for the device that first embodiment of the invention method is formed is than without using termination environment P The device of type implanted dopant 61 has the advantage that

The manufacturing method of second embodiment of the invention superjunction devices:

In place of the main distinction of second embodiment of the invention method and first embodiment of the invention method are as follows: the present invention second In embodiment method, the injection of the first p-type implanted dopant 61 is carried out using the technique injected comprehensively, and by the first P The injection of type implanted dopant 61 has been placed on before formation groove 41,42,43, other processing steps and first embodiment of the invention side The step of method, is identical.

The specific steps of the manufacturing method of second embodiment of the invention superjunction devices are as follows:

Step 1: providing N-type epitaxy layer 2, carry out comprehensive first p-type implanted dopant 61 is injected into the N type extension In the top area of layer 2, reduce the n-type doping concentration of the top area.

The injection of the first p-type implanted dopant 61, using subsequent thermal process, including the sacrifice oxygen in trench process Change the pyroprocess of film, the pyroprocess of epitaxial growth, the pyroprocess etc. for pushing away trap of p-well, in this way this described first p-type note The injection zone for entering impurity 61 can be diffused into 2-3 microns, and among this region, the net N-type at 2 top of N type column in the region is miscellaneous Matter concentration is fewer than the impurity concentration of N-type epitaxy layer 2, and concentration can accomplish the 95-80% of the concentration of N-type epitaxy layer 2.Described first The implanted dopant of p-type implanted dopant 61 is B or BF2, and Implantation Energy is 5Kev~100Kev, implantation dosage 8E10cm^-2~ 3E11cm^-2。

Due in electric current flowing area, since subsequent channel region will do it the injection of JFET, the dosage of injection is 1~ 4E12cm^-2, concentration 1 order of magnitude higher than the implantation concentration of the first p-type implanted dopant 61, therefore the first p-type note Entering influence very little of the injection of impurity 61 to conducting resistance can not consider less than 3%.

Step 2: as shown in Figure 4 A, providing N-type epitaxy layer 2, carries out first time photoetching process and defines groove 41,42, 43 forming region carries out dry etching to the N-type epitaxy layer 2 later and forms multiple grooves 41,42,43.

It, will for the groove and p-type column in 1st area of clearer difference, 2nd area and 3rd area in second embodiment of the invention method Groove in each region separately marks, specifically: groove 41 is the groove formed in 1st area, and groove 42 is the ditch formed in 2nd area Slot, groove 43 are the groove formed in 3rd area；P-type column 51 is the p-type column formed in 1st area, and p-type column 52 is the p-type formed in 1st area Column, p-type column 53 are the p-type column formed in 1st area.Width between different grooves can be set to different, Wp1 expression in Fig. 4 A The width of groove 41 is also the width of subsequent p-type column 51；Wp2 indicates the width of groove 42, is also the width of subsequent p-type column 52, Wp3 indicates the width of groove 43, is also the width of subsequent p-type column 53；Wn1 indicates that the width of the N-type column in 1st area, Wn2 indicate 2 The width of N-type column in area, Wn3 indicate the width of the N-type column in 3rd area.

In second embodiment of the invention method, it is described in detail so that the superjunction devices of production is super node MOSFET as an example: The N-type epitaxy layer 2 is formed on the surface of semiconductor substrate 1, and the semiconductor substrate 1 uses the structure of N-type heavy doping；Compared with Good to be, the N-type epitaxy layer 2 is silicon epitaxy layer, and the semiconductor substrate 1 is silicon substrate namely usually said silicon wafer or silicon wafer Disk.The drain region of super node MOSFET is generally formed in the back side of half conductive substrate 1, therefore directlys adopt the semiconductor lining of heavy doping Bottom 1, in second embodiment of the invention method, resistivity 0.001ohmcm~0.003ohmcm of the semiconductor substrate 1； Resistance 1ohmcm~2ohm.cm of the N-type epitaxy layer 2, with a thickness of 30 microns~70 microns, preferably 40 microns~60 Micron；P-N columnar region, that is, super-junction structure region: super-junction structure when the source and drain breakdown voltage BVds of respective devices is 600V~700V Height be 35 microns~45 microns namely the depth of groove 41,42,43 is 35 microns~45 microns.The present invention second is implemented In example method, it is ensured that there is certain thickness between the groove groove 41,42,43 and the semiconductor substrate 1 of high concentration Such as it is more than 5 microns of buffer layer, there is preferable power of resisting voltaic impingement with retainer member, buffer layer is generally directly to be located at ditch The N-type epitaxy layer 2 of 41,42,43 bottom of slot forms.

In second embodiment of the invention method, carrying out the first time photoetching process further includes before in the N-type extension The step of 2 surface of layer form first medium film 3, successively to 3 He of first medium film after the first time photoetching process The N-type epitaxy layer 2 carries out dry etching and forms multiple grooves 41,42,43.

In second embodiment of the invention method, the composition material of the first medium film 3 and corresponding process energy material Expect following option:

Step 3: as shown in Figure 4 C, it is fixed in the electric current flowing area and the transition region to carry out second of photoetching process Justice goes out the forming region of p-type trap 6, carries out P-type ion later and injects to form the p-type trap 6.

The top of each p-type column 51 is all formed with the p-type trap 6 and each P type in the electric current flowing area Trap 6 extends to the surface of the N-type column of corresponding 51 two sides of p-type column.In second embodiment of the invention method, in 2nd area The p-type trap 6 is then formd, which covers 2 each p-type columns 52.

In second embodiment of the invention method, the process conditions of the p-type trap 6 need to meet wanting for device threshold voltage It asks, the device for threshold voltage requirements at 2 volts~4 volts, B30-100KEV, the technique item of 3-10E13/cm2 can be used Part, i.e. implanted dopant are boron (B), and Implantation Energy is 30Kev~100Kev, implantation dosage 3E13cm^-2~10E13cm^-2；Together When to guarantee that device when breakdown voltage occurs, not occur Punchthrough (Punch through) at channel, otherwise will cause Element leakage is big, and breakdown voltage is lower.

Step 4: as shown in Figure 4 E, carrying out the first oxidation on 2 surface of the N-type epitaxy layer for being formed with the p-type trap 6 Film 7 is grown, and carries out the etch areas that third time photoetching process defines first oxidation film 7, later to first oxidation Film 7 performs etching to form protection ring oxidation film 7, and the electric current flowing area is exposed and will be described by the protection ring oxidation film 7 Transition region all cover, the protection ring oxidation film 7 also extend into the termination environment surface and by the termination environment completely or only The outermost circumferential portion of the termination environment is exposed, the protection ring oxidation film 7 is looped around the side in the electric current flowing area.It is described The structure around the electric current flowing area of protection ring oxide layer 7 can be understood with reference to Fig. 1.

At the oxidation film epitaxial layer interface of the N-type epitaxy layer 2 of the protection ring oxidation film 7 and the termination environment, N-type doping concentration by reducing the top area for being superimposed with the first p-type implanted dopant 61 makes outside the oxidation film The having lateral depletion ability of the N-type column 2 of Yan Cengjiemianchu enhances, and makes the electric field strength point at the oxidation film epitaxial layer interface The uniformity of cloth improves, and improves the ability that lateral voltage is born in the termination environment.

It is that the comprehensive first time N-type ion of autoregistration condition progress is infused in the electric current with the protection ring oxidation film 7 The region JFET is formed in flow region, while in the termination environment except 7 overlay area of protection ring oxidation film or outside Form the first N-type of terminal injection region.In second embodiment of the invention method, due to there is protection ring oxidation film 7 by transition region and end Petiolarea is protected, therefore JFET injection can carry out in the case where no photoetching, save the cost of photoetching process, because If being filled with JFET for terminal area, device BVds can significantly be caused to decline, if JFET is injected into the region of transition region, The power of resisting voltaic impingement of device can be reduced.

In second embodiment of the invention method, the technique of the corresponding first time N-type ion injection in the region JFET Condition is phosphorus (phos), 30-100Kev1-4E12/cm2, namely: implanted dopant is phosphorus, Implantation Energy be 30Kev~ 100Kev, implantation dosage 1E12cm^-2~4E12cm^-2；Alternatively, the corresponding first time N type ion in the region JFET Injection by Implantation Energy be 30Kev~60Kev and Implantation Energy be 1Mev~1.5Mev inject twice be composed, high energy The injection of amount can further lower the ratio conducting resistance of device, and charge balance is improved around p-type trap 6, improve device Bvds, carry out experimental verification it is available: for 600V device, Bvds can improve 10V~20V.

Step 5: as illustrated in figure 4f, sequentially forming the first layer polysilicon of gate oxidation films 8 and N-type heavy doping, the 4th is carried out Secondary photoetching process defines the forming region of polysilicon gate 9, performs etching to form polysilicon to the first layer polysilicon later Grid 9, each polysilicon gate 9 are planar gate structure, and each polysilicon gate 9 covers the corresponding p-type trap 6 and by described more The surface for the p-type trap 6 that crystal silicon grid 9 cover is used to form channel.

In second embodiment of the invention method can, by thermal oxide formed gate oxidation films 8, later use depositing technics shape At the first layer polysilicon.Gate oxidation films 8 are heat oxide films, the thickness of the gate oxidation films 8 of the MOSFET of general 500V~700V Degree isFirst layer polysilicon with a thickness of

The fourth lithography technique defines the forming region of polysilicon bus 9a (BUS) simultaneously, later to described the The polysilicon bus 9a, the polysilicon bus 9a it can be located at the institute of the transition region simultaneously when one layer of polysilicon performs etching The top of protection ring oxidation film 7 is stated, each polysilicon gate 9 and the polysilicon bus 9a are connected.

It can also are as follows: the fourth lithography technique defines the forming region of polysilicon field plate simultaneously, later to described the One layer of polysilicon can be formed simultaneously the polysilicon field plate when performing etching, the polysilicon field plate is located at the protection epoxidation The top of film 7, each polysilicon field plate and the polysilicon gate 9 are isolated.

Step 6: as shown at figure 4h, depositing interlayer film 11, carries out the 5th photoetching process and defines contact hole 121a, The forming region of 121b, 121c perform etching the interlayer film 11 to form contact hole 121a, the 121b later, 121c's Opening；As shown in figure 3, filling metal in the contact hole 121a, in the opening of 121b, 121c forms the contact hole 121a, 121b,121c.In Fig. 3, the contact hole of different zones is marked with different labels respectively, and the contact hole 121a corresponds to 1st area The middle contact hole for drawing source region 10 and p-type trap 6, the contact hole 121b correspond in 2nd area the contact hole for drawing p-type trap 6, institute Contact hole 121c is stated corresponding to the contact hole at the top of polysilicon bus 9a.As shown in figure 3, in second embodiment of the invention method, The step of metal is filled in the contact hole 121a, the opening of 121b, 121c includes: deposit Ti-TiN barrier layer and is moved back Fiery (Anneal), the process conditions of annealing are 630 DEG C~720 DEG C of short annealings；Contact hole is filled out in deposit tungsten (W) later It is full of, for 0.6 micron of opening, W thickness can be set as 4000 angstroms；Plasma dry is carried out later returns quarter for surface Metal completely removes.It is bigger in the size of all contact holes, for example, depth-width ratio be less than or equal to 0.5, can use AlCu or When ALSiCu realization is filled up completely, it is only necessary to deposit Ti-TiN, be carved without W deposit and corresponding return, namely directly adopt AlCu used by front metal layer 14 or ALSiCu carries out the filling of contact hole.

In second embodiment of the invention method, interlayer film 11 is the combination of the oxidation film and bpsg film that undope.Such as Fig. 4 I It is shown, it further include that progress P+ ion implanting exists after the contact hole 121a, the opening formation of 121b, 121c, before metal filling The step of contact zone P+ 13, is formed on the bottom of each contact hole 121a, 121b, 121c, reduces institute by the contact zone P+ 13 State contact hole 121a, the contact resistance between 121b, 121c and the p-type trap 6.Preferably, the contact zone P+ 13 here P-type injection impurity be B, BF2 or B and BF2 combination, general Implantation Energy exists in 30Kev~80Kev, implantation dosage 1E15cm^-2~3E15cm^-2, the power of resisting voltaic impingement of device can be improved by optimizing the injection condition.

General interlayer film 11 with a thickness ofSince contact hole 121b realizes subsequent front metal layer The connection in 6 region of protection ring p-type trap in 14 source electrodes formed and transition region ensure that the device terminal structure of same size at this Technique is able to bear voltage same as prior art in invention second embodiment method.

Step 7: depositing to form front metal layer 14 as shown in figure 3, carrying out front metal, the 6th photoetching process is carried out The forming region of grid and source electrode is defined, later the front metal layer 14 is performed etching to form the grid and the source Pole, each source region 10 and the corresponding p-type trap 6 in the electric current flowing area are connected by the identical contact hole 121a in top It is connected to the source electrode, the p-type trap 6 in the transition region is connected to the source electrode also by the contact hole 121b at top, respectively The polysilicon gate 9 with the polysilicon bus 9a by being connected and the contact by being formed at the top of the polysilicon bus 9a Hole 121c is connected to the grid.

The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered It is considered as protection scope of the present invention.

Claims

1. the intermediate region of a kind of superjunction devices, superjunction devices is electric current flowing area, termination environment is surrounded on the electric current flowing area Periphery, transition region is between the electric current flowing area and the termination environment；It is characterised by comprising:

N-type epitaxy layer is formed with multiple grooves in the N-type epitaxy layer；It is filled in the trench by p-type epitaxial layer and is formed P-type column forms N-type column by the N-type epitaxy layer between each p-type column, by multiple alternately arranged N-type columns and institute State the super-junction structure of p-type column composition；The super-junction structure is located at the electric current flowing area, the transition region and the termination environment In；

Protection ring oxidation film is looped around the side in the electric current flowing area and exposes the electric current flowing area and by the mistake It crosses area all to cover, the protection ring oxidation film also extends into the termination environment surface and by the termination environment completely or only by institute The outermost circumferential portion for stating termination environment is exposed；

The N at the oxidation film epitaxial layer interface of the N-type epitaxy layer of the protection ring oxidation film and the termination environment It include the top area that a n-type doping concentration reduces in type epitaxial layer, it is dense by the n-type doping for reducing the top area Degree makes the having lateral depletion ability enhancing of the N-type column at the oxidation film epitaxial layer interface, makes the oxidation film extension stratum boundary The uniformity of electric-field intensity distribution at face improves, and improves the ability that lateral voltage is born in the termination environment.

2. superjunction devices as described in claim 1, it is characterised in that: the N-type net doping of the top area by the N-type outside The n-type doping impurity for prolonging layer is superimposed the first p-type implanted dopant composition.

3. superjunction devices as claimed in claim 1 or 2, it is characterised in that: the doping concentration of the top area is the top The 80%~95% of the doping concentration of the N-type epitaxy layer of portion's sections bottom.

4. superjunction devices as claimed in claim 1 or 2, it is characterised in that: the depth bounds of the top area be 2 microns~ 3 microns.

5. superjunction devices as claimed in claim 2, it is characterised in that: the implanted dopant of the first p-type implanted dopant be B or BF2, Implantation Energy are 5Kev~100Kev, implantation dosage 8E10cm^-2~3E11cm^-2。

6. superjunction devices as claimed in claim 2, it is characterised in that: the injection zone of the first p-type implanted dopant passes through Lithographic definition；Alternatively, the injection technology of the first p-type implanted dopant is injection comprehensively.

7. superjunction devices as described in claim 1, it is characterised in that: in the selected of the electric current flowing area and the transition region P-type trap is formed in region, the selection area for forming the p-type trap passes through lithographic definition；Each P in the electric current flowing area The top of type column is all formed with the p-type trap and each p-type trap extends to the N of corresponding p-type column two sides The surface of type column；

It is formed with to be superimposed by gate oxidation films and polysilicon gate on the surface of the super-junction structure in the electric current flowing area and be formed The forming region of planar gate structure, the polysilicon gate is defined by photoetching process, and each polysilicon gate covers corresponding institute It states p-type trap and channel is used to form by the surface for the p-type trap that the polysilicon gate covers；

The polysilicon gate two sides in the electric current flowing area are respectively formed by source region, and the source region passes through with the polycrystalline Si-gate and the protection ring oxidation film are that comprehensive second of N-type ion of autoregistration condition is injected to be formed, second of N-type Ion implanting simultaneously in the termination environment except protection ring oxidation film overlay area or outside formed the second N-type of terminal Injection region；

Interlayer film is covered on the polysilicon gate, the source region, the protection ring oxidation film and the injection of the second N-type of the terminal Area surface；The contact hole of the interlayer film is formed through in the interlayer film, the contact hole is defined by photoetching process；

Front metal layer is formed on the surface of the interlayer film of the contact hole, grid and source electrode by the front gold Belong to layer pattern to be formed, the forming region of the grid and the source electrode is defined by photoetching process；In the electric current flowing area Each source region and the corresponding p-type trap source electrode is connected to by the identical contact hole in top, in the transition region The p-type trap be connected to the source electrode also by the contact hole at top, the polysilicon gate is connected by the contact hole at top To grid.

8. superjunction devices as claimed in claim 7, it is characterised in that: form the region JFET, institute in the electric current flowing area The region JFET is stated to be formed by injecting using the protection ring oxidation film as the comprehensive first time N-type ion of autoregistration condition；Institute The injection of first time N-type ion is stated simultaneously in the termination environment except protection ring oxidation film overlay area or outside is formed The first N-type of terminal injection region.

9. superjunction devices as claimed in claim 7, it is characterised in that: the bottom of the contact hole described in the electric current flowing area Across the source region, to eliminate the source region injected to the contact hole and the contact of the p-type trap of bottom comprehensively It influences.

10. superjunction devices as claimed in claim 7, it is characterised in that: in the protection epoxidation for being located at the transition region Polysilicon bus, the polysilicon bus and the polysilicon gate is formed at the top of film to be formed simultaneously using identical technique, Each polysilicon gate and the polysilicon bus connect, and each polysilicon gate passes through and the polysilicon bus phase Even and the grid is connected to by being formed in the contact hole at the top of the polysilicon bus.

11. a kind of manufacturing method of superjunction devices, the intermediate region of superjunction devices is electric current flowing area, and termination environment is surrounded on described The periphery in electric current flowing area, transition region is between the electric current flowing area and the termination environment；It is characterised in that it includes as follows Step:

Step 1: providing N-type epitaxy layer, the forming region that first time photoetching process defines groove is carried out, later to the N-type Epitaxial layer carries out dry etching and forms multiple grooves；

Filling p-type epitaxial layer forms p-type column in the trench, forms N by the N-type epitaxy layer between each p-type column Type column, the super-junction structure being made of multiple alternately arranged N-type columns and the p-type column；The super-junction structure is located at described In electric current flowing area, the transition region and the termination environment；

Step 2: carrying out the formation that second of photoetching process defines p-type trap in the electric current flowing area and the transition region Region carries out P-type ion later and injects to form the p-type trap；

The top of each p-type column is all formed with the p-type trap in the electric current flowing area and each p-type trap extends to The surface of the N-type column of corresponding p-type column two sides；

Step 3: carrying out the injection zone that third time photoetching process defines the first p-type implanted dopant in the termination environment；It The first p-type implanted dopant is injected into subsequent protection ring oxidation film by the injection for carrying out the first p-type implanted dopant afterwards In the top area of the N-type epitaxy layer at the oxidation film epitaxial layer interface of the N-type epitaxy layer of the termination environment, make The n-type doping concentration of the top area reduces, and the n-type doping concentration by reducing the top area makes outside the oxidation film The having lateral depletion ability of the N-type column of Yan Cengjiemianchu enhances, and makes the electric field strength point at the oxidation film epitaxial layer interface The uniformity of cloth improves, and improves the ability that lateral voltage is born in the termination environment；

Step 4: carrying out the first oxide growth on the N-type epitaxy layer surface for being formed with the p-type trap, carry out the 4th time Photoetching process defines the etch areas of first oxidation film, performs etching to form protection ring to first oxidation film later The electric current flowing area is exposed and is all covered the transition region, the protection by oxidation film, the protection ring oxidation film Epoxidation film also extends into the termination environment surface and by the termination environment completely or only by the outermost circumferential portion of the termination environment Expose, the protection ring oxidation film is looped around the side in the electric current flowing area；

Comprehensive first time N-type ion, which is carried out, as autoregistration condition using the protection ring oxidation film is infused in the electric current flowing area The middle region formation JFET, at the same in the termination environment except protection ring oxidation film overlay area or outside formed terminal First N-type injection region；

Step 5: sequentially forming the first layer polysilicon of gate oxidation films and N-type heavy doping, carries out the 5th photoetching process and define The forming region of polysilicon gate performs etching to form polysilicon gate to the first layer polysilicon later, each polysilicon gate The p-type trap for covering the corresponding p-type trap for planar gate structure, each polysilicon gate and being covered by the polysilicon gate Surface be used to form channel；

Comprehensive second of N-type ion is carried out as autoregistration condition using the polysilicon gate and the protection ring oxidation film to be infused in The polysilicon gate two sides in the electric current flowing area are respectively formed source region, while in protection ring oxidation film overlay area Except the termination environment in or outside formed the second N-type of terminal injection region；

Step 6: deposit interlayer film, carries out the forming region that the 6th photoetching process defines contact hole, later to the interlayer Film performs etching the opening to form the contact hole；Metal is filled in the opening of the contact hole forms the contact hole；

It deposits to form front metal layer Step 7: carrying out front metal, carries out the 7th photoetching process and define grid and source electrode Forming region, later the front metal layer is performed etching to form the grid and the source electrode, the electric current flowing area In each source region and the corresponding p-type trap source electrode, the transition region be connected to by the identical contact hole in top In the p-type trap be connected to the source electrode also by the contact hole at top, the polysilicon gate is connected by the contact hole at top It is connected to grid.

12. a kind of manufacturing method of superjunction devices, the intermediate region of superjunction devices is electric current flowing area, and termination environment is surrounded on described The periphery in electric current flowing area, transition region is between the electric current flowing area and the termination environment；It is characterised in that it includes as follows Step:

Step 1: providing N-type epitaxy layer, the top for being injected into the N-type epitaxy layer of comprehensive first p-type implanted dopant is carried out In region, reduce the n-type doping concentration of the top area；

Step 2: carrying out the forming region that first time photoetching process defines groove, dry method is carried out to the N-type epitaxy layer later Etching forms multiple grooves；

Step 3: carrying out the formation that second of photoetching process defines p-type trap in the electric current flowing area and the transition region Region carries out P-type ion later and injects to form the p-type trap；

Step 4: carrying out the first oxide growth on the N-type epitaxy layer surface for being formed with the p-type trap, third time is carried out Photoetching process defines the etch areas of first oxidation film, performs etching to form protection ring to first oxidation film later The electric current flowing area is exposed and is all covered the transition region, the protection by oxidation film, the protection ring oxidation film Epoxidation film also extends into the termination environment surface and by the termination environment completely or only by the outermost circumferential portion of the termination environment Expose, the protection ring oxidation film is looped around the side in the electric current flowing area；

At the oxidation film epitaxial layer interface of the N-type epitaxy layer of the protection ring oxidation film and the termination environment, pass through drop The n-type doping concentration of the low top area for being superimposed with the first p-type implanted dopant makes the oxidation film epitaxial layer interface The having lateral depletion ability enhancing of the N-type column at place, makes the uniform of the electric-field intensity distribution at the oxidation film epitaxial layer interface Property improve, improve the ability that lateral voltage is born in the termination environment；

Step 5: sequentially forming the first layer polysilicon of gate oxidation films and N-type heavy doping, carries out fourth lithography technique and define The forming region of polysilicon gate performs etching to form polysilicon gate to the first layer polysilicon later, each polysilicon gate The p-type trap for covering the corresponding p-type trap for planar gate structure, each polysilicon gate and being covered by the polysilicon gate Surface be used to form channel；

Step 6: deposit interlayer film, carries out the forming region that the 5th photoetching process defines contact hole, later to the interlayer Film performs etching the opening to form the contact hole；Metal is filled in the opening of the contact hole forms the contact hole；

It deposits to form front metal layer Step 7: carrying out front metal, carries out the 6th photoetching process and define grid and source electrode Forming region, later the front metal layer is performed etching to form the grid and the source electrode, the electric current flowing area In each source region and the corresponding p-type trap source electrode, the transition region be connected to by the identical contact hole in top In the p-type trap be connected to the source electrode also by the contact hole at top, the polysilicon gate is connected by the contact hole at top It is connected to grid.

13. the manufacturing method of the superjunction devices as described in claim 11 or 12, it is characterised in that: the doping of the top area Concentration is the 80%~95% of the doping concentration of the N-type epitaxy layer of the top area bottom.

14. the manufacturing method of the superjunction devices as described in claim 11 or 12, it is characterised in that: the depth of the top area Range is 2 microns~3 microns.

15. the manufacturing method of the superjunction devices as described in claim 11 or 12, it is characterised in that: the first p-type injection is miscellaneous The implanted dopant of matter is B or BF2, and Implantation Energy is 5Kev~100Kev, implantation dosage 8E10cm^-2~3E11cm^-2。