CN109755120B - Method for forming source/drain contacts - Google Patents

Method for forming source/drain contacts Download PDF

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Publication number
CN109755120B
CN109755120B CN201811293638.3A CN201811293638A CN109755120B CN 109755120 B CN109755120 B CN 109755120B CN 201811293638 A CN201811293638 A CN 201811293638A CN 109755120 B CN109755120 B CN 109755120B
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source
etch stop
stop layer
drain regions
semiconductor structure
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CN109755120A (en
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周顺益
S·德姆恩克
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In a first aspect, the invention relates to a method for forming source and drain contacts (700) in a semiconductor structure, comprising: -masking the source region (221s) and the drain region (221d), -replacing the unmasked sacrificial material (440) with a dielectric layer (450), -removing the masking structure (550; 520m, 510m), -selectively removing the sacrificial material (440) above the source and/or drain region (221) with respect to the dielectric layer (450) by wet etching to an extent that the top surface of the source and/or drain region (221) is exposed, and-depositing a conductive material (720) on the source and/or drain region (221), thereby forming a source and/or drain contact (700) in the semiconductor structure.

Description

Method for forming source/drain contacts
Field of the invention
The present invention relates to the formation of semiconductor structures, and more particularly to the formation of source and/or drain contacts in such semiconductor structures.
Background
In the fabrication of semiconductor devices, it is necessary to form source/drain contacts connected to their respective source/drain regions. The methods for forming self-aligned contacts that have been used to date are facing major challenges from the 10 nanometer node down. High aspect ratio etches (e.g., 15:1 or greater) that require contact formation while maintaining high etch selectivity (typically relative to SiCO or SiN) appear to be at least unrealistic to implement. As such, underetching and/or overetching problems can easily occur within the die.
Furthermore, as technology scales to 10nm nodes and below, the problem of maximizing contact area with the source/drain regions, keeping contact and fin resistance within acceptable limits, becomes increasingly important. As such, wrap-around contacts appear to be a promising contact scheme to replace the diamond-shaped source/drain regions commonly used today. However, in Complementary Metal Oxide Semiconductor (CMOS) technology, post-etch cleaning of the source/drain regions (e.g., epitaxially grown Si: P and SiGe: B) is challenging in practice.
US9685374B1 describes a method for manufacturing a semiconductor structure including forming a surrounding contact. However, the remote plasma etch used therein is difficult to control. Furthermore, the Contact Etch Stop Layer (CESL) is exposed to the selective etch twice, so CESL would need to be relatively thick (>5 nm). These two problems make this approach not well suited for small contacts; for example a 10nm node, but more particularly a 7nm node, where the contact critical dimension may typically be around 14 to 16 nm.
Accordingly, there remains a need in the art for better ways to form source/drain contacts in semiconductor structures.
Disclosure of Invention
It is an object of the present invention to provide a good method for forming a source contact and/or a drain contact in a semiconductor structure. It is a further object of the invention to provide a good intermediate structure obtainable in the course of performing said method. The above object is achieved by a method and an apparatus according to the present invention.
An advantage of embodiments of the present invention is that good source/drain contacts can be formed even for small technology nodes (e.g., 10nm nodes or 7nm nodes).
An advantage of embodiments of the present invention is that the source/drain contacts can be self-aligned.
An advantage of embodiments of the present invention is that the source/drain regions to be formed in contact therewith may be well exposed (e.g., low underetching of the material covering the source/drain regions). A further advantage of embodiments of the present invention is that source/drain contacts can be formed with minimal damage to the source/drain regions (e.g., low overetch of the source/drain regions).
It is an advantage of embodiments of the present invention that the source/drain contacts may be wrap-around contacts.
An advantage of embodiments of the present invention is that the etch performed during the method, e.g. to form gaps for source/drain contacts and expose source/drain regions, may have a high etch selectivity. It is a further advantage of embodiments of the present invention that etching can be performed to form gaps with high aspect ratios (e.g., 15: 1).
An advantage of embodiments of the present invention is that the etch stop layer covering the source/drain regions may be exposed to only a single selective removal step, allowing it to be relatively thin.
In a first aspect, the present invention relates to a method for forming a source contact and a drain contact in a semiconductor structure, comprising:
masking the source and drain regions,
-replacing the unmasked sacrificial material with a dielectric layer,
-removing the mask structure(s),
removing the sacrificial material over the source and/or drain regions selectively with respect to the dielectric layer by wet etching to an extent that the top surfaces of the source and/or drain regions are exposed, and
-depositing a conductive material on the source and/or drain regions, thereby forming source and/or drain contacts in the semiconductor structure.
In other words, the present invention relates to a method for forming a source contact and/or a drain contact in a semiconductor structure, comprising:
a. a semiconductor structure is provided, comprising:
i. a semiconductor active region including a channel region, a source region and a drain region, the source and drain regions having a top surface;
a gate structure on the channel region, the gate structure having a top surface and sidewalls;
a gate plug on a top surface of the gate structure, the gate plug having sidewalls;
spacers lining sidewalls of the gate structure and the gate plug;
v. an etch stop layer covering the top surfaces of the source and drain regions;
a sacrificial material on the etch stop layer over the source and drain regions and on other portions of the semiconductor structure;
masking the source and drain regions while leaving the other portions of the semiconductor structure unmasked;
b. selectively removing sacrificial material present on other portions of the semiconductor structure, thereby forming a gap;
c. optionally removing all or part of the mask structure;
d. depositing a dielectric layer on the semiconductor structure, thereby filling the gap;
e. exposing a sacrificial material present on the etch stop layer over the source and drain regions;
f. selectively removing the sacrificial material present on the etch stop layer over the source and drain regions;
g. selectively removing the etch stop layer covering at least the top surfaces of the source and drain regions to the extent that the top surfaces of the source and drain regions are exposed;
h. depositing a conductive material on the source and drain regions, thereby forming source and drain contacts in the semiconductor structure;
wherein step f is performed by a wet etching process;
wherein step g is performed by a wet etching process; and
wherein the material of the gate plug, the material of the spacer, the sacrificial material, the material of the etch stop layer, the material of the dielectric layer, and the material of the source and drain regions are selected in such a way that:
-during the wet etching process of step f, the sacrificial material etches faster than the material of the gate plug, the material of the spacer, the material of the etch stop layer and the material of the dielectric layer;
the etch stop layer may be completely removed without completely removing the gate plug, and
during the wet etching process of step g, the material of the etch stop layer is etched faster than the material of the spacers, the material of the dielectric layer and the material of the source and drain regions.
The etch stop layer and the gate plug may be made of the same material or different materials. If they are made of the same material, the etch stop layer may be completely removed without completely removing the gate plug because the thickness of the etch stop layer is generally less than the thickness of the gate plug. This constraint on the difference in thickness between the etch stop layer and the gate plug does not necessarily exist if they are made of different materials, but the thickness of the etch stop layer is still typically less than the thickness of the gate plug.
In various embodiments, the present invention relates to a method for forming a source contact and/or a drain contact in a semiconductor structure, comprising:
a. a semiconductor structure is provided, comprising:
i. a semiconductor active region including a channel region, a source region and a drain region, the source and drain regions having a top surface;
a gate structure on the channel region, the gate structure having a top surface and sidewalls;
a gate plug on a top surface of the gate structure, the gate plug having sidewalls;
spacers lining sidewalls of the gate structure and the gate plug;
v. an etch stop layer covering the top surfaces of the source and drain regions;
a sacrificial material on the etch stop layer over the source and drain regions and on other portions of the semiconductor structure;
masking the source and drain regions while leaving the other portions of the semiconductor structure unmasked;
b. selectively removing sacrificial material present on other portions of the semiconductor structure, thereby forming a gap;
c. optionally removing all or part of the mask structure;
d. depositing a dielectric layer on the semiconductor structure, thereby filling the gap;
e. exposing a sacrificial material present on the etch stop layer over the source and drain regions;
f. selectively removing the sacrificial material present on the etch stop layer over the source and drain regions;
g. selectively removing the etch stop layer covering at least the top surfaces of the source and drain regions to the extent that the top surfaces of the source and drain regions are exposed;
h. depositing a conductive material on the source and drain regions, thereby forming source and drain contacts in the semiconductor structure;
wherein step f is performed by a wet etching process;
wherein step g is performed by a wet etching process; and
wherein the material of the gate plug, the material of the spacer, the sacrificial material, the material of the etch stop layer, the material of the dielectric layer, and the material of the source and drain regions are selected in such a way that:
-during the wet etching process of step f, the sacrificial material etches faster than the material of the gate plug, the material of the spacer, the material of the etch stop layer and the material of the dielectric layer; and
during the wet etching process of step g, the material of the etch stop layer is etched faster than the material of the gate plug, the material of the spacer, the material of the dielectric layer and the material of the source and drain regions.
In a second aspect, the present invention relates to a semiconductor structure comprising:
i. a semiconductor active region including a channel region, a source region and a drain region, the source and drain regions having a top surface;
a gate structure on the channel region, the gate structure having a top surface and sidewalls;
a gate plug on a top surface of the gate structure, the gate plug having sidewalls;
spacers lining sidewalls of the gate structure and the gate plug;
v. an etch stop layer covering at least the top surfaces of the source and drain regions;
a sacrificial material on the etch stop layer over the source and drain regions;
a dielectric layer covering other portions of the semiconductor structure leaving the source and drain regions uncovered;
wherein the material of the gate plug, the material of the spacer, the sacrificial material, the material of the etch stop layer, the material of the dielectric layer, and the material of the source and drain regions are selected in such a way that:
during the wet etch process, the sacrificial material may be etched faster than the material of the gate plug, the material of the spacer, the material of the etch stop layer and the material of the dielectric layer;
the etch stop layer may be completely removed without completely removing the gate plug, and
during the wet etch process, the material of the etch stop layer may be etched faster than the material of the spacers, the material of the dielectric layer and the material of the source and drain regions.
In various embodiments, the case where the etch stop layer may be completely removed without completely removing the gate plug may be satisfied by making the thickness of the etch stop layer smaller than that of the gate plug, by making the material of the etch stop layer etch faster than that of the gate plug, or by a combination of both.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and features of other dependent claims as appropriate and not merely as explicitly set out in the claims.
While there has been constant improvement, change and development of devices in this field, it is believed that the inventive concept represents a substantially novel and inventive advance including departures from prior practices to provide more efficient, stable and reliable devices of this nature.
The above and other characteristics, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is given for the sake of illustration only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.
Brief description of the drawings
Fig. 1 to 6 are schematic representations of front perspective views of a semiconductor structure along different steps of a method according to a first exemplary embodiment of the present invention.
Fig. 7 to 9 are schematic representations of front (a) and side (b) perspective views of a semiconductor structure along different steps of a method according to said first exemplary embodiment of the present invention.
Fig. 10 and 13 are schematic representations of front (a) and side (b) perspective views of a semiconductor structure along different steps of a method according to a second exemplary embodiment of the present invention.
Fig. 11 and 12 are schematic representations of front perspective views of a semiconductor structure along different steps of a method according to a second exemplary embodiment of the present invention.
The same reference numbers in different drawings identify the same or similar elements.
Detailed Description
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and relative dimensions do not correspond to actual reductions to practice of the invention.
Moreover, the terms first, second, and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence temporally, spatially, in ranking, or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Furthermore, the terms top, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances with respect to their antisense words and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
It is to be noticed that the term 'comprising', used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Accordingly, the terms are to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but do not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "an apparatus comprising means a and B" should not be limited to an apparatus consisting of only components a and B. This means that for the present invention, the only relevant components of the device are a and B.
Similarly, it is to be noticed that the term 'coupled', also used in the claims, should not be interpreted as being restricted to direct connections only. The terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Thus, the scope of the term "a coupled to B" should not be limited to devices or systems in which the output of device a is directly connected to the input of device B. This means that there exists a path between the output of device a and the input of B, which may be a path including other devices or means. "coupled" may mean that two or more elements are in direct physical or electrical contact, or that two or more elements are not in direct contact with each other but yet still co-operate or interact with each other.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as will be apparent to one of ordinary skill in the art from this disclosure.
Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Furthermore, although some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are intended to be within the scope of the invention and form different embodiments as will be understood by those of skill in the art. For example, in the appended claims, any of the claimed embodiments may be used in any combination.
Further, some of the embodiments are described herein as a method or combination of elements of a method that can be performed by a processor of a computing system or other device that performs that function. A processor having the necessary instructions for carrying out such a method or elements of a method thus forms a means for carrying out the method or elements of the method. Further, the elements of an apparatus embodiment described herein are means for performing the functions performed by the means for performing the objects of the invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Reference will be made to transistors. These are devices having a first main electrode, such as a drain, a second main electrode, such as a source, and a control electrode, such as a gate for controlling the flow of charge between the first and second main electrodes.
It will be clear to those skilled in the art that the invention also applies to similar devices that may be configured in any transistor technology (e.g., including but not limited to CMOS, BICMOS, bipolar, and SiGe BICMOS technologies).
The following terms are provided merely to aid in the understanding of the present invention.
As used herein, and unless otherwise specified, 'source/drain' is understood to be 'source and/or drain'. Likewise, 'source/drain entities', such as source/drain regions, are understood to be 'source entities and/or drain entities', such as source regions and/or drain regions. In various embodiments, the source and drain may be comparable (e.g., indistinguishable) and their indications may depend on the relative voltage difference across them in the final semiconductor device.
As used herein, and unless otherwise specified, when a first material is said to be selectively removed or etched relative to a second material, this means that the first material is removed or etched faster than the second material. Preferably, the removal or etching process will remove or etch the first material at least two times faster than the second material, or more preferably at least five times faster, and still more preferably at least 10 times faster. In some preferred embodiments, the second material may not be substantially removed or etched by the removal or etching process.
In a first aspect, the present invention relates to a method for forming a source contact and/or a drain contact in a semiconductor structure, comprising:
a. a semiconductor structure is provided, comprising:
i. a semiconductor active region including a channel region, a source region and a drain region, the source and drain regions having a top surface;
a gate structure on the channel region, the gate structure having a top surface and sidewalls;
a gate plug on a top surface of the gate structure, the gate plug having sidewalls;
spacers lining sidewalls of the gate structure and the gate plug;
v. an etch stop layer covering the top surfaces of the source and drain regions;
a sacrificial material on the etch stop layer over the source and drain regions and on other portions of the semiconductor structure;
masking the source and drain regions while leaving the other portions of the semiconductor structure unmasked;
b. selectively removing sacrificial material present on other portions of the semiconductor structure, thereby forming a gap;
c. optionally removing all or part of the mask structure;
d. depositing a dielectric layer on the semiconductor structure, thereby filling the gap;
e. exposing a sacrificial material present on the etch stop layer over the source and drain regions;
f. selectively removing the sacrificial material present on the etch stop layer over the source and drain regions;
g. selectively removing the etch stop layer covering at least the top surfaces of the source and drain regions to the extent that the top surfaces of the source and drain regions are exposed;
h. depositing a conductive material on the source and drain regions, thereby forming source and drain contacts in the semiconductor structure;
wherein step f is performed by a wet etching process;
wherein step g is performed by a wet etching process; and
wherein the material of the gate plug, the material of the spacer, the sacrificial material, the material of the etch stop layer, the material of the dielectric layer, and the material of the source and drain regions are selected in such a way that:
-during the wet etching process of step f, the sacrificial material etches faster than the material of the gate plug, the material of the spacer, the material of the etch stop layer and the material of the dielectric layer; and
the etch stop layer may be completely removed without completely removing the gate plug, and
during the wet etching process of step g, the material of the etch stop layer is etched faster than the material of the spacers, the material of the dielectric layer and the material of the source and drain regions.
The semiconductor structure may also be generally referred to as a semiconductor device. The semiconductor structure may be, for example, a semiconductor circuit including one or more transistors, such as a Complementary Metal Oxide Semiconductor (CMOS) structure. The transistor may be, for example, a fin field effect architecture pattern (FinFET).
In various embodiments, the semiconductor active region (e.g., the channel region and/or the source/drain regions) may comprise a material selected from Si, SiGe, and Ge. In an embodiment, the first source/drain region (e.g., source region) and the second source/drain region (e.g., drain region) may define a channel region therebetween. In various embodiments, the semiconductor active region may include a semiconductor fin. In various embodiments, the semiconductor fin may include a channel region. In various embodiments, the semiconductor fin may include a material selected from Si, SiGe, and Ge. In various embodiments, a dielectric material may be present between two semiconductor fins. In various embodiments, the dielectric material may be SiO 2. The dielectric material (e.g., shallow trench isolation layer) advantageously provides electrical isolation between the two semiconductor fins. In various embodiments, the source/drain regions may be epitaxially grown and may optionally be doped. In various embodiments, the source/drain regions may comprise Si: P or SiGe: B.
In various embodiments, the gate structure may include a gate dielectric, a work function metal, and a gate contact. In various embodiments, the gate structure may define a channel region in the semiconductor active region that it overlaps. In various embodiments, the gate dielectric may be a high-k material (e.g., HfO 2). In various embodiments, the work function metal may be a work function adjusting metal. In various embodiments, the work function metal may be selected from TiN, TaN, TiSiN, TiAl, and TiC. In various embodiments, the gate contact may comprise W.
In an embodiment, the gate plug may comprise a nitride material (e.g., SiN) or an oxycarbide material (e.g., SiCo). In various embodiments, the gate plug may be provided using Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). In various embodiments, the thickness of the gate plug may be from 20 to 50nm, preferably from 30 to 40 nm. For example, it may be 35 nm.
In various embodiments, the spacers may comprise a low-k material (e.g., SiBCN or SiCO). In the final device, the spacers advantageously provide electrical isolation between the gate contact on the one hand and the source/drain contact on the other hand.
In various embodiments, the etch stop layer may comprise a nitride material (e.g., SiN). In various embodiments, the spacer may have sidewalls and the etch stop layer may further cover the sidewalls. In various embodiments, the etch stop layer may be provided by conformal deposition (e.g., ALD). The etch stop layer advantageously protects the source/drain region from damage (e.g., oxidation) during removal of the material covering it. Therefore, it is generally sufficient that the etch stop layer covers only the source/drain regions. However, the top surface of the liner etch stop layer may also be lined with the sidewalls of the spacers at the same time; this may be particularly true for SiN, where there is currently no readily available technology to provide a layer that covers the tops of the source/drain regions, but not also the sidewalls. In a preferred embodiment, the etch stop layer may be exposed to only a single selective removal step during the entire process. This advantageously allows the etch stop layer to be relatively thin. In various embodiments, the etch stop layer may have a thickness from 2 to 5nm, e.g., 3 nm.
In various embodiments, a top surface of the sacrificial material may be coplanar with a top surface of the gate plug. In various embodiments, the sacrificial material may be a dielectric material (e.g., SiO 2). In various embodiments, the sacrificial material may not be a carbon-containing dielectric material (e.g., carbon-containing SiO 2). In various embodiments, the other portions of the semiconductor structure may include further source/drain regions. In various embodiments, the further source/drain regions may be dummy source/drain regions. The dummy source/drain regions may be, for example, source/drain regions that will not function in the final semiconductor device and therefore also need not be contacted. In various embodiments, prior to step b, the dummy source/drain regions may be structurally similar (e.g., indistinguishable) to the source/drain regions (i.e., the source/drain regions to be contacted).
The masking structure masks portions of the semiconductor structure, including source and drain regions, on which source and drain contacts are to be formed, respectively.
In various embodiments, the masking structure may include a resist layer (e.g., a photoresist layer). Typically, when a photoresist layer is just deposited over the semiconductor structure and just patterned, the masking structure includes the photoresist layer, thereby masking the source region(s) and drain region(s) to be contacted, while leaving other portions of the semiconductor structure unmasked. In various embodiments, the masking structure may further include a hard mask layer (e.g., TiN or spin-on-glass) and/or a soft mask layer (e.g., spin-on-carbon) underlying the resist layer. Typically, a patterned photoresist layer is formed on a hard mask layer, which itself is formed on a soft mask layer. Once the pattern of photoresist is transferred to the hard mask layer and the soft mask layer, the mask structure includes the photoresist layer, the hard mask layer, and the soft mask layer. In a particular embodiment, the masking structure can include a dielectric liner (e.g., SiO2), a first hard mask layer (e.g., TiN) overlying the dielectric liner, a soft mask layer (e.g., spin-on carbon) overlying the first hard mask layer, a second hard mask layer (e.g., spin-on glass) overlying the soft mask layer, and a resist layer overlying the second hard mask layer. Typically, a soft mask layer is formed on a first hard mask layer, which itself is formed on a dielectric liner. Once the patterns of the photoresist, the second hard mask layer, and the soft mask layer are transferred to the first hard mask layer and the dielectric liner, the mask structure may include the dielectric liner, the first hard mask layer, the soft mask layer, the second hard mask layer, and the resist layer. Most typically, however, after patterning the first hard mask layer and the dielectric liner, the resist layer, the second hard mask layer, and the soft mask layer will no longer be present. Thus, in an embodiment, the mask structure comprises a patterned first hard mask layer on a patterned dielectric liner.
In various embodiments, the step b of selectively removing sacrificial material present on other portions of the semiconductor structure may be performed selectively with respect to the gate plugs and spacers. In various embodiments, step b may further comprise removing the etch stop layer. Because the selective removal in step b is limited to being performed on the other portions of the semiconductor structure (e.g., including dummy source/drain regions), the requirements for removal of the sacrificial material may advantageously be less stringent than in steps f and g. For example, some over-etching or under-etching of the dummy/source drain regions may be allowed. In various embodiments, the step b of selectively removing the sacrificial material present on the other portions of the semiconductor structure may comprise dry etching. In a preferred embodiment, the dry etch may be followed by a wet clean (e.g., wet etch). Nevertheless, selective removal of the sacrificial material by dry etching alone can be difficult to control and can produce undesirable levels of over-etching or under-etching, particularly when the critical dimension between the spacers is small. Therefore, it is advantageous to first remove most of the sacrificial material with a dry etch, and then remove any remaining sacrificial material and residues (e.g., resulting from the dry etch) with a wet clean.
In various embodiments, step c may comprise dry or wet etching; wet etching may be preferred. In various embodiments, the dry or wet etch may be based on an ammonium hydroxide-hydrogen peroxide-water mixture (APM). In various embodiments, step c may include removing the masking structure down to the dielectric liner. In other embodiments, step c may be performed in conjunction with step b.
In various embodiments, the dielectric layer (e.g., interlayer dielectric, ILD) deposited in step b may comprise a carbon-containing oxide. In a preferred embodiment, the carbon-containing oxide may be carbon-containing SiO 2. Carbon-containing dielectric materials are alternatively referred to as dense low-k materials. In various embodiments, the carbon-containing dielectric material may be deposited by spin coating or by chemical vapor deposition. In various embodiments, forming the carbon-containing dielectric material can include hydrogenating an alkoxysilane.
In various embodiments, step e may further comprise planarizing the dielectric layer. In various embodiments, the planarizing dielectric layer may include an overburden of the recessed dielectric layer. In a preferred embodiment, the capping layer may be recessed down to the gate plug. Recessing the capping layer down to the gate plug may play an advantageous role in controlling the etch selectivity in subsequent steps, such as steps f and/or g. In various embodiments, recessing the capping layer down to the gate plug may expose the sacrificial material. In various embodiments, planarizing the dielectric layer may include chemical mechanical polishing.
In various embodiments, step f may be performed selectively with respect to the gate plug, the spacer, the etch stop layer, and the dielectric layer. In various embodiments, step f may remove the sacrificial material down to the etch stop layer. In various embodiments, step f may comprise an HF-based wet etch.
In various embodiments, step g may be performed selectively with respect to the gate plug, the spacer, the dielectric layer, and the source and/or drain regions. In various embodiments, step g may remove the etch stop layer down to the source and/or drain regions. In various embodiments, step g may include a hot H3PO4 (e.g., 150 ℃ or higher, such as 160 ℃) or a hot HF (e.g., 80 to 90 ℃) based wet etch.
In various embodiments, steps f and/or g may include forming a gap over at least one source and/or drain region. In various embodiments, the gap formed in step b and/or step g may have a width (w) of from 10 to 20nm, preferably from 14 to 16 nm. In various embodiments, the ratio of the depth (d) of the gap to the width (w) dimension of the gap may be at least 10: 1, preferably at least 15: 1.
in various embodiments, the conductive material may be selected from W, Co and Ru. In various embodiments, step h may include providing a contact liner prior to depositing the conductive material. In various embodiments, the contact liner may comprise Ti or TiN. In various embodiments, step h may include filling the gap formed in step g. In various embodiments, the source contact and/or the drain contact may be a wrap-around contact. In various embodiments, the source/drain contact may be electrically coupled to the source/drain region. In various embodiments, the source/drain contacts may be in electrical contact with the source/drain regions, and are preferably direct mechanical contacts.
In various embodiments, the method may further comprise a step b' after step b and before step d, wherein:
b' lining at least the sides of the gap with a further etch stop layer.
In various embodiments, the further etch stop layer may comprise a nitride material. The etch resistance of the dielectric layer provided in step d is typically high in the top-down direction relative to the wet etch in step f and/or step g (e.g., the etch resistance of the top surface of the dielectric layer may be higher). However, the etch resistance of the dielectric layer in the lateral direction may be low. As such, the wet etch of step f and/or step g may cause some lateral overetch into the dielectric layer. This effect can advantageously be mitigated (e.g. prevented) by providing a further etch stop layer prior to step d (see example 2).
In a second aspect, the present invention relates to a semiconductor structure comprising:
i. a semiconductor active region including a channel region, a source region and a drain region, the source and drain regions having a top surface;
a gate structure on the channel region, the gate structure having a top surface and sidewalls;
a gate plug on a top surface of the gate structure, the gate plug having sidewalls;
spacers lining sidewalls of the gate structure and the gate plug;
v. an etch stop layer covering at least the top surfaces of the source and drain regions;
a sacrificial material on the etch stop layer over the source and drain regions;
a dielectric layer covering other portions of the semiconductor structure leaving the source and drain regions uncovered;
wherein the material of the gate plug, the material of the spacer, the sacrificial material, the material of the etch stop layer, the material of the dielectric layer, and the material of the source and drain regions are selected in such a way that:
during the wet etch process, the sacrificial material may etch faster than the material of the gate plug, the material of the spacer, the material of the etch stop layer and the material of the dielectric layer;
the etch stop layer may be completely removed without completely removing the gate plug, and
during the wet etch process, the material of the etch stop layer may etch faster than the material of the spacers, the material of the dielectric layer and the material of the source and drain regions.
In various embodiments, the case where the etch stop layer may be completely removed without completely removing the gate plug may be satisfied by making the thickness of the etch stop layer smaller than that of the gate plug, by making the material of the etch stop layer etch faster than that of the gate plug, or by a combination of both.
In various embodiments, any feature of the second aspect may be described independently as for any embodiment of the first aspect, respectively.
The invention will now be described by a detailed description of several embodiments of the invention. It is clear that other embodiments of the invention can be configured according to the knowledge of a person skilled in the art without departing from the true technical teaching of the invention, which is limited only by the terms of the appended claims.
Example 1: forming source/drain contacts in FinFET formation
We now refer to fig. 1. A semiconductor structure is provided comprising a substrate (100) carrying a semiconductor active region (200) and a gate structure (300). The semiconductor active region (200) includes a Si semiconductor fin (210) including a channel region (211) defined between epitaxially grown source/drain regions (221). The semiconductor fins (210) are isolated from each other by SiO2 shallow trench isolation layers (230; STI). The gate structure (300) includes a high k HfO2 gate dielectric (310), a TiN work function metal (320) and a W gate contact (330). The gate structure (300) is generally oriented perpendicular to the semiconductor fin (210). The gate structure (300) is capped by a 35nm SiN gate plug (410). The low-k SiCO spacers (420) line sidewalls of the gate structure (300) and the gate plug (410). A 3nm SiN etch stop layer (430) covers at least the top surface of the source/drain regions (221) and typically also lines the sidewalls of the spacers (420). The SiO2 sacrificial material (440) fills the gaps above the source/drain regions (221). The SiO2 dielectric liner (510) and TiN first hard mask layer (520) cover the entire structure.
We now refer to fig. 2. In this figure, the mask structure includes a patterned resist (550). A spin-on carbon planarization (e.g., soft mask) layer (530) and a spin-on glass second hard mask layer (540) are formed on the first hard mask layer (520). A patterned resist (550) is then provided on the second hard mask layer (540), thereby masking certain source/drain regions (221), while leaving other portions (560) of the semiconductor structure unmasked. As such, on the one hand, the patterned resist (550) defines those source/drain regions that will become contacted source/drain regions (221); these are source/drain regions masked by resist (550). On the other hand, the patterned resist (550) defines those source/drain regions that will act as dummy source/drain regions (216); these are source/drain regions in said other portion (560) of the semiconductor structure.
We now refer to fig. 3. The pattern is selectively etched down to the dummy source/drain regions (216), forming gaps (610) over the dummy source/drain regions (216). This is typically performed by a dry etch followed by a wet clean step; thereby removing the sacrificial material (440) and the etch stop layer (430) over the dummy source/drain regions (216). Because these dummy source/drain regions (216) will not be used as functional contact source/drain regions (221) in the final device, the etch requirements (e.g., limits on etch selectivity and over-etch) in this step may be somewhat less stringent (e.g., as compared to the etch in fig. 7 and 8 below).
We now refer to fig. 4. The remaining portions of the first hard mask layer (520) are removed by dry or wet etching based on an ammonium hydroxide-hydrogen peroxide-water mixture (APM).
We now refer to fig. 5. The gaps 610 above the source/drain regions 221 are overfilled with a carbon-containing SiO2 dielectric layer 450.
We now refer to fig. 6. The capping layer of the carbon-containing dielectric layer (450) is recessed back to the gate plug (410) by Chemical Mechanical Polishing (CMP). The sacrificial material (440) over the source/drain regions (221) to be contacted is thus exposed.
We now refer to fig. 7, which shows a front view (a) and a side view (b) of a semiconductor structure. The sacrificial material (440) over the source/drain regions (221) to be contacted is selectively removed by an HF-based wet etch at room temperature, stopping on the etch stop layer (430); thereby forming a gap (620) overlying the source/drain region (221) to be contacted.
We now refer to fig. 8, which shows a front view (a) and a side view (b) of a semiconductor structure. The etch stop layer (430) is selectively removed by a wet etch based on thermal (e.g., 160 ℃) H3PO4 or thermal (e.g., 80 to 90 ℃) HF; thereby exposing the source/drain regions (221) to be contacted.
We now refer to fig. 9, which shows a front view (a) and a side view (b) of a semiconductor structure. The source/drain contacts (700) are formed, for example, using a damascene process by lining the gaps (620) over the source/drain regions (221) to be contacted with a Ti contact liner (710) and filling the gaps (620) with a W conductive material (720; e.g., contact metal). The architecture shown in this example is such that the source/drain contacts (700) formed are Wrap Around Contacts (WAC).
Subsequently (not shown), a further metallization layer may be provided over the source/drain contacts 700.
Example 2: forming source/drain contacts in FinFET formation using additional etch stop liner
The procedure outlined in example 1 for fig. 1-4 was repeated.
We now refer to fig. 10, which shows a front view (a) and a side view (b) of a semiconductor structure. The entire structure is laminated with a thin SiCO etch stop layer (460) lining the sidewalls of the masked sacrificial material (440).
We now refer to fig. 11. The gaps 610 above the source/drain regions 221 are overfilled with a carbon-containing SiO2 dielectric layer 450.
We now refer to fig. 12. The capping layer of the carbon-containing dielectric layer (450) is recessed back to the gate plug (410) by Chemical Mechanical Polishing (CMP). The sacrificial material (440) over the source/drain regions (221) to be contacted is thus exposed.
We now refer to fig. 13, which shows a front view (a) and a side view (b) of a semiconductor structure. The sacrificial material (440) over the source/drain regions (221) to be contacted is selectively removed by an HF-based wet etch at room temperature, stopping on the etch stop layer (430); thereby forming a gap (620) overlying the source/drain region (221) to be contacted. During this selective removal, the etch stop layer (460) further protects the carbon-containing SiO2 dielectric layer (450).
Further procedures are outlined further in example 1 proceeding to fig. 8.
It is to be understood that although preferred embodiments, specific constructions and configurations, as well as materials, have been discussed herein for devices according to the present invention, various changes or modifications in form and detail may be made without departing from the scope and technical teaching of this invention. For example, any of the formulas given above are only representative of steps that may be used. Functions may be added or deleted from the block diagrams and operations may be interchanged among the functional blocks. Steps may be added to or deleted from the method within the scope of the invention.

Claims (20)

1. A method for forming source and drain contacts in a semiconductor structure, comprising:
a semiconductor structure is provided, comprising:
a semiconductor active region comprising a channel region, a source region and a drain region, wherein the source and drain regions each have a top surface;
a gate structure on the channel region, wherein the gate structure has a top surface and sidewalls;
a gate plug on the top surface of the gate structure, wherein the gate plug has sidewalls;
spacers lining the sidewalls of the gate structure and the gate plug;
an etch stop layer covering a top surface of the source region and a top surface of the drain region;
a sacrificial material on the etch stop layer and other portions of the semiconductor structure over the source and drain regions different from the source and drain regions; and
masking structures that mask the source and drain regions while leaving the other portions of the semiconductor structure unmasked;
forming a gap by selectively removing the sacrificial material present on the other portion of the semiconductor structure;
removing all or part of the mask structure;
filling the gap by depositing a dielectric layer on the semiconductor structure;
exposing the sacrificial material present on the etch stop layer over the source and drain regions;
selectively removing the sacrificial material present on the etch stop layer over the source and drain regions by a wet etch process;
selectively removing the etch stop layer covering the top surfaces of the source region and the drain region by a wet etching process to the extent that the top surfaces of the source region and the drain region are exposed;
forming the source contact and the drain contact in the semiconductor structure by depositing a conductive material on the source region and the drain region,
wherein the material of the gate plug, the material of the spacer, the sacrificial material, the material of the etch stop layer, the material of the dielectric layer, and the material of the source and drain regions are selected in such a way that:
during the selective removal of the sacrificial material present on the etch stop layer, the sacrificial material etches faster than the material of the gate plug, the material of the spacer, the material of the etch stop layer, and the material of the dielectric layer;
the etch stop layer can be completely removed without completely removing the gate plug, an
During selective removal of the etch stop layer covering the top surface of the source region and the top surface of the drain region, the material of the etch stop layer is etched faster than the material of the spacer, the material of the dielectric layer, and the material of the source and drain regions.
2. The method of claim 1, wherein the sacrificial material comprises a dielectric material.
3. The method of claim 1, wherein forming gaps by selectively removing the sacrificial material present on the other portions of the semiconductor structure is performed selectively with respect to the gate plugs and the spacers.
4. The method of claim 1, wherein forming a gap by selectively removing the sacrificial material present on the other portion of the semiconductor structure comprises dry etching.
5. The method of claim 1, wherein the gate plug comprises a nitride material or an oxycarbide material.
6. The method of claim 1, in which the spacers comprise a low-k material.
7. The method of claim 1, wherein the etch stop layer comprises a nitride material.
8. The method of claim 1, wherein the dielectric layer deposited on the semiconductor structure comprises a carbon-containing oxide.
9. The method of claim 1, wherein the source contact or the drain contact is a wrap-around contact.
10. The method of claim 1, further comprising lining at least sides of the gap with a further etch stop layer.
11. The method of claim 10, wherein the further etch stop layer comprises a nitride material.
12. The method of claim 1, wherein removing all or part of the mask structure is performed in conjunction with selectively removing the sacrificial material present on the other portions of the semiconductor structure.
13. The method of claim 1, in which exposing the sacrificial material present on the etch stop layer over the source region and the drain region comprises planarizing the dielectric layer.
14. The method of claim 1, in which the semiconductor active region comprises a semiconductor fin.
15. A semiconductor structure, comprising:
a semiconductor active region comprising a channel region, a source region and a drain region, the source region and the drain region each having a top surface;
a gate structure on the channel region, wherein the gate structure has a top surface and sidewalls;
a gate plug on the top surface of the gate structure, wherein the gate plug has sidewalls;
spacers lining the sidewalls of the gate structure and the sidewalls of the gate plug;
an etch stop layer covering the top surface of the source region and the top surface of the drain region;
a sacrificial material on the etch stop layer over the source region and the drain region;
a dielectric layer covering other portions of the semiconductor structure leaving the source and drain regions uncovered,
wherein the material of the gate plug, the material of the spacer, the sacrificial material, the material of the etch stop layer, the material of the dielectric layer, and the material of the source and drain regions are selected in such a way that:
during a wet etch process, the sacrificial material is etchable faster than the material of the gate plug, the material of the spacer, the material of the etch stop layer, and the material of the dielectric layer;
the etch stop layer can be completely removed without completely removing the gate plug, an
The material of the etch stop layer may be etched faster than the material of the spacer, the material of the dielectric layer, and the material of the source and drain regions during a wet etch process.
16. The semiconductor structure of claim 15, in which the sacrificial material comprises a dielectric material.
17. The semiconductor structure of claim 15, wherein the gate plug comprises a nitride material or an oxycarbide material.
18. The semiconductor structure of claim 15, wherein the etch stop layer comprises a nitride material.
19. The semiconductor structure of claim 15, in which the dielectric layer comprises a carbon-containing oxide.
20. The semiconductor structure of claim 15, in which the spacer comprises a low-k material.
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