CN109753831A - A kind of management method, device, equipment and the storage medium of PUF circuit - Google Patents
A kind of management method, device, equipment and the storage medium of PUF circuit Download PDFInfo
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Abstract
The invention discloses management method device, equipment and the computer readable storage mediums of a kind of PUF circuit, applied to on-site programmable gate array FPGA, including being instructed in response to the enabling to physics unclonable function PUF circuit, preset PUF circuit process is controlled to execute in the reconfigurable PR module in part of itself, to realize the function of PUF circuit under the cooperation of PR module and PUF circuit process；It in response to the halt instruction to PUF circuit, controls PUF circuit process and stops and discharged out of PR module, enable instruction according to others so as to subsequent, control other default processes and executed in PR module.This fractional hardware resource that PR module in the present invention occupies, other functions can also be realized when not realizing PUF circuit, are improved resource utilization, cost has been saved.
Description
Technical field
The present invention relates to the fields FPGA, and more particularly to a kind of management method of PUF circuit, the invention further relates to one kind
Managing device, equipment and the storage medium of PUF circuit.
Background technique
PUF is usually provided with inside FPGA (Field-Programmable Gate Array, field programmable gate array)
(Physical Unclonable Function, physics unclonable function) circuit, PUF circuit can be used to implement chip id
Generation, encryption and decryption and the IP (intellectual property, intellectual property) of (Identification, identity number)
The functions such as the protection of core, PUF circuit can only be used to achieve specific function within the sub-fraction time, but existing
In technology, PUF circuit is realized inside FPGA with cured hardware circuit, for example including with door and phase inverter etc., is accounted for always
According to a part of hardware resource of FPGA, this was indicated that in the most of the time without using PUF circuit, occupied by PUF circuit
Hardware resource it is idle waste, hardware resource utilization is lower, increases cost.
Therefore, how to provide a kind of scheme of solution above-mentioned technical problem is that those skilled in the art need to solve at present
Problem.
Summary of the invention
The object of the present invention is to provide a kind of management methods of PUF circuit, improve the utilization rate of hardware resource in FPGA,
Cost is reduced；It is a further object of the present invention to provide managing device, equipment and the storage mediums of a kind of PUF circuit, improve
The utilization rate of hardware resource, has reduced cost in FPGA.
In order to solve the above technical problems, being applied to field-programmable the present invention provides a kind of management method of PUF circuit
Gate array FPGA, comprising:
In response to the enabling instruction to physics unclonable function PUF circuit, preset PUF circuit process is controlled at itself
The reconfigurable PR module in part in execute, to realize PUF under the cooperation of the PR module and the PUF circuit process
The function of circuit；
In response to the halt instruction to the PUF circuit, controls the PUF circuit process and stop and out of described PR module
Release enables instruction according to others so as to subsequent, controls other default processes and executes in the PR module.
Preferably, the PR module is multiple；
Then the preset PUF circuit process of control executes in the reconfigurable PR module in part of itself specifically:
Preset PUF circuit process is controlled to hold in described enable in the specified reconfigurable PR module in the part of itself of instruction
Row.
Preferably, each occupied hardware resource of PR module is not less than in all default processes, hardware resource
The maximum default occupied hardware resource of process of occupancy.
Preferably, the interface of the preset PUF circuit process and the PR module matches, so as in the PR module
Interior execution.
Preferably, the hardware resource that the output bit of the PUF circuit of realization occupies for the PR module can be full
The maximum output position of foot.
Preferably, the PUF circuit submodule is ring oscillator physics unclonable function RO-PUF circuit submodule.
In order to solve the above technical problems, being applied to FPGA, packet the present invention also provides a kind of managing device of PUF circuit
It includes；
Control module controls preset PUF for instructing in response to the enabling to physics unclonable function PUF circuit
Circuit process executes in the reconfigurable PR module in part of itself, so as in the PR module and the PUF circuit process
Under cooperation, the function of PUF circuit is realized；
Release module, for controlling the PUF circuit process and stopping simultaneously in response to the halt instruction to the PUF circuit
It is discharged out of described PR module, enables instruction according to others so as to subsequent, control other default processes in the PR module
Interior execution.
Preferably, the PR module is multiple；
Then the preset PUF circuit process of control executes in the reconfigurable PR module in part of itself specifically:
Preset PUF circuit process is controlled to hold in described enable in the specified reconfigurable PR module in the part of itself of instruction
Row.
In order to solve the above technical problems, being applied to FPGA, packet the present invention also provides a kind of management equipment of PUF circuit
It includes:
Memory, for storing computer program；
Processor realizes the management method of the PUF circuit any one of as above when for executing the computer program
Step.
In order to solve the above technical problems, being applied to FPGA, institute the present invention also provides a kind of computer readable storage medium
It states and is stored with computer program on computer readable storage medium, realize when the computer program is executed by processor and such as take up an official post
The step of management method of one PUF circuit.
The present invention provides a kind of management methods of PUF circuit, are applied to on-site programmable gate array FPGA, including response
In the enabling instruction to physics unclonable function PUF circuit, controlling preset PUF circuit process can be reconfigured in the part of itself
It sets in PR module and executes, to realize the function of PUF circuit under the cooperation of PR module and PUF circuit process；In response to right
The halt instruction of PUF circuit, control PUF circuit process stop and discharge out of PR module, are enabled so as to subsequent according to others
Instruction controls other default processes and executes in PR module.
As it can be seen that in the present invention, instructed in response to the enabling to PUF circuit, control preset PUF circuit process itself
It is executed in the reconfigurable PR module in part, to realize the function of PUF circuit, in response to the halt instruction to PUF circuit, control
PUF circuit process stops and discharges out of PR module, enables instruction according to others so as to subsequent, controls other default processes
It is executed in PR module, the PUF circuit in the present invention is realized by PR module and preset PUF circuit process, is finished in use
When PUF circuit, it can control other default processes and executed in PR module to realize other default corresponding functions of process,
This fractional hardware resource that PR module occupies, other functions can also be realized when not realizing PUF circuit, improve resource benefit
With rate, cost has been saved.
The present invention also provides managing device, equipment and the computer readable storage mediums of a kind of PUF circuit, have as above
The identical beneficial effect of management method.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of flow diagram of the management method of PUF circuit provided by the invention；
Fig. 2 is a kind of structural schematic diagram of the managing device of PUF circuit provided by the invention；
Fig. 3 is a kind of structural schematic diagram of the management equipment of PUF circuit provided by the invention.
Specific embodiment
Core of the invention is to provide a kind of management method of PUF circuit, improves the utilization rate of hardware resource in FPGA,
Cost is reduced；Another core of the invention is to provide managing device, equipment and the storage medium of a kind of PUF circuit, improves
The utilization rate of hardware resource, has reduced cost in FPGA.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Referring to FIG. 1, Fig. 1 is a kind of flow diagram of the management method of PUF circuit provided by the invention, comprising:
Step S1: in response to physics unclonable function PUF circuit enabling instruct, control preset PUF circuit into
Journey executes in itself PR (Partial Reconfiguration, part are reconfigurable) module, so as to PR module with
Under the cooperation of PUF circuit process, the function of PUF circuit is realized；
Can be by accomplished in many ways specifically, enabling instruction, such as can be the pre-set programs inside FPGA pre-
If the enabling instruction generated when the moment, or the enabling instruction etc. that staff is sent by processor from outside, this hair
Bright embodiment is it is not limited here.
Specifically, PUF circuit process can be constructed in advance, it is then stored in predeterminated position, in use, inside FPGA
Static zones, which can control, to be stored in the PUF circuit process of predeterminated position and executes in PR module, the two in cooperating just
The function of PUF circuit may be implemented.
Wherein, inside FPGA, the part other than PR module is known as static zones, and control function may be implemented.
Step S2: in response to the halt instruction to PUF circuit, controlling PUF circuit process and stop and discharge out of PR module,
Instruction is enabled according to others so as to subsequent, other default processes is controlled and is executed in PR module.
Specifically, identical with enabling instruction be, halt instruction can also there are many kinds of implementations, such as can be
The halt instruction that pre-set programs inside FPGA are generated in predetermined time, or staff passes through processor from outside
The halt instruction etc. of transmission, the embodiment of the present invention is it is not limited here.
It is a kind of technology for reconfiguring FPGA portion region that part, which reconfigures, can use it and dynamically reconfigures
FPGA inner part reconfigures the logic unit in region, the normal function without influencing other regions.Part reconfigures region can be with
Receive the configuration file of multiple and different functions, so that the function of run business switching at runtime FPGA Nei is realized, for time division multiplexing
FPGA internal hardware resources realize the complication system of different function, and this technology is highly effective.Such as it can be by fpga chip
Two regions interior A, B are set as part and reconfigure region, remaining is static region, wherein can be pre-designed three for a-quadrant
Default process, in such cases, a-quadrant can be in the case where not influencing the work of other modules by matching with three default processes
It closes, is reconfigured for the first presetting module, the second presetting module and third presetting module, and realize different functions respectively.
Wherein, after use finishes PUF circuit, it can control the stopping of PUF circuit process, and discharge out of PR module, this
It is just executed in PR module without any process in the case of kind, instruction can be enabled according to others subsequent, control is other
Default process executes in PR module, and to realize that others preset the corresponding functions of process, the default processes of others can be
It is a variety of, naturally it is also possible to control PUF circuit process again and be executed in PR module etc., the embodiment of the present invention is it is not limited here.
Wherein, after PUF circuit works, the output result of available PUF circuit is simultaneously cached, to carry out
It uses.
Wherein, the theory of time-sharing multiplex is utilized in the embodiment of the present invention, for hardware resource occupied by PR module into
Row time-sharing multiplex matches from different default processes respectively in the different periods, realizes different functions, improve hardware
The utilization rate of resource, certainly, all default processes all do not need to work always in FPGA, only in this way, could not influence
The original work of FPGA.
The present invention provides a kind of management methods of PUF circuit, are applied to on-site programmable gate array FPGA, including response
In the enabling instruction to physics unclonable function PUF circuit, controlling preset PUF circuit process can be reconfigured in the part of itself
It sets in PR module and executes, to realize the function of PUF circuit under the cooperation of PR module and PUF circuit process；In response to right
The halt instruction of PUF circuit, control PUF circuit process stop and discharge out of PR module, are enabled so as to subsequent according to others
Instruction controls other default processes and executes in PR module.
As it can be seen that in the present invention, instructed in response to the enabling to PUF circuit, control preset PUF circuit process itself
It is executed in the reconfigurable PR module in part, to realize the function of PUF circuit, in response to the halt instruction to PUF circuit, control
PUF circuit process stops and discharges out of PR module, enables instruction according to others so as to subsequent, controls other default processes
It is executed in PR module, the PUF circuit in the present invention is realized by PR module and preset PUF circuit process, is finished in use
When PUF circuit, it can control other default processes and executed in PR module to realize other default corresponding functions of process,
This fractional hardware resource that PR module occupies, other functions can also be realized when not realizing PUF circuit, improve resource benefit
With rate, cost has been saved.
On the basis of the above embodiments:
Embodiment as one preferred, PR module are multiple；
Preset PUF circuit process is then controlled to execute in the reconfigurable PR module in part of itself specifically:
Preset PUF circuit process is controlled to execute in the specified reconfigurable PR module in the part of itself of enabling instruction.
Specifically, PR module can just can be achieved at the same time multiple PUF circuits in such cases to be multiple, such as can be with
PUF circuit process is controlled simultaneously to execute in 3 PR modules, to utilize function achieved by 3 PUF circuits etc. simultaneously,
The embodiment of the present invention is it is not limited here.
Wherein, specifically control PUF circuit process is executed in which PR module and can be specified by enabling instruction, can be controlled
It makes the same PUF circuit process while being executed in multiple PR modules, also can be controlled separately different types of PUF circuit process
It is executed in multiple PR modules, the embodiment of the present invention is it is not limited here.
Specifically, the quantity of PR module can independently can be set to be a variety of according to actual needs, the present invention is implemented
Example is it is not limited here.
Embodiment as one preferred, each occupied hardware resource of PR module are not less than all default processes
In, the maximum default occupied hardware resource of process of hardware resource occupancy.
Specifically, when default process executes in PR module, it is also desirable to occupy hardware resource, such as PUF circuit process exists
When executing in PR module, hardware resource shared by the two PUF achieved under cooperation is the hard of PUF circuit process occupancy
Part resource, in such cases, each occupied hardware resource of PR module cannot be less than hardware resource in all default processes
The maximum occupied hardware resource of default process is occupied, just can guarantee that all default processes can be in each PR in such cases
It executes in module to realize specific function.
Wherein, all default processes also refer to all default processes of storage, can also refer to that each PR module is corresponding
The default process needed to be implemented, the embodiment of the present invention is it is not limited here.
The interface of embodiment as one preferred, preset PUF circuit process and PR module matches, so as in PR mould
It is executed in block.
Specifically, preset PUF circuit process can match with the interface of PR module, this condition can be set in advance
Realization when setting PUF circuit process could successfully control PUF circuit process and execute in PR inside modules in such cases.
Certainly, each default process is wanted to run in some PR module, is required to when being pre-designed the default process,
Design and the matched default process of the PR module interface, so as to subsequent control, the default process is held in the corresponding PR module
Row, and realize correlation function.
Embodiment as one preferred, the hardware resource institute energy that the output bit of the PUF circuit of realization occupies for PR module
The maximum output position of satisfaction.
Specifically, PUF circuit is usually to utilize the electricity of transistor caused by uncontrollable process deviation in chip manufacturing proces
A kind of circuit learning property difference and designing, RO PUF (Ring-Oscillator Physical Unclonable
Functions) circuit is one kind of silicon PUF circuit, and basic unit is the odd number phase inverter of identical quantity and as switch
The oscillation rings of effect constituted with door, the frequency difference constrained between the oscillation rings of chip different location by comparing obtain one
The output of bit；By comparing the difference on the frequency of multiple groups oscillation rings, multidigit output is obtained as random sequence, can be applied to core
Generation, encryption and decryption and protection of IP kernel of piece ID etc..If desired the more PUF output of digit is generated, then is needed a large amount of
With structure oscillation ring, it is compared to each other frequency of oscillation and obtains the output of more bits.When realizing this circuit in FPGA, each reverse phase
Device needs to occupy a LUT (Look Up Table shows look-up table) resource, each needs to occupy a LUT resource with door,
Single oscillation rings just need 4 LUT resources, it is seen that when realizing this PUF circuit of multi output on FPGA, need to occupy very much
Hardware resource.
Wherein, existing PUF circuit is all arranged on inside FPGA with cured example, in hardware, such as RO PUF circuit passes through
The working frequency of the two neighboring oscillation rings constrained in comparable chip, obtains difference on the frequency, positive and negative according to difference on the frequency obtains a ratio
The output of special position.When needing to obtain the output of more bits, it is necessary to increase the number of oscillation rings, i.e. LUT in increase FPGA
The occupancy of hardware resource.Since resource is extremely limited in FPGA, hardware resource is also act as other main business applications, can not
The a large amount of valuable hardware resources of PUF circuit can be kept for.Under normal conditions, PUF circuit is not to be constantly in working condition, only
It is just called in system electrification early period or whenever necessary.
Specifically, due to realizing PUF circuit by PR module and the cooperation of default PUF circuit process in the embodiment of the present invention,
And other functions can also be realized by PR module and other default process cooperations in not applicable PUF circuit, therefore can
With the more of the output bit setting of the PUF circuit appropriate by realization, but will the institute of the hardware resource shared by PR module energy
Under the premise of satisfaction.
Wherein, the PUF circuit process in the embodiment of the present invention can execute in the existing PR module of FPGA, in this case
It may be restricted to the hardware resource occupancy of existing PR module itself, if the hardware resource occupancy of existing PR module is larger,
So can be by designing PUF circuit, and the PUF circuit it cooperated with PR module to show more output bit, in addition, this
PUF circuit process in inventive embodiments can also execute in the PR module rebuild, just need to design in such cases
PUF circuit process and other some default processes, and according to these all default processes, building one can satisfy each
The PR module of a default process, and be mounted on inside FPGA, the embodiment of the present invention is it is not limited here.
Embodiment as one preferred, PUF circuit process are ring oscillator physics unclonable function RO-PUF electricity
Road process.
Specifically, RO PUF circuit is that common one kind, the PUF circuit that will be realized are set as RO in PUF circuit
Multiple functions may be implemented in PUF circuit.
Wherein, constructing PUF circuit process and rebuilding the process of the PR module that PUF circuit process is applicable in be
Multiple types, such as the process of building RO PUF circuit process and its applicable PR module can be with are as follows:
1) each phase inverter and being tied in a LUT respectively with door in the oscillation rings for forming RO PUF circuit is realized
Phase inverter and function with door；
2) design and the matched RO PUF circuit process of PR module interface, including multiple oscillation rings, counter and comparator
Circuit；
3) designing remaining will be with all service application mould of RO PUF circuit process common hardware resource (i.e. PR module)
Block (default process), wherein can the system in advance to FPGA complexity decompose, distinguish which module needs to occupy always
Hardware resource work, the module design which module only just works in some period, and only will just work in certain periods
To preset process.
4) creation part reconfigures region, according to the needs of PUF output bit and default process itself institute of each service application
Hardware resource situation is accounted for, part is divided according to the maximum default occupied hardware resource of process of resource occupation and reconfigures region.
Referring to FIG. 2, a kind of Fig. 2 structural schematic diagram of the managing device of PUF circuit provided by the invention, is applied to
FPGA, including；
Control module 1 controls preset PUF for instructing in response to the enabling to physics unclonable function PUF circuit
Circuit process executes in the reconfigurable PR module in part of itself, real so as under the cooperation of PR module and PUF circuit process
The function of existing PUF circuit；
Release module 2 stops and in response to the halt instruction to PUF circuit, controlling PUF circuit process from PR module
Interior release enables instruction according to others so as to subsequent, controls other default processes and executes in PR module.
Embodiment as one preferred, PR module are multiple；
Preset PUF circuit process is then controlled to execute in the reconfigurable PR module in part of itself specifically:
Preset PUF circuit process is controlled to execute in the specified reconfigurable PR module in the part of itself of enabling instruction.
The embodiment of aforementioned management method is please referred to for the introduction of the managing device of PUF circuit provided by the invention, this
Details are not described herein for inventive embodiments.
Referring to FIG. 3, a kind of Fig. 3 structural schematic diagram of the management equipment of PUF circuit provided by the invention, is applied to
FPGA, comprising:
Memory 3, for storing computer program；
Processor 4, when for executing computer program the step of the management method of realization any one PUF circuit as above.
The embodiment of aforementioned management method is please referred to for the introduction of the management equipment of PUF circuit provided by the invention, this
Details are not described herein for inventive embodiments.
In order to solve the above technical problems, being applied to FPGA, meter the present invention also provides a kind of computer readable storage medium
It is stored with computer program on calculation machine readable storage medium storing program for executing, as above any one PUF is realized when computer program is executed by processor 4
The step of management method of circuit.
The embodiment of aforementioned management method is please referred to for the introduction of computer readable storage medium provided by the invention, this
Details are not described herein for inventive embodiments.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is said referring to method part
It is bright.
It should also be noted that, in the present specification, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of management method of PUF circuit is applied to on-site programmable gate array FPGA characterized by comprising
In response to the enabling instruction to physics unclonable function PUF circuit, preset PUF circuit process is controlled in itself portion
Divide in reconfigurable PR module and execute, to realize PUF circuit under the cooperation of the PR module and the PUF circuit process
Function；
In response to the halt instruction to the PUF circuit, controls the PUF circuit process and stop and released out of described PR module
It puts, enables instruction according to others so as to subsequent, control other default processes and executed in the PR module.
2. management method according to claim 1, which is characterized in that the PR module is multiple；
Then the preset PUF circuit process of control executes in the reconfigurable PR module in part of itself specifically:
Preset PUF circuit process is controlled to execute in described enable in the specified reconfigurable PR module in the part of itself of instruction.
3. management method according to claim 2, which is characterized in that each occupied hardware resource of PR module is equal
Not less than in all default processes, the maximum default occupied hardware resource of process of hardware resource occupancy.
4. management method according to claim 1, which is characterized in that the preset PUF circuit process and the PR mould
The interface of block matches, to execute in the PR module.
5. management method according to claim 1, which is characterized in that the output bit of the PUF circuit of realization is described
The maximum output position that the hardware resource that PR module occupies is met by.
6. management method according to any one of claims 1 to 5, which is characterized in that the PUF circuit process is annular vibration
Swing implements reason unclonable function RO-PUF circuit process.
7. a kind of managing device of PUF circuit is applied to FPGA, which is characterized in that including；
Control module controls preset PUF circuit for instructing in response to the enabling to physics unclonable function PUF circuit
Process executes in the reconfigurable PR module in part of itself, so as in the cooperation of the PR module and the PUF circuit process
Under, realize the function of PUF circuit；
Release module stops and in response to the halt instruction to the PUF circuit, controlling the PUF circuit process from institute
Release in PR module is stated, enables instruction according to others so as to subsequent, other default processes is controlled and is held in the PR module
Row.
8. managing device according to claim 7, which is characterized in that the PR module is multiple；
Then the preset PUF circuit process of control executes in the reconfigurable PR module in part of itself specifically:
Preset PUF circuit process is controlled to execute in described enable in the specified reconfigurable PR module in the part of itself of instruction.
9. a kind of management equipment of PUF circuit is applied to FPGA characterized by comprising
Memory, for storing computer program；
Processor realizes the management of the PUF circuit as described in any one of claim 1 to 6 when for executing the computer program
The step of method.
10. a kind of computer readable storage medium is applied to FPGA, which is characterized in that on the computer readable storage medium
It is stored with computer program, the PUF as described in any one of claim 1 to 6 is realized when the computer program is executed by processor
The step of management method of circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910016354.8A CN109753831A (en) | 2019-01-08 | 2019-01-08 | A kind of management method, device, equipment and the storage medium of PUF circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910016354.8A CN109753831A (en) | 2019-01-08 | 2019-01-08 | A kind of management method, device, equipment and the storage medium of PUF circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111339579A (en) * | 2020-03-26 | 2020-06-26 | 清华大学 | Electronic device and operation method thereof |
| CN111966329A (en) * | 2020-08-18 | 2020-11-20 | 合肥工业大学 | Physical unclonable function PUF-based true random number generator |
-
2019
- 2019-01-08 CN CN201910016354.8A patent/CN109753831A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111339579A (en) * | 2020-03-26 | 2020-06-26 | 清华大学 | Electronic device and operation method thereof |
| CN111339579B (en) * | 2020-03-26 | 2022-07-08 | 清华大学 | Electronic device and operation method thereof |
| CN111966329A (en) * | 2020-08-18 | 2020-11-20 | 合肥工业大学 | Physical unclonable function PUF-based true random number generator |
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