CN109753450A - Prevent the method and device of memory injection attacks - Google Patents
Prevent the method and device of memory injection attacks Download PDFInfo
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- CN109753450A CN109753450A CN201711082645.4A CN201711082645A CN109753450A CN 109753450 A CN109753450 A CN 109753450A CN 201711082645 A CN201711082645 A CN 201711082645A CN 109753450 A CN109753450 A CN 109753450A
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Abstract
The invention proposes a kind of methods for preventing memory injection attacks, are applied to microprocessor, comprising: whether the target memory address for the downlink data that memory will be written in judgement belongs to shielded region of memory；If the target memory address of the downlink data belongs to shielded region of memory, forbid the downlink data that its target memory address is written.The embodiment of the present invention is audited by the downlink data for directly returning memory to CPU write, is prevented crucial region of memory in computing system from being tampered, is guaranteed the safety and reliability of computing system.
Description
Technical field
The invention belongs to computer safety field more particularly to a kind of method and devices for preventing memory injection attacks.
Background technique
With widely available and Internet technology the high speed development of computer and intelligent terminal in recent years, equipment peace
Full problem is also even more increasingly prominent.And key core of the processor as calculating equipment, the safety problem of processor will be serious
Influence the entire safety for calculating equipment.
Currently, the safe practice for processor mainly has hardware virtualization technology and TrustZone technology.Such as
The CPU such as Intel, AMD manufacturer, the safety of CPU is realized using hardware virtualization technology；Hardware virtualization technology is that one kind is based on
Instruction scheduling rights management and control security mechanism, as virtual machine monitor (VMM, Virtual Machine Monitor,
Also referred to as Hypervisor), the franchise layer being created that when using hardware virtualization technology is referred exclusively to, which is supplied to virtual machine
Developer, for realizing the communication and event handling of virtual hardware and real hardware, the Permission Levels of VMM are greater than operating system
Permission.As shown in Figure 1, the permission of VMM can be considered at ring-1 grades in Intel virtualization technology framework.ARM frame
The TrustZone technology of structure CPU introduces safe condition mark and judgment mechanism for user mode and privileged mode, to determine
System is operated under non-security " common " performing environment, is still operated under secure and trusted " safety " environment.Safety
Monitor (Monitor) controls the conversion between safety and " common " environment, and Fig. 2 is parallel for two under TrustZone mode
The schematic diagram of security context.
But the TrustZone technology of either Intel hardware virtualization technology or ARM, is substantially all based on measurement
Verifying and secure execution environments building, can not accomplish the instruction execution when CPU is run on direct intervention core cpu assembly line
Real-time control lacks the CPU architecture that security mechanism directly participates in core pipeline.
Summary of the invention
In view of this, it is an object of the invention to propose a kind of method for preventing memory injection attacks, it is existing to solve
The problem of lacking security mechanism inside safe processor.
In some illustrative embodiments, the method for preventing memory injection attacks is applied to microprocessor, comprising:
Judge whether the target memory address for the downlink data that memory will be written belongs to shielded region of memory；If the downlink data
Target memory address belong to shielded region of memory, then forbid the downlink data that its target memory address is written.
In some preferred embodiments, the judgement will be written the downlink data of memory target memory address whether
Belong to shielded region of memory, specifically include: will be in the target memory address of the downlink data and preconfigured check list
Shielded memory address is compared；Consistent memory address is arrived if comparing, with determining the target memory of the downlink data
Location belongs to shielded region of memory.
In some preferred embodiments, the check list is stored in the Buffer of piece internal buffer.
It is described to forbid the downlink data that its target memory address is written in some preferred embodiments, it specifically includes: repairing
Memory is written according to modified target memory address in the downlink data by the target memory address for changing the downlink data；Its
In, the modified destination address is not in the shielded region of memory.
It is another object of the present invention to propose a kind of microprocessor, to solve problems of the prior art.
In some illustrative embodiments, the microprocessor, comprising: memory will be written for judging in judgment module
The target memory address of downlink data whether belong to shielded region of memory；Control module, if for the downlink data
Target memory address belongs to shielded region of memory, then forbids the downlink data that its target memory address is written.
In some preferred embodiments, the judgment module be specifically used for by the target memory address of the downlink data with
Shielded memory address is compared in preconfigured check list；Consistent memory address is arrived if comparing, is determined under this
The target memory address of row data belongs to shielded region of memory.
In some preferred embodiments, the check list is stored in the Buffer of piece internal buffer.
In some preferred embodiments, in the control module, comprising: modified module, for modifying the lower line number
According to target memory address；Writing module, for memory to be written according to modified target memory address in the downlink data: its
In, the modified destination address is not in the shielded region of memory.
It is another object of the present invention to propose a kind of calculating equipment, which is equipped with any of the above-described kind of micro- place
Manage device.
Compared with prior art, the invention has the following advantages that
1. the embodiment of the present invention is audited by the downlink data for directly returning memory to CPU write, prevent in computing system
Crucial region of memory is tampered, and guarantees the safety and reliability of computing system.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the schematic diagram of hardware virtualization technology in the prior art；
Fig. 2 is the schematic diagram of trustzone technology in the prior art；
Fig. 3 is the structural schematic diagram of microprocessor in the embodiment of the present invention；
Fig. 4 is the structural schematic diagram of memory protection component in the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of memory protection component in the embodiment of the present invention；
Fig. 6 is the structural schematic diagram of memory protection component in the embodiment of the present invention；
Fig. 7 is the structural schematic diagram of microprocessor in the embodiment of the present invention；
Fig. 8 is the structural schematic diagram that memory protection component is write in the embodiment of the present invention；
Fig. 9 is the structural schematic diagram of microprocessor in the embodiment of the present invention；
Figure 10 is the structural schematic diagram of microprocessor in the embodiment of the present invention；
Figure 11 is method for protecting EMS memory flow chart in the embodiment of the present invention；
Figure 12 is the structural block diagram of microprocessor in the embodiment of the present invention；
Figure 13 is the method flow diagram that memory injection attacks are prevented in the embodiment of the present invention；
Figure 14 is the structural block diagram of microprocessor in the embodiment of the present invention.
Specific embodiment
The following description and drawings fully show specific embodiments of the present invention, to enable those skilled in the art to
Practice them.Other embodiments may include structure, logic, it is electrical, process and other change.Embodiment
Only represent possible variation.Unless explicitly requested, otherwise individual components and functionality is that optionally, and the sequence operated can be with
Variation.The part of some embodiments and feature can be included in or replace part and the feature of other embodiments.This hair
The range of bright embodiment includes equivalent obtained by the entire scope of claims and all of claims
Object.Herein, these embodiments of the invention can individually or generally be indicated that this is only with term " invention "
For convenience, and if in fact disclosing the invention more than one, the range for being not meant to automatically limit the application is to appoint
What single invention or inventive concept.
In the following detailed description, a large amount of specific details can be proposed, in order to provide a thorough understanding of the present invention.But
It is, it will be understood by those within the art that implementable present invention without these specific details.In other cases, do not have
Well-known method, process, component and circuit are had a detailed description, in order to avoid influence the understanding of the present invention.
In order to understand main thought of the invention faster, term employed in the present invention is explained now
Illustrate: " upstream data ", for upstream data, the present invention, which uniformly refers to control by processor core from memory, to be extracted, will
The data of Cache are written；" downlink data ", for downlink data, the present invention uniformly refers to directly will be to from processor core
The data (the case where UnCache) write in memory either control the data write from Cache into memory by processor core.
Microprocessor (also known as central processor CPU) is described from the angle of microelectronic circuit, and microprocessor is one piece of super large
The integrated circuit of scale is the arithmetic core and control core for calculating equipment, mainly by arithmetic unit (ALU, Arithmetic and
Logic Unit) and the big component of controller (CU, control Unit) two composition, in addition to this, also configure several registers, height
Fast buffer storage Cache (L1 containing Cache, Cache L2, shared Cache) and realization data and state interact total
Line, the function of microprocessor are mainly the data of interpretive machine instruction and processing computer software.
The structural block diagram with the microprocessor of security mechanism in core in the present invention is shown referring now to Fig. 3, Fig. 3, such as
Shown in the structural block diagram, a kind of microprocessor is disclosed, which is built-in with processor core (CPU Core) 11, high speed
Caching Cache12, Memory Controller Hub 13 and the rdma read for auditing the upstream data for extracting Cache from memory are protected
Component 14；Rdma read protection component 14 is arranged on the read channel between Cache12 and Memory Controller Hub 13.
Modern Memory Controller Hub 13 is built on the substrate of microprocessor CPU, and core cpu 11 is extracted from memory
Data just have to pass through Memory Controller Hub 13 into Cache12, therefore the read channel between Cache12 and Memory Controller Hub 13
Upper setting rdma read protects component 14, can analyze all upstream datas that Cache12 is extracted from memory；Another point,
Read channel between Cache12 and Memory Controller Hub 13 be it is two-way, first a is from processor core 11 to Memory Controller Hub
13 send request of data, and Article 2 b is to be extracted to write toward Cache12 from memory from Memory Controller Hub 13；Preferably, of the invention
Rdma read protection component 14 is configured on the b of Article 2 channel.
The present invention configures memory protection component in the core of microprocessor, by the process for extracting Cache from memory
Audit of the middle realization to upstream data, solves the problems, such as to lack security mechanism inside existing safe processor.
As shown in figure 4, the rdma read protection component 14 in the embodiment of the present invention is single by read channel control unit 141, audit
Member 142 forms；Wherein,
The read channel control unit 141, read channel of the configuration between the Cache12 and Memory Controller Hub 13 is (such as
The Article 2 of above-mentioned read channel) on, and connect with the audit unit 142, for intercepting upstream data on the read channel,
The audit unit 142 is sent to be audited；And the upper line number for carrying auditing result for feeding back audit unit 142
According to sending the read channel back to；Preferably, the built-in screening module of read channel control unit 141 will meet the uplink of screening conditions
Data are sent into audit unit；
The audit unit 142 sends the upstream data and its auditing result back to for auditing the upstream data together
The read channel control unit 141.Wherein, auditing result will be sent to together Cache12 with upstream data by additional signal lines
In entry.
According to above-described embodiment, rdma read protection component 14 is also configured with the audit for storing shielded memory address
Table 143, the check list 143 are configured as nuclear unit 142 on trial and access, and audit unit 142 according to the guarantor in the check list 143
It protects address and audits the upstream data, judge whether the upstream data comes from shielded region of memory.
Check list 143 used by the embodiment is the storage region in computing system, which can select interior
Partial region in depositing carry out using, also can use the partial memory area domain in the Cache of microprocessor internal carry out using；
Preferably, the check list is stored in the Buffer of piece internal buffer.Wherein, buffer is similarly one piece of storage inside CPU
Circuit is mainly used for storing the information such as list.
Since security mechanism of the invention is security mechanism in core, select Buffer as the storage position of audit Yuan
It sets, the review efficiency for auditing unit can be accelerated, reduce the efficiency influence that access memory obtains shielded memory address.
Check list in the embodiment of the present invention is provided with software interface, and developer or professional technician can be specific
Shielded memory address is written in the corresponding Cache entry of the check list by operating system under mode.
Further, each entry in the Cache12 in the present invention is configured with extension flag position；The extension mark
Will position is for storing the auditing result；The auditing result is write-inhibit flag or invalid flag；Wherein, the write-inhibit flag is used
Forbid being written back at the instruction Cache entry positions；Invalid flag then indicates not intervene the Cache entry, i.e., just
Often processing.Preferably, if the line width of each Cache entry is 64 bytes, then each Cache entry needs to increase 8bit
Flag bit, i.e., each flag bit corresponds to the data of 64bit.Preferably, write-inhibit flag can be used " 1 " to indicate, invalid flag then may be used
It is indicated with " 0 ".
Preferably, the Cache in the present invention includes: L1 Cache, L2 Cache；The structure of L1 Cache and L2 Cache
Unanimously, it is configured with extension flag position, for storing write-inhibit flag；Those skilled in the art should understand that be institute of the present invention
The Cache with L1 Cache and L2 Cache used simply facilitates the configuration illustrated in the present invention to Cache, should not limit
Protection scope of the present invention.It such as also include shared Cache in Cahce.
Microprocessor such as Fig. 5, in the embodiment of the present invention, further includes: write back control unit 144；It is described to write back control list
Member 144 is configured on the write access between the processor core 11 and Cache12, for identification in the Cache entry
Write-inhibit flag, forbid the Cache entry with write-inhibit flag to be write back by the processor core 11.
Preferably, it when there is write-inhibit flag in detecting the target Cache entry that processor core 11 writes back, also triggers
Interrupt instruction executes alarm and record operation.Such as when detecting that marked Cache will be to be modified, CPU thinks this
Secondary operation is abnormal operation, directly issues and interrupts.
The microprocessor of the embodiment of the present invention is substantially carried out following two operation:
1. reading audit marking operation when data
Processor core sends Address requests to Memory Controller Hub, to indicate that Memory Controller Hub is transferred in correspondence memory address
Data content；Memory Controller Hub extracts in the data content write-in Cache in correspondence memory address, and read channel control at this time is single
Member intercepts upstream data, which is committed to audit unit；With auditing source of the unit with the upstream data in memory
Location is compared one by one with the shielded memory address in check list, is compared successfully then by the upstream data and write-inhibit flag one
It rises and feeds back to read channel control unit, comparison is unsuccessful, and the upstream data is only fed back to read channel control unit；Read channel
Control unit sends upstream data or upstream data and write-inhibit flag in former read channel back to, is written in corresponding Cache entry,
If upstream data carries write-inhibit flag at this time, there is write-inhibit flag in the extension flag position in the Cache entry of storage；If
Upstream data does not carry write-inhibit flag, then the extension flag position in the Cache entry of its storage is invalid flag at this time.
The Cache entry with write-inhibit flag is forbidden to be written back into when 2. writing data
When processor core writes back, write back whether the target Cache entry that control unit detection writes back there is taboo to write mark
Note, if there is write-inhibit flag, then prevents target Cache entry from being written back into；If without write-inhibit flag, this time of directly letting pass
It writes back.Wherein, after preventing target Cache entry from being written back into, alarm and record operation are also executed.
Microprocessor in the embodiment of the present invention further include: memory protection component 15 is write, it is described to write memory protection component 15
It is configured on the write access between the Cache12 and the Memory Controller Hub 13, in auditing and writing back to from Cache12
The downlink data deposited.
Such as Fig. 6, further, the memory protection component 15 of writing includes: that write access control unit 151 and the audit are single
Member 142；Wherein, audit unit and check list can be separately configured by writing memory protection component 15, component can also be protected total with rdma read
With audit unit 142 and check list 143；Memory protection component 15 is write in the embodiment and rdma read protection component 14 shares audit
Unit and check list.
The write access control unit 151 configures on the write access between the Cache12 and Memory Controller Hub 13,
And connect with the audit unit 142, for intercepting downlink data on the write access, it is sent to the audit unit
142 are audited；And send the downlink data for carrying auditing result back to the write access；
The audit unit 142 is also used to audit the downlink data, judgement according to the protection address in audit Yuan
Whether the downlink data distorts shielded region of memory, sends the downlink data and its auditing result back to the write access control
Unit processed.
The present invention also by directly being audited to write access, prevents shielded region of memory to be tampered.
Further, when determining that the downlink data will distort shielded region of memory, the audit unit 142 is also
For modifying the destination address of the downlink data；Wherein, the modified destination address is not in the shielded memory field
In domain.
It in through the foregoing embodiment, can not only guarantee the normal operating of microprocessor, but also computing system is avoided to be attacked
It influences.
In the present invention above embodiments describe the embodiment of more microprocessor, it is one or more of to implement
Example is also combined into the scheme of independent microprocessor.
The structural block diagram of the secure microprocessor with write access audit framework is shown referring now to Fig. 7, Fig. 7, such as should
Shown in structural block diagram, disclose a kind of microprocessor, the microprocessor be built-in with processor core 11, cache Cache12,
The memory of writing of Memory Controller Hub 13 and the downlink data for writing back to memory from Cache protects component 15；It is described to write memory
Protection component 15 is configured on the write access between the Cache12 and the Memory Controller Hub 13.
The present invention configures memory protection component in the core of microprocessor, forbids shielded region of memory to be tampered, prevents
The only generation of memory injection attacks solves the problems, such as to lack security mechanism inside existing safe processor.
As shown in figure 8, the memory protection component 15 of writing in the embodiment of the present invention includes: write access control unit 151
With audit unit 152；Wherein, writing memory protects component 15 to be also configured with the check list for storing shielded memory address
153, which is configured as nuclear unit 152 on trial and accesses, and audits unit 152 according to the protection in the check list 153
The downlink data is audited in address, judges whether the downlink data comes from shielded region of memory.
The write access control unit 151 configures on the write access between the Cache12 and Memory Controller Hub 13,
And connect with the audit unit 152, for intercepting downlink data on the write access, it is sent to the audit unit
152 are audited；And send the downlink data for carrying auditing result back to the write access；
The audit unit 152 judges institute for auditing the downlink data according to the protection address in check list 153
It states whether downlink data distorts shielded region of memory, sends the downlink data and its auditing result back to the write access and control
Unit.
Further, when determining that the downlink data will distort shielded region of memory, the audit unit 152 is also
For modifying the destination address of the downlink data；Wherein, the modified destination address is not in the shielded memory field
In domain.
Preferably, it when there is write-inhibit flag in detecting the target Cache entry that processor core 11 writes back, also triggers
Interrupt instruction executes alarm and record operation.
Specifically, audit unit executes following audit and processing operation:
1. whether audit downlink data will distort shielded region of memory；
2. the target memory address of downlink data is modified, by downlink data after modification in the case where determining will distort
It is sent to Memory Controller Hub；In the case where determining without tampering, downlink data is directly sent to Memory Controller Hub；Its
In, in the case where determining will distort, execute alarm and record operation.
The invention also provides a kind of calculating equipment, which is equipped with the microprocessor in above-described embodiment.
A kind of structural block diagram of microprocessor is shown referring now to Fig. 9, Fig. 9, as shown in the structural block diagram, discloses one
Kind microprocessor, the microprocessor are built-in with processor core 11, cache Cache12 and are configured in the processing
Control unit 154 is write back on write access between device core 11 and Cache12, for identification in the Cache12 entry
Write-inhibit flag forbids the Cache12 entry with write-inhibit flag to be write back by the processor core 11.
Since Cache includes L1 Cache and L2 Cache, and L1 Cache is divided into Instruction Cache and data again
Cache, in normal processor stability framework, having limited Instruction Cache can not be tampered, therefore write back in the present invention
The preferred embodiment of control unit is on the write access being configured between processor core and data Cache.
The problem of preventing shielded memory address to be tampered can be played through the foregoing embodiment, in microprocessor core
Improve the safety and reliability of computing system.
The interaction of microcontroller core at present is completed based on protocol bus in piece, therefore micro- in the embodiment of the present invention
It can also increase in processor and then be also configured with read channel Master for example, by using AXI protocol interface for the bridge-jointing unit of interaction
(master) end, the end read channel Slave (from)；And the end write access Master (master), the end write access Slave (from), such as Figure 10.
1, Figure 11 shows the flow chart of method for protecting EMS memory in the present invention referring now to fig. 1, public as shown in the flow chart
A kind of method for protecting EMS memory is opened, this method is applied to microprocessor, comprising:
Step S11. judges whether the upstream data extracted from memory comes from shielded region of memory；
If the step S12. upstream data comes from shielded region of memory, write-inhibit flag is assigned to the upstream data；
Wherein, the write-inhibit flag is used to indicate the upstream data and forbids being modified；
Step S13. will carry the upstream data write cache Cache of the write-inhibit flag.
The case where passing through audit and write-inhibit flag in the embodiment of the present invention, crucial memory address can be prevented to be tampered；
On the other hand, by auditing in rdma read to upstream data, examination amount when writing memory can directly be reduced.
Judge whether the upstream data extracted from memory comes from shielded region of memory described in the embodiment, specifically
It include: to compare the source address of the upstream data in memory with shielded memory address in preconfigured check list
It is right；Consistent memory address is arrived if comparing, determines the upstream data from shielded region of memory.Wherein, the audit
Table is stored in the buffer.
Each entry in Cache described in the embodiment is configured with extension flag position；It uses the extension flag position
In the storage write-inhibit flag；Wherein, the write-inhibit flag, which is specifically used for instruction, has at the Cache entry positions of write-inhibit flag
Forbid being written back into.
In the embodiment it is described by carry the write-inhibit flag the upstream data write cache Cache it
Afterwards, further includes: whether the target Cache entry that measurement processor core writes back has write-inhibit flag；If there are the taboos for detection
Label is write, then the Cache entry is forbidden to be write back by processor core.
Present invention is alternatively directed to method for protecting EMS memory to propose a preferred embodiment, the method for protecting EMS memory in the embodiment,
Applied to the microprocessor in the embodiment of the present invention, comprising:
Step 1. processor core sends request of data to Memory Controller Hub；It wherein, include mesh in the request of data
Mark the target memory address of data；
Step 2. Memory Controller Hub receives and according to the request of data, extracts number of targets from the target memory address
According to (i.e. upstream data)；
Step 3. rdma read protects component to obtain target data, and will be in the memory address and check list of the target data
Shielded memory address is compared one by one, after the completion of comparison, (is compared and is successfully write mark to prohibit target data and comparison result
Note, comparing unsuccessfully is invalid flag) send former read channel back to, it is written in corresponding Cache；
When step 4. processor core writes back Cache, writes back control unit and obtain write back data, and detect this and write
Whether have write-inhibit flag, if there is then forbidding the write back data that its target Cache is written if returning in the target Cache entry of data
In entry；The write back data is not handled if not, write back data will write direct its target Cache entry.
2, Figure 12 shows the structural block diagram for executing the microprocessor of method for protecting EMS memory referring now to fig. 1, such as the structure
Shown in block diagram, a kind of microprocessor 100 is disclosed, comprising: it is protected to judge whether the upstream data extracted from memory comes from
Region of memory judgment module 101；If the upstream data comes from shielded region of memory, which is assigned and is prohibited
Write the mark module 102 of label；Wherein, the write-inhibit flag is used to indicate the upstream data and forbids being modified；It will carry
State the writing module 103 of the upstream data write cache Cache of write-inhibit flag.
Judgment module described in the embodiment be specifically used for by upstream data source address in memory be pre-configured with
Check list in shielded memory address be compared；Consistent memory address is arrived if comparing, determines that the upstream data comes
From shielded region of memory.
Check list described in the embodiment is stored in piece in buffer.
Each entry in Cache described in the embodiment is configured with extension flag position；It uses the extension flag position
In the storage write-inhibit flag；Wherein, the write-inhibit flag, which is specifically used for instruction, has at the Cache entry positions of write-inhibit flag
Forbid being written back into.
Microprocessor in the embodiment, further includes: whether the target Cache entry that measurement processor core writes back has
The detection module 104 of write-inhibit flag；If detection forbids the Cache entry to be write by processor core there are the write-inhibit flag
The taboo writing module 105 returned.
3, Figure 13 shows the flow chart that the method for memory injection attacks is prevented in the present invention referring now to fig. 1, such as the stream
Shown in journey figure, a kind of method for preventing memory injection attacks is disclosed, this method is applied to microprocessor, comprising:
Whether the target memory address for the downlink data that memory will be written in step S31. judgement belongs to shielded memory
Region；
If the target memory address of the step S32. downlink data belongs to shielded region of memory, forbid the lower line number
According to its target memory address of write-in.
The embodiment of the present invention is audited by the downlink data for directly returning memory to CPU write, prevents to close in computing system
Key region of memory is tampered, and guarantees the safety and reliability of computing system.
It is protected to judge whether the target memory address for the downlink data that memory will be written belongs to described in the embodiment
Region of memory, specifically include: will it is shielded in the target memory address of the downlink data and preconfigured check list in
Address is deposited to be compared；Consistent memory address is arrived if comparing, determines that the target memory address of the downlink data belongs to and is protected
The region of memory of shield.Preferably, the check list is stored in piece in buffer.
Forbid the downlink data that its target memory address is written described in the embodiment, specifically include: modifying the downlink
Memory is written according to modified target memory address in the downlink data by the target memory address of data；Wherein, modified
The destination address is not in the shielded region of memory.
Present invention is alternatively directed to prevent memory injection attacks from also proposed a preferred embodiment, memory is prevented in the embodiment
The method of injection attacks, applied to the microprocessor in the embodiment of the present invention, comprising:
Step 1.Cache inwardly deposits into row data and writes back, and write back data (i.e. downlink data) is sent to Memory Controller Hub；
Step 2. writes memory protection component and obtains the write back data, and by the target memory address of the write back data and audit
Shielded memory address in table is compared one by one；
Step 3. compares successfully, then modifies the target memory address of the write back data, modified write back data is sent back to
Assigned core position is written in former write access；And execute alarm and record operation；
Step 4. compares unsuccessful, then directly sends the write back data back to former write access, and corresponding core position is written.
4, Figure 14 shows the structural block diagram for executing the microprocessor of method for protecting EMS memory referring now to fig. 1, such as the structure
Shown in block diagram, a kind of microprocessor 200 is disclosed, comprising: the target memory address of the downlink data of memory will be written in judgement
Whether the judgment module 201 of shielded region of memory is belonged to；If the target memory address of the downlink data belongs to shielded
Region of memory then forbids the downlink data that the control module 202 of its target memory address is written.
Judgment module described in the embodiment be specifically used for by the target memory address of the downlink data with it is preconfigured
Shielded memory address is compared in check list；Consistent memory address is arrived if comparing, determines the mesh of the downlink data
Mark memory address belongs to shielded region of memory.
Check list described in the embodiment is stored in piece in buffer.
In control module described in the embodiment, comprising: modify the modification mould of the target memory address of the downlink data
Block 203；By the downlink data according to the writing module 204 of modified target memory address write-in memory；Wherein, modified
The destination address is not in the shielded region of memory.
The invention also discloses a kind of calculating equipment, which, which is equipped with any of the above-described kind, has the micro- of security mechanism
Processor, the calculating equipment can set for main frame, all-in-one machine, portable computer, intelligent hand-held terminal, intelligence wearing
The smart machine that microprocessor can be assembled such as standby.
It should also be appreciated by one skilled in the art that various illustrative logical boxs, mould in conjunction with the embodiments herein description
Electronic hardware, computer software or combinations thereof may be implemented into block, circuit and algorithm steps.In order to clearly demonstrate hardware and
Interchangeability between software surrounds its function to various illustrative components, frame, module, circuit and step above and carries out
It is generally described.Hardware is implemented as this function and is also implemented as software, depends on specific application and to entire
The design constraint that system is applied.Those skilled in the art can be directed to each specific application, be realized in a manner of flexible
Described function, still, this realization decision should not be construed as a departure from the scope of protection of this disclosure.
The above description of the embodiment is only used to help understand the method for the present invention and its core ideas；Meanwhile for this
The those skilled in the art in field, according to the thought of the present invention, there will be changes in the specific implementation manner and application range,
In conclusion the contents of this specification are not to be construed as limiting the invention.
Claims (9)
1. a kind of method for preventing memory injection attacks, which is characterized in that be applied to microprocessor, comprising:
Judge whether the target memory address for the downlink data that memory will be written belongs to shielded region of memory；
If the target memory address of the downlink data belongs to shielded region of memory, forbid the downlink data that its target is written
Memory address.
2. the method according to claim 1 for preventing memory injection attacks, which is characterized in that in the judgement will be written
Whether the target memory address for the downlink data deposited belongs to shielded region of memory, specifically includes:
The target memory address of the downlink data is compared with shielded memory address in preconfigured check list；
Consistent memory address is arrived if comparing, determines that the target memory address of the downlink data belongs to shielded memory field
Domain.
3. the method according to claim 2 for preventing memory injection attacks, which is characterized in that the check list is stored in piece
In the Buffer of internal buffer.
4. the method according to claim 1 for preventing memory injection attacks, which is characterized in that described to forbid the downlink data
Its target memory address is written, specifically includes:
The target memory address for modifying the downlink data, by the downlink data according in the write-in of modified target memory address
It deposits；Wherein, the modified destination address is not in the shielded region of memory.
5. a kind of microprocessor characterized by comprising
Judgment module, for judging to be written whether the target memory address of downlink data of memory belongs to shielded memory
Region；
Control module forbids the downlink if the target memory address for the downlink data belongs to shielded region of memory
Its target memory address is written in data.
6. microprocessor according to claim 5, which is characterized in that the judgment module is specifically used for the downlink data
Target memory address be compared with shielded memory address in preconfigured check list；
Consistent memory address is arrived if comparing, determines that the target memory address of the downlink data belongs to shielded memory field
Domain.
7. microprocessor according to claim 6, which is characterized in that the check list is stored in piece internal buffer Buffer
In.
8. microprocessor according to claim 5, which is characterized in that in the control module, comprising:
Modified module, for modifying the target memory address of the downlink data；
Writing module, for memory to be written according to modified target memory address in the downlink data；
Wherein, the modified destination address is not in the shielded region of memory.
9. a kind of calculating equipment, which is characterized in that the calculating equipment is equipped with the described in any item micro processs of claim 5-8
Device.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112256605A (en) * | 2020-11-03 | 2021-01-22 | 蔺建琪 | Secure DMA controller and data transfer method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112256605A (en) * | 2020-11-03 | 2021-01-22 | 蔺建琪 | Secure DMA controller and data transfer method |
| CN112256605B (en) * | 2020-11-03 | 2024-05-17 | 蔺建琪 | Secure DMA controller and data handling method |
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