CN109753000A - A kind of multiduty intelligent substation high-speed sampling method and device - Google Patents
A kind of multiduty intelligent substation high-speed sampling method and device Download PDFInfo
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- CN109753000A CN109753000A CN201910046831.5A CN201910046831A CN109753000A CN 109753000 A CN109753000 A CN 109753000A CN 201910046831 A CN201910046831 A CN 201910046831A CN 109753000 A CN109753000 A CN 109753000A
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Abstract
The invention discloses a kind of multiduty intelligent substation high-speed sampling methods, include the following steps, FPGA high-speed data acquisition；FPGA low-pass filtering, FPGA linear interpolation, FPGA data push, DSP application sample data.Present invention simultaneously discloses a kind of multiduty intelligent substation high-speed sampling devices.The present invention program; compared with prior art, it realizes from FPGA high-speed data acquisition, according to the sample rate and low-pass coefficients of different application settings; complete the filtering and interpolation processing of the data of each application; it can satisfy protection, observing and controlling, the data requirements of combining unit and fault oscillograph; DSP load factor is low; scalability is strong, and integrated for intelligent substation multifunctional equipment provides a kind of method for being multiplexed sampled data, has a good application prospect.
Description
Technical field
The present invention relates to intelligent substation of electric power system fields, and in particular to a kind of multiduty intelligent substation high speed is adopted
Quadrat method and device.
Background technique
Intelligent substation uses digitized communication mode, substantially increases data sharing abilities, also promotes dress indirectly
That sets is integrated.From the discrete arrangement of protection observing and controlling of early stage, device is integrated to protecting to survey, in station domain protective device finally,
And All-in-One device, the integrated level of device is higher and higher, and data sharing degree is increasing.
State Grid of China Technology College's journal was in an article of volume 2 " intelligent substation 110 (66) kV system All-in-One in 2016
Device reorganizing research " in mention, a kind of integrated protection, observing and controlling, non-energy metering, combining unit, intelligent terminal All-in-One dress
It sets.
Since the demand of each applied business is different, cause the demand to device sample rate and cutoff frequency also different, it is right
The cutoff frequency of sample rate and frequency not higher than 300Hz that 1.2kHz is generally required for protective device, fills observing and controlling
The sample rate of 2.4kHz is generally required for setting, cutoff frequency is not higher than the sample rate of 1.2kHz, one for combining unit
As require the sample rate of 4kHz, cutoff frequency is generally not more than 2kHz, adopting for 10kHz is generally required for fault oscillograph
Sample rate, cutoff frequency are generally not more than 5kHz.So so for Multi-applications Integration into a device, the demand of multi-sampling rate can not
By same set of hardware realization, needs to configure different sampling boards and realize different sample rate and low-pass cut-off frequencies, cause
Integrated difficulty.
Summary of the invention
It is an object of the present invention to can not be matched by same set of hardware realization, needs to solve the demand of multi-sampling rate
The problem of different sampling boards realizes different sample rates and low-pass cut-off frequencies is set, proposes a kind of multiduty intelligent power transformation
It stands high-speed sampling method, different samplings is interpolated to using different filtering algorithms using the high-speed data acquisition that FPGA is unified
Frequency can satisfy the different sample rates of each application and the requirement of different cutoff frequencies.
In order to achieve the above object, the technical scheme adopted by the invention is that:
A kind of multiduty intelligent substation high-speed sampling method, includes the following steps,
Step (A), FPGA high-speed data acquisition: FPGA directly controls the data conversion of ADC, and the data for passing through ADC
The sampled data of bus reading ADC；Then step (B) is executed；
Step (B), FPGA low-pass filtering: FPGA carries out the filtering processing of data using low-pass filtering；Then step is executed
(C)；
Step (C) FPGA linear interpolation: according to the sample rate of setting, goes out sampled data using linear interpolation method interpolation；
Then step (D) is executed；
Step (D), FPGA data push: the sampled data after interpolation is pushed to DDR by FPGA by the way of DMA；So
Execute step (E) afterwards；
Step (E), DSP application sample data: the sampled data that DSP application program is read in DDR is calculated, and terminates stream
Journey.
Further, FPGA directly controls the data conversion of AD, and the data/address bus for passing through ADC in the step (A)
Read the sampled data of ADC specifically: FPGA controls the CONVERT pin of ADC chip, and then controls the sample conversion of ADC, adopts
With rising edge, failing edge or double edge triggerings.
Further, in the step (B) linear filtering formula are as follows:
Wherein, y (n) is the sampled value after linear filtering, and x (n-k) is to move back the data of k point before original sample value, and b (k) is
Filter factor, k are sampled point serial number, and the value of k is 0-15, i.e. 16 filter factors.
Further, the filter factor is multiple groups, the output corresponding to multiple groups low-pass filtering.
Further, in the step (C) linear interpolation method formula are as follows:
Wherein, y (t) is the sampled value after linear interpolation, and k is sampled point serial number, and x (k) is the sampled value of original k point, x (k
It+1) is the sampled value of original k+1 point, t0Corresponding markers, t are put for x (k)1Corresponding markers is put for x (k+1), t is linear interpolation
Markers, tsFor the crude sampling period.
Further, it includes the different application of multiple groups, the functional module different corresponding to multiple groups that the DSP, which is applied,.
The present invention accordingly proposes a kind of multiduty intelligent substation high-speed sampling device, including FPGA high-speed data is adopted
Collect unit, FPGA low-pass filter unit, FPGA linear interpolation unit, FPGA data push unit, DSP application sample data sheet
Member, each unit are sequentially connected with；Wherein:
The FPGA high-speed data acquisition unit: the data conversion of ADC, and the number for passing through ADC are directly controlled by FPGA
The sampled data of ADC is read according to bus；
The FPGA low-pass filter unit: it receives the sampled data of the FPGA high-speed data acquisition unit and is adopted by FPGA
The filtering processing of data is carried out with low-pass filtering；
The FPGA linear interpolation unit: the processed data of FPGA low-pass filter unit are received, according to setting
Sample rate goes out sampled data using linear interpolation method interpolation；
The FPGA data push unit: FPGA uses the sampled data after the FPGA linear interpolation unit interpolation
The mode of DMA is pushed to DDR；
The DSP application sample data cell: the sampled data that DSP application program is read in DDR is calculated.
Further, the data conversion of AD is directly controlled by FPGA in the FPGA high-speed data acquisition unit, and lead to
The data/address bus for crossing ADC reads the sampled data of ADC specifically: FPGA controls the CONVERT pin of ADC chip, and then controls
The sample conversion of ADC is triggered using rising edge, failing edge or double edges.
Further, in the FPGA low-pass filter unit linear filtering formula are as follows:
Wherein, y (n) is the sampled value after linear filtering, and x (n-k) is to move back the data of k point before original sample value, and b (k) is
Filter factor, k are sampled point serial number, and the value of k is 0-15, i.e. 16 filter factors.
Further, the filter factor is multiple groups, the output corresponding to multiple groups low-pass filtering.
Further, in the FPGA linear interpolation unit linear interpolation method formula are as follows:
Wherein, y (t) is the sampled value after linear interpolation, and k is sampled point serial number, and x (k) is the sampled value of original k point, x (k
It+1) is the sampled value of original k+1 point, t0Corresponding markers, t are put for x (k)1Corresponding markers is put for x (k+1), t is linear interpolation
Markers, tsFor the crude sampling period.
Further, it includes the different application of multiple groups, the functional module different corresponding to multiple groups that the DSP, which is applied,.
The beneficial effects of the present invention are: using multiduty intelligent substation high-speed sampling method of the present invention, energy
The requirement of the different sample rates and different cutoff frequencies that enough meet each application is answered using the high-speed data acquisition that FPGA is unified
With different filtering algorithms, it is interpolated to different sample frequencys, meets the integrated requirement of various applications, it is negative to reduce dsp chip
Load rate improves the integrated level of device, and scalability is strong, provides a kind of multiplexing for the integrated of intelligent substation multifunctional equipment
Using the method for data, have a good application prospect.
Detailed description of the invention
Fig. 1 is a kind of multiduty intelligent substation high-speed sampling method flow chart of the invention.
Fig. 2 is a kind of multiduty intelligent substation high-speed sampling structure drawing of device of the invention.
Specific embodiment
Below in conjunction with Figure of description, the present invention is further illustrated.
A kind of multiduty intelligent substation high-speed sampling method of the invention, comprising the following steps:
Step (A), FPGA high-speed data acquisition.FPGA directly controls the data conversion of ADC, and the data for passing through ADC
The sampled data of bus reading ADC.After executing the step (A), execute step (B).
Step (B), FPGA low-pass filtering.FPGA carries out the filtering processing of data using low-pass filtering；Execute the step (B)
Afterwards, step (C) is executed.
Step (C), FPGA linear interpolation.According to the sample rate of setting, sampled data is gone out using linear interpolation method interpolation；
After executing the step (C), execute step (D).
Step (D), FPGA data push.Sampled data after interpolation is pushed to DDR by FPGA by the way of DMA；It holds
It has gone after step (D), has executed step (E).
Step (E), DSP application sample data.The sampled data that DSP application program is read in DDR is calculated.Terminate stream
Journey.
In above scheme, FPGA directly controls the data conversion of AD in the step (A), and total by the data of ADC
The sampled data of line reading ADC specifically: FPGA controls the CONVERT pin of ADC chip, and then controls the sample conversion of ADC,
Using rising edge, failing edge or double edge triggerings, to improve sampling rate.
In above scheme, the formula of linear filtering in the step (B) are as follows:
Wherein, y (n) is the sampled value after linear filtering, and x (n-k) is to move back the data of k point before original sample value, and b (k) is
Filter factor.K is sampled point serial number, and the value of k is 0-15, that is, 16 filter factors, filter factor can be zero.
In above scheme, the filter factor is multiple groups, more in the present embodiment corresponding to the output of multiple groups low-pass filtering
The group number of group is 1-5 group.
In above scheme, the formula of linear interpolation method in the step (C) are as follows:
Wherein, y (t) is the sampled value after linear interpolation, and k is sampled point serial number, and x (k) is the sampled value of original k point, x (k
It+1) is the sampled value of original k+1 point, t0Corresponding markers, t are put for x (k)1Corresponding markers is put for x (k+1), t is linear interpolation
Markers, tsFor the crude sampling period.
In above scheme, it is the different application of multiple groups, the functional module different corresponding to multiple groups, sheet that the DSP, which is applied,
The group number of multiple groups is 1-5 group in embodiment.
The present invention accordingly proposes a kind of multiduty intelligent substation high-speed sampling device, as shown in Fig. 2, including FPGA
High-speed data acquisition unit, FPGA low-pass filter unit, FPGA linear interpolation unit, FPGA data push unit, DSP application are adopted
Sample data cell, each unit are sequentially connected with；Wherein:
The FPGA high-speed data acquisition unit: the data conversion of ADC, and the number for passing through ADC are directly controlled by FPGA
The sampled data of ADC is read according to bus.
Wherein, the data conversion of AD is directly controlled by FPGA in the FPGA high-speed data acquisition unit, and pass through ADC
Data/address bus read the sampled data of ADC specifically: FPGA controls the CONVERT pin of ADC chip, and then controls ADC
Sample conversion is triggered using rising edge, failing edge or double edges.
The FPGA low-pass filter unit: it receives the sampled data of the FPGA high-speed data acquisition unit and is adopted by FPGA
The filtering processing of data is carried out with low-pass filtering.
Wherein, in the FPGA low-pass filter unit linear filtering formula are as follows:
Wherein, y (n) is the sampled value after linear filtering, and x (n-k) is to move back the data of k point before original sample value, and b (k) is
Filter factor, k are sampled point serial number, and the value of k is 0-15, i.e. 16 filter factors.The filter factor is multiple groups, is corresponded to
The output of multiple groups low-pass filtering.
The FPGA linear interpolation unit: the processed data of FPGA low-pass filter unit are received, according to setting
Sample rate goes out sampled data using linear interpolation method interpolation.
Wherein, in the FPGA linear interpolation unit linear interpolation method formula are as follows:
Wherein, y (t) is the sampled value after linear interpolation, and k is sampled point serial number, and x (k) is the sampled value of original k point, x (k
It+1) is the sampled value of original k+1 point, t0Corresponding markers, t are put for x (k)1Corresponding markers is put for x (k+1), t is linear interpolation
Markers, tsFor the crude sampling period.
The FPGA data push unit: FPGA uses the sampled data after the FPGA linear interpolation unit interpolation
The mode of DMA is pushed to DDR.
The DSP application sample data cell: the sampled data that DSP application program is read in DDR is calculated.Described
It includes the different application of multiple groups, the functional module different corresponding to multiple groups that DSP, which is applied,.
Basic principles and main features and advantage of the invention have been shown and described above.The technical staff of the industry should
Understand, the present invention is not limited to the above embodiments, and the above embodiments and description only describe originals of the invention
Reason, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these changes and improvements
It all fall within the protetion scope of the claimed invention.The claimed scope of the invention is by appended claims and its equivalent circle
It is fixed.
Claims (10)
1. a kind of multiduty intelligent substation high-speed sampling method, it is characterised in that: include the following steps,
Step (A), FPGA high-speed data acquisition: FPGA directly controls the data conversion of ADC, and the data/address bus for passing through ADC
Read the sampled data of ADC；Then step (B) is executed；
Step (B), FPGA low-pass filtering: FPGA carries out the filtering processing of data using low-pass filtering；Then step (C) is executed；
Step (C) FPGA linear interpolation: according to the sample rate of setting, goes out sampled data using linear interpolation method interpolation；Then
It executes step (D)；
Step (D), FPGA data push: the sampled data after interpolation is pushed to DDR by FPGA by the way of DMA；Then it holds
Row step (E)；
Step (E), DSP application sample data: the sampled data that DSP application program is read in DDR is calculated, and terminates process.
2. a kind of multiduty intelligent substation high-speed sampling method according to claim 1, which is characterized in that
FPGA directly controls the data conversion of AD in the step (A), and the sampling of ADC is read by the data/address bus of ADC
Data specifically: FPGA controls the CONVERT pin of ADC chip, and then controls the sample conversion of ADC, using rising edge, decline
Edge is double along triggering.
3. a kind of multiduty intelligent substation high-speed sampling method according to claim 1, which is characterized in that
The formula of linear filtering in the step (B) are as follows:
Wherein, y (n) is the sampled value after linear filtering, and x (n-k) is the data that k point is moved back before original sample value, and b (k) is filtering
Coefficient, k are sampled point serial number, and the value of k is 0-15, i.e. 16 filter factors.
4. a kind of multiduty intelligent substation high-speed sampling method according to claim 3, which is characterized in that
The filter factor is multiple groups, the output corresponding to multiple groups low-pass filtering.
5. a kind of multiduty intelligent substation high-speed sampling method according to claim 1, it is characterised in that:
The formula of linear interpolation method in the step (C) are as follows:
Wherein, y (t) is the sampled value after linear interpolation, and k is sampled point serial number, and x (k) is the sampled value of original k point, x (k+1)
For the sampled value of original k+1 point, t0Corresponding markers, t are put for x (k)1Corresponding markers is put for x (k+1), when t is linear interpolation
Mark, tsFor the crude sampling period.
6. a kind of multiduty intelligent substation high-speed sampling method according to claim 1, it is characterised in that:
It includes the different application of multiple groups, the functional module different corresponding to multiple groups that the DSP, which is applied,.
7. a kind of multiduty intelligent substation high-speed sampling device, it is characterised in that: including FPGA high-speed data acquisition unit,
FPGA low-pass filter unit, FPGA linear interpolation unit, FPGA data push unit, DSP application sample data cell, each unit
It is sequentially connected with；Wherein:
The FPGA high-speed data acquisition unit: the data conversion of ADC is directly controlled by FPGA, and total by the data of ADC
The sampled data of line reading ADC；
The FPGA low-pass filter unit: the sampled data of the FPGA high-speed data acquisition unit is received and by FPGA using low
The filtering processing of pass filter progress data；
The FPGA linear interpolation unit: the processed data of FPGA low-pass filter unit are received, according to the sampling of setting
Rate goes out sampled data using linear interpolation method interpolation；
The FPGA data push unit: the sampled data after the FPGA linear interpolation unit interpolation is used DMA by FPGA
Mode be pushed to DDR；
The DSP application sample data cell: the sampled data that DSP application program is read in DDR is calculated.
8. a kind of multiduty intelligent substation high-speed sampling device according to claim 7, which is characterized in that
The data conversion of AD is directly controlled in the FPGA high-speed data acquisition unit by FPGA, and total by the data of ADC
The sampled data of line reading ADC specifically: FPGA controls the CONVERT pin of ADC chip, and then controls the sample conversion of ADC,
Using rising edge, failing edge or double edge triggerings.
9. a kind of multiduty intelligent substation high-speed sampling device according to claim 7, which is characterized in that
The formula of linear filtering in the FPGA low-pass filter unit are as follows:
Wherein, y (n) is the sampled value after linear filtering, and x (n-k) is the data that k point is moved back before original sample value, and b (k) is filtering
Coefficient, k are sampled point serial number, and the value of k is 0-15, i.e. 16 filter factors.
10. a kind of multiduty intelligent substation high-speed sampling device according to claim 7, it is characterised in that:
The formula of linear interpolation method in the FPGA linear interpolation unit are as follows:
Wherein, y (t) is the sampled value after linear interpolation, and k is sampled point serial number, and x (k) is the sampled value of original k point, x (k+1)
For the sampled value of original k+1 point, t0Corresponding markers, t are put for x (k)1Corresponding markers is put for x (k+1), when t is linear interpolation
Mark, tsFor the crude sampling period.
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Application publication date: 20190514 |