CN109743562A - Matching cost counting circuit structure and its working method based on Census algorithm - Google Patents
Matching cost counting circuit structure and its working method based on Census algorithm Download PDFInfo
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Abstract
The invention discloses a kind of matching cost counting circuit structures and its working method based on Census algorithm, it include: the first stage, the original left images pixel value that the left and right camera of binocular camera is shot, interval specified period enter cache module and are cached；Second stage carries out window interior processing to left images, and the data information from cache module enters window module, handles and exports within the specified period；Phase III, initial cost are sought and are optimized, and the data obtained through window processing module enter computing module completion initial cost within the specified period and seek optimizing with the Bit String digit of initial cost, are finally spliced by output module and are exported.Matching cost counting circuit structure and its working method provided by the invention based on Census algorithm, calculating process relates to the operations such as addition and subtraction and exclusive or, also the circuit structures such as adder, subtracter, exclusive or have mainly been used in circuit, it realizes that image and video data conversion process are simple, Resources on Chip consumption can be reduced.
Description
Technical field
The invention belongs to images, technical field of video processing, and in particular to a kind of pair of image, video carry out pretreated base
In the matching cost counting circuit structure and its working method of Census algorithm.The present invention can be used for high-definition image, video into
The stereo matching system that row is handled in real time.
Background technique
With the fast development of computer vision, requirement of the people to video resolution is higher and higher, video resolution court
4K (3840 × 2160) and 8K (7680 × 4320) ultra high-definition direction develop.Stereo matching is one crucial in stereoscopic vision
Point, Stereo matching is a kind of technology of the depth information of target object for restoring shooting from flat image.
Binocular stereo vision is on the basis for fully understanding and analyzing human visual system's working principle, in conjunction with existing
Technological means simulates human visual system using video camera and computer.The basic principle is that: first using in different location
On two or more video cameras same target is shot, obtain two dimensional image from different visual angles；Spatial point is in gained
To image in position deviation calculated according to pixel matching；It is finally former using triangulation according to obtained position deviation
Reason is to carry out three-dimensional reconstruction.Stereo matching mainly includes asking the calculating of initial matching cost, cost polymerization, disparity computation and parallax excellent
Change.
The development of Stereo Matching Technology is maked rapid progress, with the raising of matching algorithm precision and speed, application scenarios into
One step expands.Census algorithm is a kind of method for calculating initial cost, is important a part in stereo matching system, for
How the stereo matching system of high-definition image, video accomplishes that lower cost, key are how to reduce in actual use
Resources on Chip consumption；Resources on Chip consumption is only efficiently controlled, just can guarantee and be preferably applied in engineering practice.
Census Region Matching Algorithm is to belong to one kind of nonparametric zone algorithm, and Census transformation is based on neighborhood gray scale
Compare and not gray scale itself, therefore the Region Matching Algorithm based on Census transformation compares phenomena such as gain and luminance deviation
Robust, and Census transformation remains the location information of neighborhood territory pixel, has good matching effect.Based on Census algorithm
Matching cost computing hardware circuit structure mainly include original left images caching；Window interior is carried out to left images
Processing；Three phases are sought and optimized to initial cost.Input of the output as next stage on last stage, the pixel of caching
Value Data is exported to window module, and left images window calculation, which goes out Bit String and exports, calculates to next stage and optimize initial generation
Valence.Census transformation be it is a kind of for sectional perspective matched non-parametric transformations, conversion process is simple, only used addition and subtraction and
The operations such as exclusive or, the resource consumption for controlling Census conversion section have important meaning to the control of stereo matching system entirety resource
Justice.
Summary of the invention
The purpose of the present invention is design a kind of matching cost counting circuit knot based on Census algorithm of low consumption of resources
Structure and its working method, for seeking initial cost, to support the binocular solid of high-definition image, video to match work and Three-dimensional Gravity
Build work.
In view of this, the present invention provides a kind of matching cost counting circuit structure based on Census algorithm, comprising:
Cache module, it is real including the left image cache module and right image cache module being made of random access memory
The caching of the pixel value for the left images that now the left and right camera of binocular camera is shot；
Further, left image cache module is identical with right image cache module structure, including the specified number connected side by side
The random access memory of amount, the specified quantity value are the even number not less than 2.
Further, the random access memory depth in left image cache module be less than right image cache module in
The depth of machine access memory.
Window processing module, including the left image processing module being made of window array and right image processing module and
Corresponding shifting cache module, the pixel value in alignment processing left image cache module and right image cache module obtain new ratio
Spy's string output；
Further, left image processing module and right image processing module window array having the same, the window array
It is built by shift register.
Further, which is window width × window height arrangement, wherein window width and window height are
Identical or different odd number.
Further, the most central point of window array is window center, and the value of storage is center pixel value, with window array
Remaining each pixel value of storage relatively obtains new Bit String output.
Further, right image processing module increases by an offset buffer on the basis of window processing module, the caching
Device exports after caching to the output Bit String of window array in right image processing module.
Computing module, including exclusive or processing module and count processing module, the exclusive or processing modules implement to left image at
The output Bit String for managing module and right image processing module is specifying the step-by-step exclusive or in the period, and exports exclusive or result to counting
Processing module, the counting processing module are sought corresponding Hamming distance within the specified period and are exported, i.e. initial cost；
Optimization module, including comparator and execution module realize the Bit String digit within the specified period to initial cost
Optimization；
Bit String after optimization is stored in different deposits by the period by output module, including register module and splicing module
In device, then the Bit String in different registers is combined using splicing module, obtains final optimization initial cost number
It is believed that breath.
Based on foregoing circuit, the work for matching cost counting circuit structure based on Census algorithm that the present invention also provides this
Make method, treatment process is divided into 3 stages:
Original image is obtained first, shoots to obtain left image and right image by the left camera and right camera of binocular camera, so
After carry out treatment by stages；
First stage is image buffer storage, and it is slow that the pixel value interval of the left image and right image specified period respectively enters left image
Storing module and right image cache module are cached；
Second stage is window calculation, the data information from left image cache module and right image cache module respectively into
Enter left image window processing module and right image window processing module to handle and export within the specified period；
Phase III is that initial cost is sought and optimized, and the data obtained through window processing module enter computing module and referring to
Step-by-step exclusive or is completed in fixed cycle, initial cost is then sought in specified period, realizes initial generation subsequently into optimization module
The Bit String digit of valence optimizes, and finally combines output by output module.
Further, window calculation includes:
To be removed in window array the pixel value of remaining each window storage other than center pixel value respectively with imago in this
Element value carries out size comparison, and number of comparisons indicates with i, i=window width × window height -1, as a result obtain that bit wide is i 2 into
Bit String processed；
Using left image as target figure, right image is used as with reference to figure, is searched for from left to right；
Left image obtains the 2 system Bit Strings that a bit wide is i by window calculation, and right image first does n times window calculation,
The Bit String obtained every time is cached, the 2 system Bit Strings that n bit wide is i are obtained；
By right image through handling the 2 system Bit Strings that n obtained bit wide is i and 1 position that left image is obtained through processing
Width is that the 2 system Bit Strings of i are output to that initial cost is sought and the optimizing phase is calculated and optimized.
Further, initial cost seek and optimize include:
Input of the output in window calculation stage as this stage, by left image through handling an obtained bit wide as the 2 of i
System Bit String and right image are handled n obtained bit wide and carry out step-by-step respectively in computing module for the 2 system Bit Strings of i
Xor operation finds out the 2 system Bit Strings that n new bit wides are i；
Hamming distance is calculated according to the 2 system Bit Strings that new bit wide is i；
Compression truncation optimization is carried out to Hamming distance in optimization module, obtains initial cost.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing do and simply introduce, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the matching cost computing hardware circuit structure signal described in the embodiment of the present invention based on Census algorithm
Figure；
Fig. 2 is the electrical block diagram of the gray value caching of left image described in the embodiment of the present invention；
Fig. 3 is the electrical block diagram of the gray value caching of right image described in the embodiment of the present invention；
Fig. 4 is the electrical block diagram that left figure window interior described in the embodiment of the present invention calculates；
Fig. 5 is the electrical block diagram that right figure window interior described in the embodiment of the present invention calculates；
Fig. 6 is that left and right figure described in the embodiment of the present invention exports Bit String step-by-step XOR circuit structural schematic diagram；
Fig. 7 is the electrical block diagram of calculating Hamming distance described in the embodiment of the present invention；
Fig. 8 is that initial cost described in the embodiment of the present invention optimizes electrical block diagram；
Fig. 9 is that the initial cost under all parallaxes described in the embodiment of the present invention combines output circuit schematic diagram.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawing, the present invention is proposed
The matching cost counting circuit structure chart based on Census algorithm be described further.Obviously, described embodiment is only
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiment of the present invention, those skilled in the art
Every other embodiment obtained without making creative work, belongs to protection scope of the present invention.
One embodiment of the invention provides a kind of matching cost counting circuit structure based on Census algorithm, the circuit knot
Structure realizes Census transformation and shoots to obtain a left side by the left camera of binocular camera and right camera first before using the circuit
Image and right image, in the present embodiment, left image and right image are gray level image, and gray value should as original value input
Circuit carries out calculation processing, further please refers to Fig. 1, which includes:
Cache module, it is real including the left image cache module and right image cache module being made of random access memory
The caching of the pixel value for the left images that now the left and right camera of binocular camera is shot；
In some embodiments, left image cache module is identical with right image cache module structure, including the finger connected side by side
The random access memory of fixed number amount, the specified quantity value are the even number not less than 2.
In the present embodiment, left image cache module and right image cache module are realized to left image sum of the grayscale values right image ash
The caching of angle value, specifically, Fig. 2 and Fig. 3 give the structure chart of left and right gray level image pixel write-in ram, including left and right
Image buffer storage module, it can be seen that left images cache module structure having the same, write-in and the mode read are also identical,
Left images cache module provided in this embodiment includes 4 ram connected side by side, i.e. random access memories, from top to bottom
Successively label ram0, ram1, ram2, ram3.
In some embodiments, the random access memory depth in left image cache module is less than in right image cache module
Random access memory depth.
In the present embodiment, the ram depth of right image cache module is identical with picture traverse, the ram of left image cache module
Depth is different with the ram depth of right image cache module, and the ram depth of left image cache module is less than right image cache module,
I.e. left figure has a certain number of pixel datas not need to cache, and the ram of left image cache module, which reads data, can also lag right image
The clock cycle of tetra- times of identical quantity of ram of cache module.
Further, the stage is cached in pixel value, the caching of left images is all using dual-port ram, the circuit structure
The caching to left images pixel value is completed within the specified period, it is assumed that the specified period of the present embodiment is 4, then every 4 clocks
Period, a pixel was written into ram, and the pixel value that do not go together is write into different ram, which ram is written by presently written
Rear 2 decisions of the counter of the image line of ram, first write, then write into ram1, ram2, ram3 to ram0, then into ram0
It writes, the data before covering.Ram is preferential using writing, and every 4 clock cycle read one group of data, reads data and starts from third row write
Data start, and newest data line is exactly the third line at this time, and ram2 will be written in the third line data at the same time, cache preceding 2 in ram
Row data read out preceding 2 row data and newest the third line data；When writing fourth line, newest data line is exactly at this time
Four rows, ram3 will be written in fourth line data at the same time, the preceding 3 row data of caching in ram, by preceding 3 row data and the newest 4th
Row data are read out, and so on, a line ends processing next line, reads out in the window for being sent into the next stage and calculates.
The matching cost counting circuit structure based on Census algorithm further comprises: window processing module, including by
The left image processing module and right image processing module of window array composition and corresponding shifting cache module, alignment processing
Pixel value in left image cache module and right image cache module obtains new Bit String output；
In some embodiments, left image processing module and right image processing module window array having the same, the window
Array is built by shift register, wherein needing shift register quantity is window width, and shift unit storage depth is
Window height.
In some embodiments, which is window width × window height arrangement, and window width and window height are
Identical or different odd number.Also, the arbitrary access that in embodiment, window height value is equal in left images cache module is deposited
Reservoir, that is, ram quantitative value adds 1.
In some embodiments, the most central point of window array is window center, and the value of storage is center pixel value, with window
Remaining each pixel value of display storage relatively obtains new Bit String output.
Based on above embodiments, Fig. 4 gives the circuit structure diagram of left image window processing module, and the window of the design is big
Small is 5x5, specifies every 4 clock cycle to complete a window and compares, the most central point of window is the position of center pixel, is used for
It comparing with the value of other non-central pixels, the point value of the design being greater than equal to center pixel is 1, otherwise,
As 0, by left-to-right, the Bit String of a 24-bit can be formed from top to bottom, and processing the first row pixel only needs preceding 3 row picture
Prime number evidence, the second row of processing need preceding 4 row data, and processing the third line to countdown line 3 pixel needs 5 row data, second from the bottom
Row needs last 4 row data, and last line needs last three rows data.
In some embodiments, right image processing module increases by an offset buffer on the basis of window processing module, should
Buffer exports after caching to the output Bit String of window array in right image processing module.
Fig. 5 is the circuit structure diagram of right image window processing module provided in this embodiment, with Fig. 4 structure having the same
Window, unlike the result of window calculation of Fig. 5 can first handle and the Bit String of buffer some amount is to offset buffer
In, the quantity of caching is exactly the search parallax during our actual match, and the parallax of the design is set as 79, calculates last
Left image window processing module starts to calculate first Bit String when a Bit String, finally exports left and right image calculated result
To next module.The part that parallax 0 arrives parallax 3 is eliminated in actual use, also, in 55 to 79 section of parallax, removes institute
There is even number parallax, leave odd number parallax point Bit String, as a result disparity correspondence is total 64, and the quantity of offset buffer is equal to parallax
Coupling number 64.
It is provided in an embodiment of the present invention should matching cost counting circuit structure based on Census algorithm further include:
Computing module, including exclusive or processing module and counting processing module, wherein exclusive or processing modules implement is to left image processing module
Output Bit String with right image processing module is specifying the step-by-step exclusive or in the period, and exports exclusive or result to counting processing mould
Block, the counting processing module seek corresponding Hamming distance within the specified period, i.e., initial cost and export；
In the present embodiment, Fig. 6 is bonded the present invention as processing module is counted as exclusive or processing module and Fig. 7 jointly
In counting module, wherein Fig. 6 give calculate the Hamming distance first step step-by-step XOR circuit structure chart.From last rank
The left and right image of section be computed after output, left image is computed a 24-bit Bit String of output and successively passes through with right image
64 24-bit Bit Strings for calculating output carry out step-by-step xor operation, and to complete within 4 specified periods.As schemed,
First clock cycle in 4 clock cycle completes the exclusive or behaviour of rgt_str0_o to rgt_str15_o and 1ft_str_o
Make, second period completes the xor operation of rgt_str16_o to rgt_str31_o and lft_str_o, and the third period completes
The xor operation of rgt_str32_o to rgt_str47_o and lft_str_o, the 4th period complete rgt_str48_o to rgt_
Result just can be given to str0_o in xor operation of every completion by the xor operation of str63_o and lft_str_o, selector
It is exported to str15_0, each period completes the processing of 16 data, thus completes left and right image within 4 clock cycle
The step-by-step xor operation of the 2 system Bit String of 24-bit exported after the calculating of window processing module.It is obtained in 4 periods
16 output results are input to next module by 64 new 24-bit2 system Bit Strings, each period.
Fig. 7 gives the circuit structure diagram for seeking Hamming distance.Using 4 level production lines, each period completes level-one flowing water
Line operation carries out additional calculation, will be 1 in the 2 system Bit Strings of 16 24-bit from step-by-step exclusive or module in every 4 periods
Number to calculate to obtain 16 big bit wide be 5,2 system Bit Strings of the size between 0 to 24 continuously perform 4 times in this way
Operation, just obtained 64 Hamming distances of total 64 2 system numbers of 24-bit from step-by-step exclusive or module.
It is provided in an embodiment of the present invention to be somebody's turn to do the matching cost counting circuit structure based on Census algorithm further include: optimization mould
Block is made of comparator and execution module, is realized and is optimized within the specified period to the Bit String digit of initial cost；
In the present embodiment, Fig. 8 is initial cost optimization electrical block diagram.Just to the Hamming distance from last module
It is the initial cost that we need, the optimization of 16 initial costs is completed within 4 specified clock cycle, by judging its
Size is input in corresponding execution module, to then cost is become present 3-bit by original 5-bit compression truncation
Output carries out such operation 4 times, obtains new initial cost after 64 optimizations, further decreases resource consumption.
The matching cost counting circuit structure based on Census algorithm provided in an embodiment of the present invention finally includes: output
Module is made of register module and splicing module, and the Bit String after optimization is stored in different registers by the period, then sharp
The Bit String in different registers is combined with splicing module, obtains final optimization data information.
Fig. 9 is the initial cost splicing output circuit structure schematic diagram under all parallaxes.The a cycle in 4 periods will
First group of 16 initial cost data of input are stored in the register of first group of 16 × 3bit；Second period is by first group of deposit
The data value of device is assigned to the register of second group of 16 × 3bit, while newest data are stored in first group of register；Then
Data in second group of register are assigned to third group by the third period, while the value of first group of register is assigned to second group,
Newest one group of value is assigned to first group of register again；The last one period is by one group of new data and 3 groups of front register
In data sequentially splice output, complete entire design to this.
It is designed based on foregoing circuit, another embodiment of the present invention provides should be based on the matching cost calculating of Census algorithm
The working method of circuit structure is shooting to obtain left image and right image as original by the left camera and right camera of binocular camera
Further comprise 3 stages under the premise of image:
It is the image buffer storage stage first, the pixel value of left image and right image is spaced and the period is specified to respectively enter left image
Cache module and right image cache module are cached；
In the present embodiment, in the image buffer storage stage, realizes and the pixel value of original left and right gray level image is cached, use ram
Image data from DDR is stored, specifies and a pixel is inputted to the specified of specified ram using every 4 clock cycle
Address, when reading data, every 4 periods complete the once reading to one group of data.
Followed by the window calculation stage, the data information from left image cache module and right image cache module respectively into
Enter left image window processing module and right image window processing module to handle and export within the specified period；
In some embodiments, which includes:
To be removed in window array the pixel value of remaining each window storage other than center pixel value respectively with imago in this
Element value carries out size comparison, and number of comparisons indicates with i, i=window width × window height -1, as a result obtain that bit wide is i 2 into
Bit String processed；
Again using left image as target figure, right image is used as with reference to figure, is searched for from left to right；
Left image obtains the 2 system Bit Strings that a bit wide is i by window calculation later, and right image first makees n times window
It calculates, the Bit String obtained every time is cached, obtain the 2 system Bit Strings that n bit wide is i；
Finally by right image through handling the 2 system Bit Strings that n obtained bit wide is i and left image is obtained through processing 1
A bit wide is that the 2 system Bit Strings of i are output to that initial cost is sought and the optimizing phase is calculated and optimized.
In the present embodiment, in the window calculation stage, window processing is carried out to left images, window width and window height are big
Small is odd number, in the present embodiment, is 5 × 5 window array, and every 4 clock cycle is specified to receive one group of number from ram
According to, data in window are started to process when window is filled for the first time after meeting the requirements, the mainly data in window compare,
The most central point of window becomes window center and pixel center point, and the processing of a window, Mei Gezhou are completed in 4 periods
Phase exports one group of data, and 4 periods export one group of complete data and enter next stage, and specific calculating process is in above-mentioned implementation
Has embodiment in example, this will not be repeated here.
It is finally that initial cost is sought and optimizing phase, the data obtained through window processing module enter computing module and referring to
Step-by-step exclusive or is completed in fixed cycle, initial cost is then sought in specified period, realizes initial generation subsequently into optimization module
The Bit String digit of valence optimizes, and finally combines output by output module.
In some embodiments, which includes:
Input first by the output in window calculation stage as this stage, by left image through handling an obtained bit wide
For i 2 system Bit Strings and right image handled 2 system Bit Strings that obtained n bit wide is i in computing module respectively into
Row step-by-step xor operation finds out the 2 system Bit Strings that n new bit wides are i；
Then Hamming distance is calculated according to the 2 system Bit Strings that new bit wide is i；
Compression truncation optimization finally is carried out to Hamming distance in optimization module, obtains initial cost.
In the present embodiment, the phase III carries out cost calculating and optimization, firstly, finding out Hamming distance i.e. within 4 periods
Then initial cost carries out initial cost optimization, last initial cost splicing output, specific calculating and optimization method are above-mentioned
It is embodied in embodiment, this will not be repeated here.
Matching cost counting circuit structure and its working method provided in an embodiment of the present invention based on Census algorithm, it is whole
A design is all inputted using every 4 clock cycle, handles and exports a data.Entire Census hardware circuit design process
It mainly include 3 stages: the caching of original left images；Window interior processing is carried out to left images；Initial cost seek and
Optimization.Each stage successively carries out, input of the output in upper stage as the next stage.In embodiment provided by the invention, it is based on
The input of the matching cost counting circuit of Census algorithm is the pixel value of gray level image, and bit wide is 8-bit, every 4 clock weeks
Phase inputs a pixel value and does single treatment to a pixel value simultaneously, being cached i.e. to image pixel including the first stage
Ram is written；Second stage reads pixel to the window of specified size slave ram, handles the pixel from ram in window；The
It is triphasic to seek Hamming distance and initial cost optimization, finally export.The present invention has used the operations such as addition and subtraction and exclusive or, real
Existing image and video data conversion process are simple, can preferably control resource consumption.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Anyone skilled in the art in the technical scope that the embodiment of the present invention discloses, the variation that can readily occur in or
Replacement, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection of claim
Subject to range.
Claims (10)
1. a kind of matching cost counting circuit structure based on Census algorithm, which is characterized in that the circuit structure realizes
Matching cost based on Census algorithm calculates, comprising:
Cache module, including the left image cache module and right image cache module being made of random access memory, realization pair
The caching of the pixel value for the left images that the left and right camera of binocular camera is shot；
Window processing module, including the left image processing module and right image processing module that are made of window array and correspondence
Shifting cache module, the pixel value in left image cache module and right image cache module described in alignment processing obtains new ratio
Spy's string output；
Computing module, including exclusive or processing module and counting processing module, the exclusive or processing modules implement is to left image processing
Step-by-step exclusive or of the output Bit String of module and right image processing module within the specified period, and export at exclusive or result to counting
Module is managed, the counting processing module is sought corresponding Hamming distance within the specified period and exported, i.e. initial cost；
Optimization module, including comparator and execution module are realized within the specified period to the Bit String of the initial cost
Digit optimization；
Bit String after the optimization is stored in different deposits by the period by output module, including register module and splicing module
In device, then the Bit String in the different registers is combined using splicing module, it is first after obtaining final optimization
Beginning worth of data information.
2. the matching cost counting circuit structure according to claim 1 based on Census algorithm, which is characterized in that described
Left image cache module is identical with right image cache module structure, including the random access memory of the specified quantity connected side by side
Device, the specified quantity value are the even number not less than 2.
3. according to claim 1 or 2 any matching cost counting circuit structures based on Census algorithm, feature exist
In the random access memory depth in the left image cache module is less than the random access memory in right image cache module
The depth of device.
4. the matching cost counting circuit structure according to claim 1 based on Census algorithm, which is characterized in that described
Left image processing module and right image processing module window array having the same, the window array are built by shift register
It forms.
5. the matching cost counting circuit structure according to claim 4 based on Census algorithm, which is characterized in that described
Window array is window width × window height arrangement, and the window width and window height are identical or different odd number.
6. according to claim 1 or 4 or 5 any matching cost counting circuit structures based on Census algorithm, special
Sign is that the most central point of the window array is window center, and the value of storage is center pixel value, with window array storage
Remaining each pixel value relatively obtains new Bit String output.
7. according to claim 1 or 4 any matching cost counting circuit structures based on Census algorithm, feature exist
In the right image processing module increases by an offset buffer on the basis of window processing module, and the buffer is to right figure
It is exported after being cached as the output Bit String of window array in processing module.
8. a kind of working method of the matching cost counting circuit structure based on Census algorithm characterized by comprising
Original image is obtained, the left camera and right camera of binocular camera shoot to obtain left image and right image；
The period is specified to respectively enter left image cache module and the right side in the pixel value interval of image buffer storage, the left image and right image
Image buffer storage module is cached；
Window calculation, the data information from left image cache module and right image cache module respectively enter at left image window
Reason module and right image window processing module were handled and are exported within the specified period；
Initial cost is sought and is optimized, the data obtained through window processing module enter computing module completed within the specified period by
Position exclusive or, then seeks initial cost in specified period, and the Bit String digit of initial cost is realized subsequently into optimization module
Optimization, finally combines output by output module.
9. the working method of the matching cost counting circuit structure according to claim 8 based on Census algorithm, special
Sign is that the window calculation includes:
To be removed in window array the pixel value of remaining each window storage other than center pixel value respectively with the center pixel
Value carries out size comparison, and number of comparisons is indicated with i, i=window width × window height -1, as a result obtains 2 systems that bit wide is i
Bit String；
Using left image as target figure, right image is used as with reference to figure, is searched for from left to right；
Left image obtains the 2 system Bit Strings that a bit wide is i by window calculation, and right image first does n times window calculation, will be every
Secondary obtained Bit String is cached, and the 2 system Bit Strings that n bit wide is i are obtained；
It is i that right image, which is handled the 2 system Bit Strings that n obtained bit wide is i and 1 bit wide that left image is obtained through processing,
2 system Bit Strings be output to that initial cost is sought and the optimizing phase is calculated and optimized.
10. the working method of the matching cost counting circuit structure according to claim 9 based on Census algorithm, special
Sign is, the initial cost seek and optimize include:
Input of the output in window calculation stage as this stage, by left image through handling 2 systems that an obtained bit wide is i
Bit String and right image are handled n obtained bit wide and carry out step-by-step exclusive or respectively in computing module for the 2 system Bit Strings of i
Operation finds out the 2 system Bit Strings that n new bit wides are i；
Hamming distance is calculated according to the 2 system Bit Strings that new bit wide is i；
Compression truncation optimization is carried out to Hamming distance in optimization module, obtains initial cost.
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