CN109743158A - For realizing the system and high-performance SM3 algorithm implementation method of high-performance SM3 algorithm - Google Patents
For realizing the system and high-performance SM3 algorithm implementation method of high-performance SM3 algorithm Download PDFInfo
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Abstract
The invention discloses a kind of system for realizing high-performance SM3 algorithm and high-performance SM3 algorithm implementation methods, the system includes configuration register, interface bus device, data administrator and encryption kernel, and the valid data length and source address information of data to be compressed are configured by configuration register；Interface bus device receives the configuration information that configuration register is sent, and selects data to be compressed, and be sent in data administrator；The data that data administrator receiving interface bus unit is sent, according to the configuration information that configuration register is sent, judge whether finishing touch data need to supplement data at two, if not needing, then data are supplemented into a data, and the data after complement is operated cache；If desired, then data are supplemented into two data, and the data after complement is operated cache；Encryption kernel reads data to be compressed from data administrator and is iterated compression processing.
Description
Technical field
The present invention relates to data processing field, have be related to it is a kind of promoted SM3 algorithm processing performance for realizing high property
The system and high-performance SM3 algorithm implementation method of energy SM3 algorithm.
Background technique
SM3 algorithm is mainly used for digital signature and verifying, message authentication code generation and verifying, generating random number etc..
Existing SM3 algorithm is essentially all to be grasped to do data input with CPU, and CPU reads back data from storage, then
Again encryption kernel is written in the data read back by CPU, and read-write is each primary, and CPU needs to monitor SM3 state, waits next stroke count
According to write-in.It will increase unnecessary data processing time in this way, and CPU can be occupied.Also be by the way of supple-settlement
SM3 algorithm is realized with soft code, is dealt with so more slowly, the hardware process speed that is far from is fast.
In conclusion the problem of how promoting SM3 algorithm processing performance at present, still shortage effective solution scheme.
Summary of the invention
In order to overcome the above-mentioned deficiencies of the prior art, it is for realizing high-performance SM3 algorithm present disclose provides a kind of
System and high-performance SM3 algorithm implementation method effectively promote SM3 compression algorithm process performance, reduce CPU and participate in data processing
Time reduces data and inputs the unnecessary waiting time.
Technical solution used by the disclosure is:
A kind of system for realizing high-performance SM3 algorithm, the system include:
Configuration register, for configuring the valid data length and source address information of data to be compressed, and by the letter of configuration
Breath is sent to interface bus device and data administrator；The encryption kernel data that feed back to that treated are also received, and are delayed
It deposits；
Interface bus device is chosen from corresponding storage address for receiving the configuration information of configuration register transmission
Data to be compressed out, and be sent in data administrator；
Data administrator, for the data that receiving interface bus unit is sent, the configuration sent according to configuration register
Information, judges whether finishing touch data to be compressed require supplementation with into two data, if not needing, finishing touch is to be compressed
Data are supplemented into a data, and the data after complement is operated cache；If desired, then data are supplemented into two stroke counts
According to, and the data after complement is operated cache；
Encryption kernel is iterated data using SM3 algorithm for reading data to be compressed from data administrator
Compression processing, will treated data feedback to configuration register；And it generates corresponding interrupt and is sent to CPU.
Further, the interface bus device includes sequentially connected interface, bus and memory, the interface difference
It is connect with configuration register, data administrator, the configuration information that configuration register is sent is received, through bus from memory
The data to be compressed that corresponding address is stored are taken out, and the data to be compressed that will acquire are sent in data administrator.
Further, the data administrator includes FIFO, complement controller and buffer, and the FIFO connects
The data that mouth is sent, and cached, judge whether data to be compressed are finishing touch data to be compressed, if it is not, then
Data to be compressed are transferred directly to buffer；If so, judging finishing touch according to the configuration information that configuration register is sent
Whether data to be compressed require supplementation with into two data, if not needing, by finishing touch data supplement to be compressed at a stroke count
According to storing data into buffer again；If desired, then finishing touch data to be compressed are supplemented into two data again by data
It stores in buffer；The complement controller carries out complement operation to finishing touch data to be compressed, and after complement is operated
Data store into buffer.
A kind of high-performance SM3 algorithm implementation method, this method are based on as described above for realizing high-performance SM3 algorithm
System realize, method includes the following steps: configuring the valid data length and source address of data to be compressed；
Data to be compressed are read from memory according to the source address of configuration, and are cached；
Judge whether it is finishing touch data to be compressed；
If it is not, then directly treating compressed data is iterated compression processing；
If so, judge whether finishing touch data to be compressed require supplementation with into two data, it, will be last if not needing
One data supplement to be compressed is iterated compression processing at a data, and to the data after complement operation, if desired, then will
Finishing touch data supplement to be compressed is iterated compression processing at two data, and to the data after complement operation.
Further, described the step of carrying out complement operation to finishing touch data to be compressed, includes:
According to the valid data length of configuration, the valid data of finishing touch data to be compressed are taken out, according to valid data
Length generate corresponding supplementary data, then valid data are written in encryption kernel together with supplementary data and are iterated compression
Processing.
Further, the production method of the supplementary data are as follows:
If the valid data length of finishing touch data to be compressed mends 1, finally less than 448 bits after valid data
64 bits with effect data length, central filler several zero；
It is then replaced if the valid data length of finishing touch data to be compressed is more than or equal to 448 bits less than 512 bits
At two data, 1 is mended after the first stroke data valid bit, and is mended 0 and gathered enough 512 bits；Second data is by 448 bits 0 and most
The valid data length composition of 64 bits afterwards；
If the valid data length of finishing touch data to be compressed is equal to 512 bits, add again after the valid data
The valid data effective length of upper 1 bit 1,447 bits of bit 0 and 64.
Further, during Iteration Contraction processing, interface bus device will be next time to the data of Iteration Contraction
It is deposited into the FIFO buffer of data administrator；The buffer of data administrator buffer from FIFO takes out 16
Digital data, as data to be compressed next time, to this current data compression after, data to be compressed will be written to next time
In encryption kernel.
Further, described to treat the step of compressed data is iterated compression processing and include:
The data to be compressed sent using 32 bit register accessed cache devices, and displacement operation is carried out, obtain multiple 32
The extension word Wj of bit；
Dynamic message is calculated using register and extends word Wj '；
Wheel number is calculated using controller.
Further, further includes:
After finishing touch compressed data has been handled, by treated, data are stored into the buffer of configuration register.
Through the above technical solutions, the beneficial effect of the disclosure is:
(1) disclosure is directly come out the reading data that memory stores by interface, reduces CPU operation, can be effective
Promotion SM3 Iteration Contraction handle the performance of larger batch data；
(2) disclosure carries out complement operation to data by the complement controller in data administrator, according to register
The valid data length of middle configuration, takes out the valid data of finishing touch, generates corresponding supplementary data according to valid data, then
This part valid data is written in encryption kernel together with filling data, CPU can be effectively reduced and participate in data manipulation processing,
The time is saved for encryption kernel；
(3) disclosure mitigates CPU burden by configuration register configuration data length and source address information, primary to configure
After good, it is only necessary to which processing interruption is all right, does not need monitoring encryption nuclear state.
Detailed description of the invention
The Figure of description for constituting a part of this disclosure is used to provide further understanding of the disclosure, and the disclosure is shown
Meaning property embodiment and its explanation do not constitute the improper restriction to the disclosure for explaining the application.
Fig. 1 is for realizing the structure chart of the system of high-performance SM3 algorithm；
Fig. 2 is the flow chart of high-performance SM3 algorithm implementation method.
Specific embodiment
The disclosure is described further with embodiment with reference to the accompanying drawing.
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the disclosure.Unless another
It indicates, all technical and scientific terms that the disclosure uses have logical with disclosure person of an ordinary skill in the technical field
The identical meanings understood.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
One or more embodiments provide a kind of system for realizing high-performance SM3 algorithm, effectively promote SM3 algorithm
Compression processing performance reduces the time that CPU participates in data processing, reduces data and inputs the unnecessary waiting time.
As shown in Figure 1, the system includes configuration register, interface bus device, data administrator and encryption kernel, it is described
Encryption kernel is connect with configuration register, data administrator respectively, the configuration register respectively with interface bus device, data
Managing device connection, the interface bus device are also connect with data administrator.
Specifically, the configuration register is used for configuration data length and source address information, the information of configuration is sent to
Interface bus device and data administrator；The data that encryption kernel is fed back to also are received, and are cached.
The interface bus device, for receive configuration register transmission configuration information, from corresponding address choose to
The data of compression, are sent in data administrator.
In the present embodiment, the interface bus device includes sequentially connected interface, bus and memory, the interface
It is connect respectively with configuration register, data administrator, the configuration information that configuration register is sent is received, by bus from storage
The data to be compressed for storing corresponding address in device are taken out, and the data to be compressed received are sent data pipe by interface
It manages in device.
The present embodiment is directly come out the reading data that memory stores by interface, reduces CPU operation.
The data administrator and is stored for the data that receiving interface is sent, judge data to be compressed whether be
Finishing touch data to be compressed, if it is not, data to be compressed are then transferred directly to encryption kernel；If so, being posted according to configuration
The configuration information that storage is sent, judges whether finishing touch data to be compressed require supplementation with into two data, will if not needing
Finishing touch is supplemented into a data, and the data after complement is operated cache；If desired, then by finishing touch supplement at
Two data, and the data after complement is operated cache.
In the present embodiment, the data administrator includes FIFO, complement controller and buffer, FIFO buffer
The data that receiving interface is sent, and cached；Judge whether data to be compressed are finishing touch data to be compressed, if not
It is that data to be compressed are then transferred directly to buffer；If so, judgement is most according to the configuration information that configuration register is sent
Whether latter pen data to be compressed require supplementation with into two data, if not needing, finishing touch data to be compressed are sent to benefit
Number controller, complement controller is by finishing touch data to be compressed supplement at a data, and the data after complement is operated are deposited
It stores up in buffer；If desired, finishing touch data to be compressed are sent to complement controller, complement controller is by finishing touch
Data to be compressed supplement is at two data, and the data after complement is operated are stored into buffer.
The present embodiment carries out complement operation to data by the complement controller in data administrator, according in register
The valid data length of configuration takes out the valid data of finishing touch data to be compressed, generates phase according to the length of valid data
The supplementary data answered, then this part valid data is written in encryption kernel together with supplementary data.
The encryption kernel carries out data using SM3 algorithm for reading data from the buffer of data administrator
Iteration Contraction processing, will treated data feedback to configuration register；And generate corresponding interrupt and be sent to CPU, by CPU
Reason.
During encryption kernel carries out compression processing, interface will can be stored in the data of Iteration Contraction next time in advance
In FIFO buffer into data administrator；It, can be from FIFO when a data enter encryption kernel and are iterated compression
Buffer takes out 16 words, and the data that the next record that gathered in advance needs wait this current data compression to terminate, immediately will be next
Pen is written in encryption kernel, can be controlled each processing time in 65 CLOCK, can be saved under reading so in this way
One consumed time.
Resource can make full use of using iterative calculation using encryption IP kernel in the present embodiment, reduce the wasting of resources, it can
The effective performance for promoting SM3 Iteration Contraction and handling larger batch data mitigates CPU burden, after primary configuration is good, it is only necessary to locate
Reason interruption is all right, does not need monitoring encryption nuclear state.
One or more embodiments provide a kind of high-performance SM3 algorithm implementation method, effectively promote the processing of SM3 compression algorithm
Performance reduces the time that CPU participates in data processing, reduces data and inputs the unnecessary waiting time.
As shown in Fig. 2, the high-performance SM3 algorithm implementation method the following steps are included:
S101 configures the valid data length and source address of data to be compressed.
In the present embodiment, using configuration register configuration data length and source address information, the information of configuration is sent
To interface bus device and data administrator.
S102 reads data to be compressed from memory according to the source address of data to be compressed, and caches.
In the present embodiment, the source address for the data to be compressed that interface configuration register is sent, by bus from depositing
The data to be compressed for storing corresponding address in reservoir are taken out, and send data administrator for data to be compressed
In.
S103 judges whether it is finishing touch data to be compressed, if it is not, then treating compressed data is iterated compression
Processing, by treated, data are stored into the buffer of configuration register；If so, judging that finishing touch data to be compressed are
It is no to require supplementation with into two data.
In the present embodiment, if the data to be compressed of data administrator storage are not finishing touch data, data pipe
Reason device directly enters data into encryption kernel；If finishing touch data to be compressed then judge the finishing touch data
Whether two data are required supplementation with into.
S104, if not needing, according to the valid data length configured in register, then the number to be compressed to finishing touch
According to supplement at a data；If desired, then according to the valid data length configured in register, then to be compressed to finishing touch
Data are supplemented into two data.
S105 is iterated compression processing to the finishing touch data to be compressed after complement operation, will treated data
It stores in the buffer of configuration register.
During encryption kernel carries out compression processing, the data to Iteration Contraction can be deposited into data in advance by interface
In FIFO buffer in managing device；When a data enter encryption kernel and are iterated compression, can from FIFO buffer
16 words are taken out, the data that the next record that gathered in advance needs wait this current data compression to terminate, next record is written immediately
Into encryption kernel, each processing time can be controlled in this way in 65 CLOCK, can save read next record institute in this way
The time of consumption.
In the step S103, treating the step of compressed data is iterated compression processing includes:
S103-1, the data to be compressed that encryption kernel inside is sent using 16 32 bit registers come accessed cache device, and
Displacement operation is carried out, the extension word of 16 32 bits is obtained.
In the present embodiment, 16 32 bit registers are inside encryption kernel as clock does shifting function are as follows:
Data0 ← data1 ← data2 ... data14 ← data15 (Wj in corresponding encryption kernel).
S103-2, encryption kernel inside calculate dynamic message using data0 and data4 register and extend word Wj '.
S103-3, encryption kernel inside deposit the extension word of each round generation using 8 individual registers.
S103-4, encryption kernel inside calculate wheel number using controller, to data compression knot since valid data input
Beam supply and demand 64 is taken turns.
S103-5, after valid data input, encryption kernel sends commencing signal to buffer, and buffer stores under 16
Primary data to be compressed wait this current data compression to terminate, are immediately written to 16 data next time to be compressed
In encryption kernel, it is ensured that the continuity of data input.
S103-6, finishing touch data input in encryption kernel, while buffer can send an end signal to encryption kernel,
Encryption kernel exports valid data into configuration register after compression.
In the present embodiment, the data to be compressed to finishing touch carry out the step of complement operation and include:
(1) if the valid data length of finishing touch data to be compressed is less than 448bit, 1 is mended after valid data, most
For 64bit with effect data length, (512-64- data effective length -1) a zero is filled out in centre afterwards；
(2) if the valid data length of finishing touch data to be compressed is more than or equal to 448bit, it is less than 512bit, needs to replace
At two data, 1 is mended after significance bit, 0 is then mended and gathers enough 512bit, second is 448bit0, the data length of 64bit；
(3) it if the valid data length of finishing touch data to be compressed is equal to 512bit, needs again to add one after this
1bit1,447bit0,64bit data effective length.
The high-performance SM3 algorithm implementation method that the present embodiment proposes can effectively reduce CPU and participate in data manipulation processing,
The time is saved for encryption kernel, can effectively promote the performance that SM3 Iteration Contraction handles larger batch data, mitigates CPU burden,
After primary configuration is good, it is only necessary to which processing interruption is all right, does not need monitoring encryption nuclear state.
One or more embodiments provide a kind of specific embodiment of high-performance SM3 algorithm implementation method.
In the embodiment, data to be encrypted are 0,110 0,001 0,110 0,010 0,110 0,011 0001, data length
For 28bit, the effective length for needing to configure data is 7Byte.But since bus bit wide is 32bit, data are actually written
Data in the FIFO buffer of managing device are 8Byte.Data are read out from FIFO buffer, according to configuration register
Configured valid data length intercepts the valid data in the last character, is combined into valid data, then valid data again
1, central filler 419 (512-28-1-64) bit0 are mended later, and last 64bit inserts data effective length 28bit, obtains final
512bit data are as follows: 0,110 0,001 0,110 0,010 0,110 0,011 0001 10..00 (419bit0) 00 ... 11100
(64bit)。
It can be seen from the above description that above-mentioned one or more embodiments realize following technical effect:
(1) disclosure is directly come out the reading data that memory stores by interface, reduces CPU operation, can be effective
Promotion SM3 Iteration Contraction handle the performance of larger batch data；
(2) disclosure carries out complement operation to data by the complement controller in data administrator, according to register
The valid data length of middle configuration, takes out the valid data of finishing touch, generates corresponding supplementary data according to valid data, then
This part valid data is written in encryption kernel together with filling data, CPU can be effectively reduced and participate in data manipulation processing,
The time is saved for encryption kernel；
(3) disclosure mitigates CPU burden by configuration register configuration data length and source address information, primary to configure
After good, it is only necessary to which processing interruption is all right, does not need monitoring encryption nuclear state.
Although above-mentioned be described in conjunction with specific embodiment of the attached drawing to the disclosure, model not is protected to the disclosure
The limitation enclosed, those skilled in the art should understand that, on the basis of the technical solution of the disclosure, those skilled in the art are not
Need to make the creative labor the various modifications or changes that can be made still within the protection scope of the disclosure.
Claims (9)
1. a kind of system for realizing high-performance SM3 algorithm, characterized in that the system includes:
Configuration register is sent out for configuring the valid data length and source address information of data to be compressed, and by the information of configuration
Give interface bus device and data administrator；The encryption kernel data that feed back to that treated are also received, and are cached；
Interface bus device, for receive configuration register transmission configuration information, selected from corresponding storage address to
The data of compression, and be sent in data administrator；
Data administrator, for receiving interface bus unit send data, according to configuration register send configuration information,
Judge whether finishing touch data to be compressed need to supplement data at two, if not needing, by finishing touch number to be compressed
Data according to supplement at a data, and after complement is operated cache；If desired, then finishing touch data to be compressed are mended
Two data are filled into, and the data after complement is operated cache；
Encryption kernel is iterated compression to data using SM3 algorithm for reading data to be compressed from data administrator
Processing, will treated data feedback to configuration register；And it generates corresponding interrupt and is sent to CPU.
2. the system according to claim 1 for realizing high-performance SM3 algorithm, characterized in that the interface bus dress
It sets including sequentially connected interface, bus and memory, the interface is connect with configuration register, data administrator respectively,
The configuration information that configuration register is sent is received, is taken by the data to be compressed that bus stores corresponding address from memory
Out, and the data to be compressed that will acquire are sent in data administrator.
3. the system according to claim 1 for realizing high-performance SM3 algorithm, characterized in that the data management dress
The data sent including FIFO, complement controller and buffer, the FIFO receiving interface are set, and are cached, are judged wait press
Whether the data of contracting are finishing touch data to be compressed, if it is not, data to be compressed are then transferred directly to buffer；If
Be, then according to configuration register send configuration information, judge finishing touch data to be compressed whether need by data supplement at
Two, if not needing, finishing touch data to be compressed is sent to complement controller and supplement data at a data, then are sent out
It is sent in buffer；If desired, then finishing touch data to be compressed complement controller is sent to supplement data at two stroke counts
According to re-sending in buffer；The complement controller carries out complement operation to finishing touch data to be compressed, and complement is grasped
Data after work are stored into buffer.
4. a kind of high-performance SM3 algorithm implementation method, this method is based on of any of claims 1-3 for realizing height
What the system of performance SM3 algorithm was realized, characterized in that method includes the following steps:
Configure the valid data length and source address of data to be compressed；
Data to be compressed are read from memory according to the source address of configuration, and are cached；
Judge whether it is finishing touch data to be compressed；
If it is not, then directly treating compressed data is iterated compression processing；
If so, judging whether finishing touch data to be compressed need to supplement data at two, if not needing, by last
Pen data supplement to be compressed is iterated compression processing at a data, and to the data after complement operation；It if desired, then will most
Latter pen data supplement to be compressed is iterated compression processing at two data, and to the data after complement operation.
5. high-performance SM3 algorithm implementation method according to claim 4, characterized in that described to be compressed to finishing touch
Data carry out complement operation the step of include:
According to the valid data length of configuration, the valid data of finishing touch data to be compressed are taken out, according to the length of valid data
Degree generates corresponding supplementary data, then valid data are written in encryption kernel together with supplementary data and are iterated at compression
Reason.
6. high-performance SM3 algorithm implementation method according to claim 5, characterized in that the generation side of the supplementary data
Method are as follows:
If the valid data length of finishing touch data to be compressed mends 1, last 64 ratio less than 448 bits after valid data
Feature valid data length, central filler several zero；
If the valid data length of finishing touch data to be compressed is more than or equal to 448 bits, it is less than 512bit, is then replaced as two
Data mend 1 after the first stroke data valid bit, and mend 0 and gather enough 512 bits；Second data is by 448 bits 0 and last 64 ratio
Special valid data length composition；
If the valid data length of finishing touch data to be compressed is equal to 512 bits, one is added after the valid data
The valid data effective length of 1 bit 1 of pen, 447 bits of bit 0 and 64.
7. high-performance SM3 algorithm implementation method according to claim 4, characterized in that in the process of Iteration Contraction processing
In, interface bus device will be deposited into the FIFO buffer of data administrator to the data of Iteration Contraction next time；Data
The buffer of managing device buffer from FIFO takes out 16 digital datas, as data to be compressed next time, to this current pen
After data compression, data to be compressed it will be written in encryption kernel next time.
8. high-performance SM3 algorithm implementation method according to claim 4, characterized in that described to treat compressed data progress
Iteration Contraction processing the step of include:
The data to be compressed sent using 32 bit register accessed cache devices, and displacement operation is carried out, obtain multiple 32 bits
Extension word Wj；
Dynamic message is calculated using register and extends word Wj '；
Wheel number is calculated using controller.
9. high-performance SM3 algorithm implementation method according to claim 4, characterized in that further include:
After finishing touch compressed data has been handled, by treated, data are stored into the buffer of configuration register.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610105A (en) * | 2019-09-25 | 2019-12-24 | 郑州轻工业学院 | Secret sharing-based authentication method for three-dimensional model file in cloud environment |
| CN112217646A (en) * | 2020-10-13 | 2021-01-12 | 天津津航计算技术研究所 | Device and method for realizing SM3 password hash algorithm |
| CN112422489A (en) * | 2020-03-11 | 2021-02-26 | 深圳华锐金融技术股份有限公司 | Service data transmission method, device, computer equipment and storage medium |
-
2019
- 2019-01-04 CN CN201910007811.7A patent/CN109743158A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610105A (en) * | 2019-09-25 | 2019-12-24 | 郑州轻工业学院 | Secret sharing-based authentication method for three-dimensional model file in cloud environment |
| CN110610105B (en) * | 2019-09-25 | 2020-07-24 | 郑州轻工业学院 | Secret sharing-based authentication method for three-dimensional model file in cloud environment |
| CN112422489A (en) * | 2020-03-11 | 2021-02-26 | 深圳华锐金融技术股份有限公司 | Service data transmission method, device, computer equipment and storage medium |
| CN112422489B (en) * | 2020-03-11 | 2021-11-02 | 深圳华锐金融技术股份有限公司 | Service data transmission method, device, computer equipment and storage medium |
| CN112217646A (en) * | 2020-10-13 | 2021-01-12 | 天津津航计算技术研究所 | Device and method for realizing SM3 password hash algorithm |
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Application publication date: 20190510 |