CN109742141A - A kind of GaN base HEMT device and preparation method thereof - Google Patents
A kind of GaN base HEMT device and preparation method thereof Download PDFInfo
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Abstract
A kind of GaN base HEMT device and preparation method thereof, since the grid structure of GaN base HEMT device uses three mask plate structures (3-mask), increase by one layer of metal layer in barrier metal layer and p-GaN cap layers, grid resistance can be significantly reduced, increase the flexibility of field plate designs.So that device reduces dynamic on-off at high VDS, p-GaN layer is not influenced due to containing Al ingredient in grid metal, and when etching deposition grid metal, so its gate resistance very little, grid-control ability enhancing, to further promote the overall performance of device.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, and in particular to a kind of GaN base HEMT device and preparation method thereof.
Background technique
With the increasingly increase of efficient complete circuit for power conversion and system requirements, with low-power consumption and high speed characteristics
Power device has attracted many concerns recently.Wide bandgap semiconductor gallium nitride GaN material is big with forbidden bandwidth, critical with it to be hit
The features such as electric field is high, electron saturation velocities are high is worn, the ideal material of new generation of semiconductor power device is become.In recent years, with AI
(ln, Ga, Sc) N/GaN can be improved the safety of circuit work for the GaN base HEMT device of representative, so, GaN base HEMT device
Part becomes a current important research direction.On the one hand have benefited from extremely strong spontaneous polarization and piezoelectricity between GaN and AIGaN
Polarity effect, so that the two-dimensional electron gas (2-DEG) of high electron concentration and high electron mobility is formed between GaN/AlGaN, electricity
Son is at concentrations up to 1012-1013cm-2, electron mobility may be up to 2000cm2/V；On the other hand, AlGaN/GaN HEMT device work
Skill is simple, is suitably based on kinds of platform and is developed, and the development cycle is short, at low cost.
GaN base HEMT device is normally on device.In circuit, the power component of normally-off, also referred to as enhancement mode (e
Mode) transistor is the first choice of failsafe operation.It realizes enhancement transistor, needs to make grid region when gate voltage is 0V
Transistor is completely closed, one of method is p-type GaN (p-GaN) grid adulterated using Mg, promotes channel in the state of the equilibrium
In conduction band, to realize enhanced work.One of major processes of GaN base HEMT device are concave grid groove technology at present
With the F ion injection technology in gate electrode region.P-GaN grid HEMT can be divided into two major classes, and one kind is that Xiao Te is formed in p-GaN layer
Base contact, another kind of is grid injection transistor (Git) that p-GaN layer is formed with Ohmic contact.And ohm in p-GaN layer connects
Touching is easy to increase the leakage current of grid.P-GaN grid have big dynamic on resistance at high VDS, and due to extension p-
GaN, so that the design of field plate becomes complicated.So form Schottky contacts with p-GaN layer, to the flexible use of field plate for
It for GaN base HEMT device, is solved the problems, such as required for p-GaN HEMT device.
Summary of the invention
The present invention solves the technical problem of the p-GaN layers in GaN base HEMT device to form Schottky contacts.
According in a first aspect, provide a kind of GaN base HEMT device in a kind of embodiment, including substrate, buffer layer, GaN ditch
Channel layer, AlGaN potential barrier, P-GaN cap layers, metal layer, barrier metal layer and dielectric layer；
The buffer layer is stacked in the substrate；
The GaN channel layer is stacked on the buffer layer；
The AlGaN potential barrier is stacked on the GaN channel layer；
The P-GaN cap layers are stacked on the AlGaN potential barrier；
The metal layer is stacked on the AlGaN potential barrier；
The barrier metal layer is stacked on the metal layer；
The dielectric layer is arranged outside the P-GaN cap layers, the metal layer and the barrier metal layer, for sealing
State GaN base HEMT device.
According to second aspect, a kind of preparation method of GaN base HEMT device is provided in a kind of embodiment, comprising:
It is sequentially prepared buffer layer, GaN channel layer, AlGaN potential barrier, P-GaN cap layers and metal layer on substrate；
First medium layer is deposited on the metal layer；
First window is opened on the first medium layer, the bottom of the window is located on the metal layer；
Barrier metal layer is deposited on the first window；
Second dielectric layer is deposited on the outside of the barrier metal layer, the second dielectric layer seals the barrier metal layer.
According to a kind of GaN base HEMT device and preparation method thereof of above-described embodiment, due in barrier metal layer and p-GaN cap
One layer of metal-layer structure is increased between layer, so that the gate resistance (Rsh-metal) of GaN base HEMT device is reduced, is increased
The flexibility of field plate designs reduces dynamic on-off at high VDS.
Detailed description of the invention
Fig. 1 is a kind of the schematic diagram of the section structure of GaN base HEMT device in embodiment；
Fig. 2 is a kind of preparation technology flow chart of GaN base HEMT device in embodiment；
Fig. 3 (a)~(e) sequentially shows the preparation process flow step of the application GaN base HEMT device, in which:
(a) buffer layer, GaN channel layer, AlGaN potential barrier, P-GaN cap layers and metal layer are sequentially prepared on substrate；
(b) etching sheet metal and cap layers to barrier layer stop；
(c) in deposition of metal first medium layer；
(d) barrier metal layer is deposited on first window；
(e) second dielectric layer is deposited on the outside of barrier metal layer；
Fig. 4 is a kind of section schematic diagram of GaN base HEMT device in an embodiment；
Fig. 5 is a kind of structural schematic diagram of GaN base HEMT device in an embodiment.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.Wherein different embodiments
Middle similar component uses associated similar element numbers.In the following embodiments, many datail descriptions be in order to
The application is better understood.However, those skilled in the art can recognize without lifting an eyebrow, part of feature
It is dispensed, or can be substituted by other elements, material, method in varied situations.In some cases, this Shen
Please it is relevant it is some operation there is no in the description show or describe, this is the core in order to avoid the application by mistake
More descriptions are flooded, and to those skilled in the art, these relevant operations, which are described in detail, not to be necessary, they
Relevant operation can be completely understood according to the general technology knowledge of description and this field in specification.
It is formed respectively in addition, feature described in this description, operation or feature can combine in any suitable way
Kind embodiment.Meanwhile each step in method description or movement can also can be aobvious and easy according to those skilled in the art institute
The mode carry out sequence exchange or adjustment seen.Therefore, the various sequences in the description and the appended drawings are intended merely to clearly describe a certain
A embodiment is not meant to be necessary sequence, and wherein some sequentially must comply with unless otherwise indicated.
It is herein component institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object,
Without any sequence or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and
It is indirectly connected with (connection).
Schottky knot: schottky junction is the interface of a kind of simple metal and semiconductor, similar to PN junction, is had
Rectification characteristic.
Ohm knot: i.e. Ohmic contact, a kind of interface of simple metal and semiconductor are that abutment does not generate significantly
Additional impedance and it will not make equilibrium carrier concentration inside semiconductor that significant change occur.
MIS knot: the contact structures (Metal-insulator-semiconductor of metal-insulator semiconductor
Junction), contacted between metal and semiconductor by insulator.
HEMTs: high electron mobility transistor
CMOS: compensated semiconductor's metal-oxide semiconductor (MOS)
GaN: gallium nitride, a kind of wide bandgap semiconductor compound are the representatives of third generation semiconductor, are very suitable to high-power
And the production of microwave device
Composite anode: the metal of semiconductor devices anode and the interface of semiconductor are connect using two or more mode
Touching.
Rsh-metal: full name the metal sheet resistance of the gate metal grid metal field plate
Resistance
PVD: full name Physical Vapor Deposition, physical vapour deposition (PVD) are most common in semiconductor technology
The mode of metal deposit.
LPCVD: full name Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition are
One of the major way that high quality dielectric film deposits in semiconductor technology.
MOCVD: full name Metal-organic Chemical Vapor Deposition, metallo-organic compound chemistry
Gaseous phase deposition, a kind of novel vapour phase epitaxy growing technology to grow up on the basis of vapor phase epitaxial growth (VPE) are main to use
In the growth of the compound semiconductors such as GaN/SiC.
PEVCD: full name Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical
Vapor deposition is one of the major way that high quality dielectric film deposits in semiconductor technology, is mainly used for last part technology sheath
Deposition.
RIE: full name is Reactive Ion Etching, reactive ion etching, a kind of microelectronics dry corrosion process.
IPC: full name Inductively Coupled Plasma, plasma inductive coupling, a kind of microelectronics dry method corruption
Etching technique.
Yellow light: carrying out gluing, soft roars of laughter, exposure, development, hard baking for chips such as silicon wafers, it made to make certain figure by lithography, this
Technique is yellow light.
Lithography mask version (also known as light shield, English are Mask Reticle), abbreviation mask plate is that micro-nano technology technology is common
Photoetching process used in figure mother matrix.Mask pattern structure is formed by opaque shading film on the transparent substrate, then
Graphical information is transferred on product substrate by exposure process.Mask plate to be processed is by glass/quartz substrate, layers of chrome and light
Photoresist layer is constituted.Its graphic structure can be processed by mask-making technology and be obtained, and commonly using process equipment is write-through lithographic equipment, such as be swashed
Light direct-write lithography machine, electron beam lithography machine etc..Mask plate using very extensive, the field for being related to photoetching process require using
Mask plate, as IC (Integrated Circuit, integrated circuit), FPD (Flat Panel Display, flat-panel monitor),
PCB (Printed Circuit Boards, printed circuit board), MEMS (Micro Electro Mechanical Systems,
MEMS) etc..
In embodiments of the present invention, the grid structure of GaN base HEMT device uses three mask plate structures (3-mask), i.e., in grid
Metal layer and p-GaN cap layers increase by one layer of metal layer, and grid resistance (Rsh-metal) can be significantly reduced, increase the spirit of field plate designs
Activity, and device is made to reduce dynamic on-off at high VDS.
Embodiment one:
As shown in Figure 1, for a kind of the schematic diagram of the section structure of GaN base HEMT device in embodiment, including from the bottom up according to
Substrate, buffer layer 100, GaN channel layer 200, AlGaN potential barrier 300, P-GaN cap layers 400, the metal layer 500, grid of secondary stacking
Metal layer 700, first medium layer 600 and second dielectric layer 800.Buffer layer 100 is stacked in substrate.GaN channel layer 200 is folded
It sets on buffer layer 100.AlGaN potential barrier 300 is stacked on GaN channel layer 200.P-GaN cap layers 400 are stacked in
On AlGaN potential barrier 300.Metal layer 500 is stacked on AlGaN potential barrier 300.Barrier metal layer 700 is stacked in metal layer
On 500.Dielectric layer includes first medium layer 600 and second dielectric layer 800, is arranged in P-GaN cap layers 400,500 and of metal layer
The outside of barrier metal layer 700, for sealing GaN base HEMT device.By P-GaN cap layers between AlGaN potential barrier 300 and dielectric layer
400 keep apart.The GaN base HEMT device further includes Two-dimensional electron gas-bearing formation, is formed in the GaN channel layer and the AlGaN
The contact surface of barrier layer is biased to GaN channel layer side.Wherein, the thickness of metal layer 500 is not more than the thickness of P-GaN cap layers
Degree.Barrier metal layer 700 is made of TiN, Ni, Au, W, at least one of materials such as Pt or Pd.Dielectric layer is by SiNx、SiO2、
SiON、Al2At least one of materials such as O3 or AlN are constituted.AlGaN potential barrier 300 is by AlxGa1-xN,InxGa1-xN,
InxAl1-xN, or InxAlyGa1-x-yAt least one of materials such as N are constituted.The grid knot of GaN base HEMT device disclosed in the present application
Structure is three mask plate grid structures, including P-GaN cap layers 400, metal layer 500 and barrier metal layer 700.Wherein in barrier metal layer 700
Contain Al ingredient.
Disclosed herein as well is a kind of process flows of GaN base HEMT device manufacture, as shown in Fig. 2, being a kind of embodiment
The preparation technology flow chart of middle GaN base HEMT device, comprising:
Step 1 is sequentially prepared buffer layer, GaN channel layer, AlGaN potential barrier, P-GaN cap layers and metal on substrate
Layer.
Buffer layer, GaN channel layer, AlGaN potential barrier, P-GaN cap layers and gold are sequentially prepared as shown in Fig. 3 (a), on substrate
Belong to layer, after specifically cleaning to substrate wafer, 30nm GaN channel layer is deposited using LPCVD technique, by injecting acceptor
It is cap layers that impurity Mg, which forms p-GaN layer,.It is again metal layer with LPCVD deposition 10nm TiN layer.Wherein, the material of substrate layer 1 is N
One of type doped silicon material, gallium nitride material, sapphire material.
Step 2 deposits first medium layer on the metal layer.
As shown in Fig. 3 (b), etching sheet metal and cap layers to barrier layer stop, and are specifically selected using BCl3/SF6 wafer
The dry etching TiN layer and p-GaN layer of selecting property are until AlGaN layer stops.
It is specifically first with PECVD deposit 50nm SiO2 in deposition of metal first medium layer as shown in Fig. 3 (c)
Dielectric layer, one side protective separation area prevent 2DEG channel and the short circuit of back segment electrode metal；On the other hand, it can further be passivated
Device surface promotes device performance.
Step 3 opens first window on first medium layer, and the bottom of the window is located on metal layer.Specifically use
ICP etching mode forms gate window, and etching will carry out more accurate time control, stop at TiN metal layer.
Step 4 deposits barrier metal layer on the first window.
As shown in Fig. 3 (d), barrier metal layer is deposited on first window, specifically LPCVD is deposited again in crystal column surface
Then TiN barrier metal layer of the 20nm containing Al makes it have grid field using the dry etching TiN barrier metal layer of BCl3/SF6 selectivity
Plate effect.
Step 5 deposits second dielectric layer on the outside of barrier metal layer, and second dielectric layer seals barrier metal layer, protects for surface
Shield.
As shown in Fig. 3 (e), second dielectric layer is deposited on the outside of barrier metal layer, specifically again PECVD deposits 50nm SiO2.
The preparation method of GaN base HEMT device disclosed in the present application, is deposited on the surface p-GaN for relatively thin TiN layer first,
Then fall TiN layer and p-GaN layer with the dry etching of BCl3/SF6 selectivity, the region after etching is carried out with SiO2 and Al2O3
Deposition forms dielectric layer, carries out deposition grid metal after subsequently the dielectric layer of gate region will be etched, finally by deposition second
Layer SiO2 dielectric layer passivation.During this growing film, so that device has four layers of field plate.Metal field plate is for reducing device
Dynamic electric voltage has great importance, and can also have an impact to the breakdown voltage of device.
By above-mentioned steps, a complete three mask plates grid structure element manufacturing is completed, behind can carry out as needed
Multilayer wiring.It, through the above steps can be with as shown in figure 4, for a kind of section schematic diagram of GaN base HEMT device in an embodiment
Find out, on the one hand technique and condition used in the manufacturing process of entire device are that Si CMOS technology is compatible, and technique
Complexity is low, strong operability, has coordinated the contradiction between device performance and process complexity well.It on the other hand can be right
The design of grid field plate becomes more flexible.For TiN grid metal, wherein incorporation Al ion can reduce grid resistance, so that its
Grid-control ability is reinforced.In conclusion this patent can flexible design grid field plate, reduction grid resistance be effectively p-GaN HEMT device
The design of the volume production scheme of part, which provides, to be used for reference well and refers to.
Based on GaN base HEMT disclosed in the present application and grid structure, as shown in figure 5, for a kind of GaN base HEMT in an embodiment
The structural schematic diagram of device is grown on 200mm Si (111) chip using Metallo-Organic Chemical Vapor deposition (MOCVD) technology
GaN layer.P-GaN layer is successively grown with GaN buffer layer, channel and potential barrier.2-DEG thin layer is formed in the interface of AlGaN/GaN
Place is located in GaN film layer.P-GaN cap layers improve the conduction band in channel in the state of the equilibrium, to realize enhanced work.
SiO2 and Al2O3 film layer also functions to passivation, inhibits current collapse effect and reduces surface leakage, is mainly used to eliminate material
Surface state, improve the stability and reliability of device.It can be seen that field plate designs may be implemented in the exposure mask of grid metal and etching
Flexibility.TiN and p-GaN forms Schottky diode, belongs to reverse bias in the on-state work of transistor, reduces
Gate leak current.P-GaN layer is not influenced due to containing Al ingredient in grid metal, and when etching deposition grid metal, so
Its gate resistance (Rsh-metal) very little, grid-control ability enhancing, to further promote the overall performance of device.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not to limit
The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple
It deduces, deform or replaces.
Claims (10)
1. a kind of GaN base HEMT device, which is characterized in that including substrate, buffer layer, GaN channel layer, AlGaN potential barrier, P-
GaN cap, metal layer, barrier metal layer and dielectric layer；
The buffer layer is stacked in the substrate；
The GaN channel layer is stacked on the buffer layer；
The AlGaN potential barrier is stacked on the GaN channel layer；
The P-GaN cap layers are stacked on the AlGaN potential barrier；
The metal layer is stacked on the AlGaN potential barrier；
The barrier metal layer is stacked on the metal layer；
The dielectric layer is arranged outside the P-GaN cap layers, the metal layer and the barrier metal layer, described for sealing
GaN base HEMT device.
2. HEMT device as described in claim 1, which is characterized in that further include Two-dimensional electron gas-bearing formation, be formed in the GaN ditch
The contact surface of channel layer and the AlGaN potential barrier is biased to the GaN channel layer side.
3. HEMT device as described in claim 1, which is characterized in that by institute between the AlGaN potential barrier and the dielectric layer
State the isolation of P-GaN cap layers.
4. HEMT device as described in claim 1, which is characterized in that the thickness of the metal layer is not more than the P-GaN cap layers
Thickness.
5. HEMT device as described in claim 1, which is characterized in that the barrier metal layer is by TiN, Ni, Au, W, the materials such as Pt or Pd
At least one of matter is constituted.
6. HEMT device as described in claim 1, which is characterized in that the dielectric layer is by SiNx、SiO2、SiON、Al2O3Or
At least one of materials such as AlN are constituted.
7. HEMT device as described in claim 1, which is characterized in that the AlGaN potential barrier is by AlxGa1-xN,InxGa1-xN,
InxAl1-xN, or InxAlyGa1-x-yAt least one of materials such as N are constituted.
8. HEMT device as described in claim 1, which is characterized in that the grid structure of the HEMT device is three mask plate grid knots
Structure, including the P-GaN cap layers, the metal layer and the barrier metal layer；Contain Al ingredient in the barrier metal layer.
9. a kind of preparation method of GaN base HEMT device characterized by comprising
It is sequentially prepared buffer layer, GaN channel layer, AlGaN potential barrier, P-GaN cap layers and metal layer on substrate；
First medium layer is deposited on the metal layer；
First window is opened on the first medium layer, the bottom of the window is located on the metal layer；
Barrier metal layer is deposited on the first window；
Second dielectric layer is deposited on the outside of the barrier metal layer, the second dielectric layer seals the barrier metal layer.
10. method as claimed in claim 9, which is characterized in that contain Al ingredient in the barrier metal layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117936403A (en) * | 2023-12-26 | 2024-04-26 | 苏州汉骅半导体有限公司 | GaN HEMT epitaxial material Hall test sample and preparation method thereof |
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| US20150325667A1 (en) * | 2014-05-08 | 2015-11-12 | Nxp B.V. | Semiconductor device and manufacturing method |
| CN106684140A (en) * | 2015-11-06 | 2017-05-17 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing same |
| CN108735810A (en) * | 2017-04-21 | 2018-11-02 | 瑞萨电子株式会社 | The manufacturing method of semiconductor devices and semiconductor devices |
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| US20040201038A1 (en) * | 2003-01-27 | 2004-10-14 | Tokuharu Kimura | Compound semiconductor device and its manufacture |
| US20150325667A1 (en) * | 2014-05-08 | 2015-11-12 | Nxp B.V. | Semiconductor device and manufacturing method |
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