CN109741770A - A kind of storage device, processor and electronic equipment - Google Patents
A kind of storage device, processor and electronic equipment Download PDFInfo
- Publication number
- CN109741770A CN109741770A CN201811639237.9A CN201811639237A CN109741770A CN 109741770 A CN109741770 A CN 109741770A CN 201811639237 A CN201811639237 A CN 201811639237A CN 109741770 A CN109741770 A CN 109741770A
- Authority
- CN
- China
- Prior art keywords
- storage device
- source electrode
- grid
- voltage
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
This application provides a kind of storage devices, comprising: the first source electrode, for providing power supply for the storage device;Grid, for forming electric field with first source electrode;And it is set to the suspending door between first source electrode and the grid, for storing the electronics of characterization storage device storage information;Wherein, first source electrode and the grid have first voltage.In the storage device, due to first source electrode and grid voltage having the same, then potential-free between the two is poor, therefore, based on the electric field formed between first source electrode and grid, so that the electronic still in the suspending door in the electric field ensure that the storage organization logic polarity in electronic equipment remains unchanged so that the logic polarity that the storage device is read out is constant.
Description
Technical field
The present invention relates to field of electronic devices, and more specifically, it relates to a kind of storage device, processor and electronics to set
It is standby.
Background technique
Electronic equipment generally all has storage organization, for storing to information, still, uses one section in electronic equipment
After time, the storage organization of electronic equipment will appear problem.
The problem of storage organization, is embodied in, and the storage organization logic polarity is unstable.
Therefore, the stable method of the logic polarity of the storage organization can be guaranteed by needing one kind.
Summary of the invention
In view of this, being solved electric in the prior art the present invention provides a kind of storage device, processor and electronic equipment
The unstable problem of the storage organization logic polarity of sub- equipment.
To achieve the above object, the invention provides the following technical scheme:
A kind of storage device, comprising:
First source electrode, for providing power supply for the storage device;
Grid, for forming electric field with first source electrode;
And
The suspending door being set between first source electrode and the grid stores information for storing characterization storage device
Electronics;
Wherein, first source electrode and the grid have first voltage.
Preferably, above-mentioned storage device, wherein the voltage difference at the suspending door both ends characterizes the storage unit
Virtual voltage level is 0 based on the virtual voltage level, and the logic polarity when storage device is in reading state is 0.
Preferably, above-mentioned storage device, further includes: the second source electrode;
Voltage difference between second source electrode and the grid characterizes whether presently described storage device is in reading shape
State;
Wherein, when second source electrode has second voltage, the storage device is in reading state;Second source electrode
When with first voltage, the storage device is in standby.
Preferably, above-mentioned storage device, further includes:
Drain electrode, for forming the first triode with the first source electrode, grid and being used for and second source electrode, the grid
Pole forms the second triode;
Wherein, when the drain electrode has tertiary voltage, the storage device is in reading state;The drain electrode has first
When voltage, the storage device is in standby.
Preferably, above-mentioned storage device, further includes:
Roof door, the roof door are connected with the grid, and the roof door and the suspending door are arranged in parallel.
A kind of processor, comprising: at least two storage devices;
Wherein, the storage device include the first source electrode, grid and be set to first source electrode and the grid it
Between suspending door;
Wherein, the first source electrode, for providing power supply for the storage device;
Grid, for forming electric field with first source electrode;
The suspending door, for storing the electronics of characterization storage device storage information;
Wherein, first source electrode and the grid have first voltage.
Preferably, above-mentioned processor, suspending door both ends described in the storage device voltage difference characterization described in deposit
The virtual voltage level of storage device is 0 based on the virtual voltage level, and the storage device is in logic when reading state
Polarity is 0.
Preferably, above-mentioned processor, the storage device, further includes: the second source electrode;
Voltage difference between second source electrode and the grid characterizes whether presently described storage device is in reading shape
State;
Wherein, when second source electrode has second voltage, the storage device is in reading state;Second source electrode
When with first voltage, the storage device is in standby.
Preferably, above-mentioned processor, the storage device, further includes:
Drain electrode, for forming the first triode with the first source electrode, grid and being used for and second source electrode, the grid
Pole forms the second triode;
Wherein, when the drain electrode has tertiary voltage, the storage device is in reading state;The drain electrode has first
When voltage, the storage device is in standby.
A kind of electronic equipment, including first processor and second processor;
The first processor has working condition and off working state;
There is working condition, for obtaining when the first processor uses off working state in the second processor
Information must be inputted, and triggers the first processor switching and is in working condition;
It wherein, include at least two storage devices in the second processor;
The storage device includes the first source electrode, grid and is set to outstanding between first source electrode and the grid
Float gate;
Wherein, the first source electrode, for providing power supply for the storage device;
Grid, for forming electric field with first source electrode;
The suspending door, for storing the electronics of characterization storage device storage information;
Wherein, first source electrode and the grid have first voltage.
It can be seen via above technical scheme that compared with prior art, the present invention provides a kind of storage devices, comprising:
First source electrode, for providing power supply for the storage device;Grid, for forming electric field with first source electrode;And setting
Suspending door between first source electrode and the grid, for storing the electronics of characterization storage device storage information;Wherein,
First source electrode and the grid have first voltage.In the storage device, due to first source electrode and grid have it is identical
Voltage, then potential-free between the two is poor, therefore, based on the electric field formed between first source electrode and grid so that be in the electricity
The electronic still in suspending door in ensure that electronics so that the logic polarity that the storage device is read out is constant
Storage organization logic polarity in equipment remains unchanged.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of memory device embodiment 1 provided by the present application;
Fig. 2 is the schematic illustration of logic polarity variation in the prior art;
Fig. 3 is initial read in the prior art (power supply in 2.2V7 days) distribution schematic diagram;
Fig. 4 is high-temperature baking distribution situation in the prior art;
Fig. 5 is a kind of another structural schematic diagram of memory device embodiment 1 provided by the present application;
Fig. 6 is a kind of structural schematic diagram of memory device embodiment 2 provided by the present application;
Fig. 7 is a kind of structural schematic diagram of memory device embodiment 3 provided by the present application;
Fig. 8 is a kind of application scenarios schematic diagram of storage device provided by the present application;
Fig. 9 is a kind of structural schematic diagram of processor embodiment provided by the present application;
Figure 10 is the structural schematic diagram of a kind of electronic equipment embodiment provided by the present application.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, it is a kind of structural schematic diagram of memory device embodiment 1 provided by the present application, which includes
With flowering structure: the first source electrode (source), grid (CG) and suspending door (floating gate);
Wherein, first source electrode, for providing power supply for the storage device;
Wherein, grid, for forming electric field with first source electrode;
Wherein, the suspending door is set between first source electrode and the grid, is deposited for storing characterization storage device
Store up the electronics of information;
Wherein, first source electrode and the grid have first voltage.
Specifically, being stored with electronics in the suspending door, the distribution of the electronics characterizes storage device storage information
State.
In specific implementation, the state of the storage information is expressed as the logic polarity of the storage device, and 0 or 1.
It should be noted that first voltage having the same between first source electrode and grid, which is based on the
Electric field is formed between one source electrode and grid, potential-free is poor in the electric field, so that the electronic still in the suspending door in the electric field,
Prevent the possibility leaked electricity, solves the problems, such as because of the variation of logic polarity caused by leaking electricity, so that the storage device is patrolled
It is constant to collect polarity.
Wherein, the voltage difference at the suspending door both ends characterizes the virtual voltage level of the storage unit, and due to this
The voltage at suspending door both ends is first voltage, then the virtual voltage level of the storage unit is 0, quasi- based on the virtual voltage
Position is 0, and the logic polarity when storage device is in reading state is 0.
It should be noted that since the voltage at the suspending door both ends is first voltage, even if with the increasing for using the time
Long, the electronics in the suspending door is not also affected, and will not move, and then guarantee the logic that the storage device is read out
Polarity is constant.
It should be noted that the storage device can be using E-flash (high pressure embedded flash memory in specific implementation
Body).
As shown in Figure 5 is a kind of another structural schematic diagram of memory device embodiment 1 provided by the present application, the device packet
It includes with flowering structure: the first source electrode (source), grid (CG) and suspending door (floating gate) and roof door (top
gate);
Wherein, consistent in first source electrode, grid, the structure function of suspending door and a upper structural schematic diagram.
Wherein, the roof door, the roof door are connected with the grid, and the roof door and the suspending door are arranged in parallel.
Specifically, movement of the roof door for electronics in controlling filed, to complete the mistake that suspending door storage electronically forms electric field
Journey, to realize the write-in and erasing of control storage unit.
As shown in Figure 2 is the schematic illustration of E-flash logic polarity variation in the prior art, includes suspending in the figure
Door (floating gate) and electric field (field).Wherein, there are two the regions of N ﹢ for electric field tool, in standby, the electricity
Voltage value at is larger, so that the voltage of suspending door side corresponding with electric field is greater than the voltage of the suspending door other side, and then makes
The electronics in suspending door is obtained under the action of potential difference, it is close to the corresponding side of electric field, lead to electronic equipment in the suspending door
Distribution changes, and the logic polarity of the final E-flash has become 1 from 0.Electricity in the electric field that solid arrow indicates in figure
The direction of gesture from high to low, dotted arrow indicate the moving direction of electronics in suspending door.
As shown in Figure 3 is initial read (2.2V continued power 7 days) distribution situation (Initial read in the prior art
(2.2V power on 7days) Vt distribution) schematic diagram, in the figure, horizontal axis indicates voltage (VPP), unit V (volt
It is special), the longitudinal axis indicates that fail bits count (Fail bit count).Line 301 indicates damage curve, and the expression of line 302 is normal bent
Line, wherein each point indicates to be one-time detection (X:FA).In the part that wherein dotted line outlines, damage curve has bitmap
Random number (bitmap ramdom), distribution of the damage curve between general 1.8V-6.6V is mixed and disorderly, not according to gradually increasing
Long trend distribution, correspondingly, the logic polarity of a bit (position) of E-flash becomes 1 by 0 in the part.
It is shown in Fig. 4 for distribution situation (Bake Vt distribution) after high-temperature baking in the prior art.In the figure,
Horizontal axis indicates voltage (VPP), unit V (volt), and the longitudinal axis indicates that fail bits count (Fail bit count), wherein Mei Gedian
Expression is one-time detection (X:FA).Wherein, curve 402 and 404 is the song recompiled by the scheme in the application
Line, curve 401 and 403 are the curves for toasting 120 DEG C (degree Celsius) 24 hours (hrs) and obtaining;Wherein initial voltage is larger (initial
Voltage is normalized curve not less than the curve of 6V), no longer occurs being distributed mixed and disorderly situation, be distributed according to the trend gradually increased,
Wherein the curve 401 and 402 of initial voltage smaller (initial voltage is less than 6) is damage curve, the region of 5.6V to 6V or so
Middle region is distributed mixed and disorderly situation, this will lead to logic polarity of the structure and becomes 1 by 0, even across recompiling or dry
The problem of baking 120 DEG C 24 hours, still will appear logic polarity variation.
To sum up, a kind of storage device provided in this embodiment, comprising: the first source electrode, for being provided for the storage device
Power supply;Grid, for forming electric field with first source electrode;And it is set to outstanding between first source electrode and the grid
Float gate, for storing the electronics of characterization storage device storage information;Wherein, first source electrode and the grid have the first electricity
Pressure.In the storage device, due to first source electrode and grid voltage having the same, then potential-free between the two is poor, therefore, base
The electric field formed between first source electrode and grid, so that the electronic still in the suspending door in the electric field, so that
The logic polarity that the storage device is read out is constant, ensure that the logic polarity of the storage device in electronic equipment maintains not
Become.
It is as shown in FIG. 6, it is a kind of structural schematic diagram of memory device embodiment 2 provided by the present application, which includes
With flowering structure: the first source electrode (source), grid (CG), suspending door (floating gate) and the second source electrode (SG);
Wherein, the first source electrode, grid, the structure function of suspending door are consistent with the corresponding construction function in embodiment 1, this reality
It applies in example and does not repeat them here.
Wherein, the voltage difference between second source electrode and the grid characterizes whether presently described storage device is in reading
State;
Wherein, when second source electrode has second voltage, the storage device is in reading state;Second source electrode
When with first voltage, the storage device is in standby.
It in specific implementation, is connected between second source electrode and suspending door by special construction 601, which, which has, reduces leakage
The function of electricity prevents from making under the action of the electric field between second source electrode and grid the electronics in suspending door mobile, reduces leakage
Electricity.
Specifically, having a voltage difference between second source electrode and grid, the grid and the first source electrode all have the first electricity
Pressure, then when second source electrode has first voltage, the voltage difference 0 between the grid and second source;Second source electrode has the
When two voltage, the voltage difference between the grid and second source is the difference of second voltage and first voltage.
Specifically, the storage device is in standby when voltage difference is 0 between the grid and the second source electrode;The grid
When voltage difference between the second source electrode is not 0, then the storage device is in reading state, electronics distribution situation in suspending door
It can be read with the content-form of 1 byte.In specific implementation, the first voltage can use 1.8 volts, the second voltage
0 volt can be used.
It should be noted that second source electrode reads the data value of storage using 0V low level level in the present embodiment.
To sum up, in a kind of storage device provided in this embodiment, further includes: the second source electrode;Second source electrode with it is described
Voltage difference between grid characterizes whether presently described storage device is in reading state;Wherein, second source electrode has the
When two voltage, the storage device is in reading state;When second source electrode has first voltage, the storage device is in
Standby mode.In the present solution, determining the state of the storage state at this time based on the voltage difference between the second source electrode and grid, sentence
Disconnected process is simple and easy.
As shown in Figure 7, it is a kind of structural schematic diagram of memory device embodiment 3 provided by the present application, which includes
With flowering structure: the first source electrode (source), grid (CG), suspending door (floating gate) and the second source electrode (SG) and leakage
Pole (drain);
Wherein, the first source electrode, grid, suspending door, the structure function of the second source electrode and the corresponding construction function in embodiment 2
Unanimously, it is not repeated them here in the present embodiment.
Drain electrode, for forming the first triode with the first source electrode, grid and being used for and second source electrode, the grid
Pole forms the second triode;
Wherein, when the drain electrode has tertiary voltage, the storage device is in reading state;The drain electrode has first
When voltage, the storage device is in standby.
Wherein, which forms a triode by the suspending door and the first source electrode, grid, and drain electrode also passes through suspending door
A triode is formed with the second source electrode, grid, includes suspending door in two triodes.
Specifically, voltage difference is 0 between the drain electrode and grid, which is in when the drain electrode has first voltage
Standby mode;When the drain electrode has tertiary voltage, voltage difference is not 0 between the grid and drain electrode, which, which is in, reads
State.
In specific implementation, which can be 0.1V.
To sum up, in a kind of storage device provided in this embodiment, further includes: drain electrode, for being formed with the first source electrode, grid
First triode and be used for and second source electrode, the grid form the second triode;Wherein, the drain electrode has the
When three voltage, the storage device is in reading state;When the drain electrode has first voltage, the storage device is in standby
State.In the present solution, can determine the state of the storage state at this time based on the voltage difference between drain electrode and grid, judged
Journey is simple and easy.
As shown in Figure 8, it is a kind of application scenarios schematic diagram of storage device provided by the present application, including reading state
(read) and standby mode (stand by) two states, the storage device include grid (CG), the first source electrode (source),
Two source electrodes (SG), drain electrode (drain), suspending door (floating gate) and roof door (top gate).Wherein, the end CG electricity
Pressure is 1.8V, which is Flash_Vcc, which is 1.8V, which is to read shape
When state, which is 0V, and the end Drain voltage is 0.1V;When the storage device is standby mode, which is
1.8V, drain termination voltage are Flash_Vcc, which is 1.8V.
Corresponding with a kind of above-mentioned memory device embodiment provided by the present application, present invention also provides include the storage
The processor embodiment of device.
As shown in Figure 9 is a kind of structural schematic diagram of processor embodiment provided by the present application, the processor include with
Flowering structure: at least two storage devices 901;
Wherein, which includes the first source electrode, grid and is set between first source electrode and the grid
Suspending door;
Wherein, the first source electrode, for providing power supply for the storage device;Grid, for being formed with first source electrode
Electric field;The suspending door, for storing the electronics of characterization storage device storage information;Wherein, first source electrode and the grid
It is great to have first voltage.
Specifically, the structure function of the storage device can refer to memory device embodiment above-mentioned, in the present embodiment not
It is described in detail.
In specific implementation, which can be distributed in array fashion, and each storage device corresponds to the processor
One data bit (bit).
Preferably, above-mentioned processor, suspending door both ends described in the storage device voltage difference characterization described in deposit
The virtual voltage level of storage device is 0 based on the virtual voltage level, and the storage device is in logic when reading state
Polarity is 0.
Preferably, above-mentioned processor, the storage device, further includes: the second source electrode;
Voltage difference between second source electrode and the grid characterizes whether presently described storage device is in reading shape
State;
Wherein, when second source electrode has second voltage, the storage device is in reading state;Second source electrode
When with first voltage, the storage device is in standby.
Preferably, above-mentioned processor, the storage device, further includes:
Drain electrode, for forming the first triode with the first source electrode, grid and being used for and second source electrode, the grid
Pole forms the second triode;
Wherein, when the drain electrode has tertiary voltage, the storage device is in reading state;The drain electrode has first
When voltage, the storage device is in standby.
To sum up, a kind of processor provided in this embodiment, comprising: at least two storage devices;Wherein, the storage device packet
Include the first source electrode, grid and the suspending door being set between first source electrode and the grid;Wherein, the first source electrode is used
In providing power supply for the storage device;Grid, for forming electric field with first source electrode;The suspending door, for storing
Characterize the electronics of storage device storage information;Wherein, first source electrode and the grid have first voltage.The processor
In each storage device, due to first source electrode and grid voltage having the same, then potential-free between the two is poor, therefore, base
The electric field formed between first source electrode and grid, so that the electronic still in the suspending door in the electric field, so that
The logic polarity that the storage device is read out is constant, ensure that the logic polarity of the storage device in electronic equipment maintains not
Become.
Corresponding with a kind of above-mentioned memory device embodiment provided by the present application, present invention also provides deposit comprising above-mentioned
The electronic equipment embodiment of storage device, processor.
As shown in Figure 10 is the structural schematic diagram of a kind of electronic equipment embodiment provided by the present application, which includes
With flowering structure: first processor 1001 and second processor 1002;
Wherein, the first processor 1001 has working condition and off working state;
Wherein, there is working condition, for using inoperative in the first processor in the second processor 1002
When state, input information is obtained, and triggers the first processor switching and is in working condition;
It wherein, include at least two storage devices in the second processor;
The storage device includes the first source electrode, grid and is set to outstanding between first source electrode and the grid
Float gate;
Wherein, the first source electrode, for providing power supply for the storage device;Grid, for being formed with first source electrode
Electric field;The suspending door, for storing the electronics of characterization storage device storage information;Wherein, first source electrode and the grid
It is great to have first voltage.
Wherein, the structure function of the storage device is consistent with the embodiment of aforementioned storage device, does not do in the present embodiment superfluous
It states.
In specific implementation, which is CPU (central processing unit, center in electronic equipment
Processor), which is the EC (embedded controller, embedded controller) in electronic equipment.
To sum up, in each storage device of a kind of electronic equipment provided in this embodiment, due to first source electrode and grid
Voltage having the same, then potential-free between the two is poor, therefore, based on the electric field formed between first source electrode and grid, so that
Electronic still in the suspending door in the electric field is protected so that the logic polarity that the storage device is read out is constant
The logic polarity for having demonstrate,proved the storage device in electronic equipment remains unchanged.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.The device provided for embodiment
For, since it is corresponding with the method that embodiment provides, so being described relatively simple, related place is said referring to method part
It is bright.
To the above description of provided embodiment, enable those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and principle provided in this article and features of novelty phase one
The widest scope of cause.
Claims (10)
1. a kind of storage device, comprising:
First source electrode, for providing power supply for the storage device;
Grid, for forming electric field with first source electrode;
And
The suspending door being set between first source electrode and the grid, for storing the electricity of characterization storage device storage information
Son;
Wherein, first source electrode and the grid have first voltage.
2. storage device according to claim 1, wherein it is single that the voltage difference at the suspending door both ends characterizes the storage
The virtual voltage level of member is 0 based on the virtual voltage level, and the storage device is in logic polarity when reading state
It is 0.
3. storage device according to claim 1, further includes: the second source electrode;
Voltage difference between second source electrode and the grid characterizes whether presently described storage device is in reading state;
Wherein, when second source electrode has second voltage, the storage device is in reading state;Second source electrode has
When first voltage, the storage device is in standby.
4. storage device according to claim 3, further includes:
Drain electrode, for forming the first triode with the first source electrode, grid and being used for and second source electrode, the grid group
At the second triode;
Wherein, when the drain electrode has tertiary voltage, the storage device is in reading state;The drain electrode has first voltage
When, the storage device is in standby.
5. storage device according to claim 1, further includes:
Roof door, the roof door are connected with the grid, and the roof door and the suspending door are arranged in parallel.
6. a kind of processor, comprising: at least two storage devices;
Wherein, the storage device includes the first source electrode, grid and is set between first source electrode and the grid
Suspending door;
Wherein, the first source electrode, for providing power supply for the storage device;
Grid, for forming electric field with first source electrode;
The suspending door, for storing the electronics of characterization storage device storage information;
Wherein, first source electrode and the grid have first voltage.
7. the voltage difference of processor according to claim 6, suspending door both ends described in the storage device characterizes institute
The virtual voltage level of storage device is stated, is 0 based on the virtual voltage level, when the storage device is in reading state
Logic polarity is 0.
8. processor according to claim 7, the storage device, further includes: the second source electrode;
Voltage difference between second source electrode and the grid characterizes whether presently described storage device is in reading state;
Wherein, when second source electrode has second voltage, the storage device is in reading state;Second source electrode has
When first voltage, the storage device is in standby.
9. processor according to claim 7, the storage device, further includes:
Drain electrode, for forming the first triode with the first source electrode, grid and being used for and second source electrode, the grid group
At the second triode;
Wherein, when the drain electrode has tertiary voltage, the storage device is in reading state;The drain electrode has first voltage
When, the storage device is in standby.
10. a kind of electronic equipment, including first processor and second processor;
The first processor has working condition and off working state;
There is working condition, for obtaining defeated when the first processor uses off working state in the second processor
Enter information, and triggers the first processor switching and be in working condition;
It wherein, include at least two storage devices in the second processor;
The storage device includes the first source electrode, grid and the suspension being set between first source electrode and the grid
Door;
Wherein, the first source electrode, for providing power supply for the storage device;
Grid, for forming electric field with first source electrode;
The suspending door, for storing the electronics of characterization storage device storage information;
Wherein, first source electrode and the grid have first voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811639237.9A CN109741770A (en) | 2018-12-29 | 2018-12-29 | A kind of storage device, processor and electronic equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811639237.9A CN109741770A (en) | 2018-12-29 | 2018-12-29 | A kind of storage device, processor and electronic equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
CN109741770A true CN109741770A (en) | 2019-05-10 |
Family
ID=66362523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811639237.9A Pending CN109741770A (en) | 2018-12-29 | 2018-12-29 | A kind of storage device, processor and electronic equipment |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN109741770A (en) |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0757486A (en) * | 1993-08-06 | 1995-03-03 | Sony Corp | Driving method for nand type nonvolatile memory |
EP0774788A1 (en) * | 1995-11-14 | 1997-05-21 | Programmable Microelectronics Corporation | A PMOS flash memory cell capable of multi-level threshold voltage storage |
CN1218294A (en) * | 1997-10-09 | 1999-06-02 | 美商常忆科技股份有限公司 | Nonvolatile PMOS two transistor memory cell and array |
CN1627446A (en) * | 2003-12-08 | 2005-06-15 | 联华电子股份有限公司 | Method for programming P channel electrically erasable programmable read only memory |
US20090161439A1 (en) * | 2007-12-25 | 2009-06-25 | Genusion, Inc. | Nonvolatile Semiconductor Memory Device |
CN101573764A (en) * | 2006-12-22 | 2009-11-04 | 崔雄林 | 2t NOR-type non-volatile memory cell array and method of processing data of 2t NOR-type non-volatile memory |
CN101997956A (en) * | 2009-08-17 | 2011-03-30 | 联想(北京)有限公司 | Method for switching work mode of mobile terminal and mobile terminal |
CN102136480A (en) * | 2010-01-21 | 2011-07-27 | 上海华虹Nec电子有限公司 | EEPROM (electrically erasable programmable read only memory) device |
CN104781884A (en) * | 2012-11-08 | 2015-07-15 | 桑迪士克科技股份有限公司 | Flash memory with data retention bias |
US20150325307A1 (en) * | 2014-05-09 | 2015-11-12 | Semiconductor Manufacturing International (Beijing) Corporation | Method for setting a flash memory for htol testing |
CN105718338A (en) * | 2014-12-05 | 2016-06-29 | 联想(北京)有限公司 | Information processing method and electronic device |
CN106415839A (en) * | 2014-06-12 | 2017-02-15 | 德克萨斯仪器股份有限公司 | Reducing retention loss in analog floating gate memory |
CN107104105A (en) * | 2016-01-28 | 2017-08-29 | 台湾积体电路制造股份有限公司 | One Time Programmable with floating gate shield part(OTP)Memory cell and its manufacture method |
CN107836042A (en) * | 2015-04-05 | 2018-03-23 | Neo半导体公司 | 2T SONOS flash memories |
-
2018
- 2018-12-29 CN CN201811639237.9A patent/CN109741770A/en active Pending
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0757486A (en) * | 1993-08-06 | 1995-03-03 | Sony Corp | Driving method for nand type nonvolatile memory |
EP0774788A1 (en) * | 1995-11-14 | 1997-05-21 | Programmable Microelectronics Corporation | A PMOS flash memory cell capable of multi-level threshold voltage storage |
CN1218294A (en) * | 1997-10-09 | 1999-06-02 | 美商常忆科技股份有限公司 | Nonvolatile PMOS two transistor memory cell and array |
CN1627446A (en) * | 2003-12-08 | 2005-06-15 | 联华电子股份有限公司 | Method for programming P channel electrically erasable programmable read only memory |
CN101573764A (en) * | 2006-12-22 | 2009-11-04 | 崔雄林 | 2t NOR-type non-volatile memory cell array and method of processing data of 2t NOR-type non-volatile memory |
US20090161439A1 (en) * | 2007-12-25 | 2009-06-25 | Genusion, Inc. | Nonvolatile Semiconductor Memory Device |
CN101997956A (en) * | 2009-08-17 | 2011-03-30 | 联想(北京)有限公司 | Method for switching work mode of mobile terminal and mobile terminal |
CN102136480A (en) * | 2010-01-21 | 2011-07-27 | 上海华虹Nec电子有限公司 | EEPROM (electrically erasable programmable read only memory) device |
CN104781884A (en) * | 2012-11-08 | 2015-07-15 | 桑迪士克科技股份有限公司 | Flash memory with data retention bias |
US20150325307A1 (en) * | 2014-05-09 | 2015-11-12 | Semiconductor Manufacturing International (Beijing) Corporation | Method for setting a flash memory for htol testing |
CN105097048A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(北京)有限公司 | Flash setting method used for HTOL (High Temperature Operating Life) test |
CN106415839A (en) * | 2014-06-12 | 2017-02-15 | 德克萨斯仪器股份有限公司 | Reducing retention loss in analog floating gate memory |
CN105718338A (en) * | 2014-12-05 | 2016-06-29 | 联想(北京)有限公司 | Information processing method and electronic device |
CN107836042A (en) * | 2015-04-05 | 2018-03-23 | Neo半导体公司 | 2T SONOS flash memories |
CN107104105A (en) * | 2016-01-28 | 2017-08-29 | 台湾积体电路制造股份有限公司 | One Time Programmable with floating gate shield part(OTP)Memory cell and its manufacture method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8050097B2 (en) | Method of programming nonvolatile memory device | |
JP5422984B2 (en) | NONVOLATILE MEMORY, MEMORY CONTROL DEVICE, MEMORY CONTROL SYSTEM, AND NONVOLATILE MEMORY CONTROL METHOD | |
CN101923899B (en) | Method and device for erasing nonvolatile memory | |
Cooke | The inconvenient truths of NAND flash memory | |
CN101867169B (en) | It is applied to the protection circuit of flash memory | |
CN103489479B (en) | Semiconductor storage unit and its operating method | |
CN101981627A (en) | Nand memory | |
CN103366831B (en) | The detection method of memory | |
CN103680622B (en) | The nonvolatile memory (NVM) of adaptable write operation | |
CN104064222B (en) | The checking device of flash memories | |
US11004505B1 (en) | Method for operating a non-volatile memory cell | |
KR20120062075A (en) | Controller for memory and storage system includint the same, method for measuring life span of memory | |
CN106328203A (en) | Flash memory device and method for initializing program operation thereof | |
US8359427B2 (en) | Semiconductor device | |
CN109741770A (en) | A kind of storage device, processor and electronic equipment | |
CN106448730A (en) | Method for Writing in an EEPROM Memory and Corresponding Memory | |
KR100791838B1 (en) | Smart card and method for testing of smart card | |
KR100610490B1 (en) | Eeprom cell and eeprom block | |
CN105989888B (en) | Nonvolatile memory device, method of operating the same, and test system having the same | |
CN102237136B (en) | Storage subunit erasure method used in storage device | |
US8081520B2 (en) | Over erase correction method of flash memory apparatus | |
CN107341075B (en) | Power-down protection device and electronic equipment | |
CN105097029B (en) | A kind of storage equipment and information processing method | |
US8854887B2 (en) | Nonvolatile memory device and method of programming the same | |
KR20080024370A (en) | Nand flash memory device and method of initializing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190510 |