CN109740247B - IP and EFPGA port connection method and optimization method thereof - Google Patents
IP and EFPGA port connection method and optimization method thereof Download PDFInfo
- Publication number
- CN109740247B CN109740247B CN201811641453.7A CN201811641453A CN109740247B CN 109740247 B CN109740247 B CN 109740247B CN 201811641453 A CN201811641453 A CN 201811641453A CN 109740247 B CN109740247 B CN 109740247B
- Authority
- CN
- China
- Prior art keywords
- efpga
- resource
- port
- result
- legal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a port connection method of IP and EFPGA, comprising the following steps: establishing a hierarchical design project by using a hardware description language; mapping an IO port of the IP to a port of a top module based on a logical relation of the IP on the EFPGA to be connected in the hierarchical design engineering; performing logical synthesis on the operation of the hierarchical design project, and outputting a comprehensive result; each IO in the comprehensive result selects any legal IO resource in the IO resources of the single-side port of the IO module to be connected with the EFPGA to be distributed; and when each IO has a legal position, saving the position information of the IO resource. A preferred method comprises the steps that legal IO resource position information is randomly distributed to each IO in a repeated comprehensive result for many times, and overall layout, detailed layout and winding are respectively carried out to obtain a time sequence performance result; and sequencing the time sequence performance results, and selecting the position information of the IO resource with the optimal time sequence performance result. And a plurality of IO positions are used for replacing the IP of a single position, so that the work of the integrated IP is normalized and streamlined.
Description
Technical Field
The invention relates to the field of integrated connection of IP and EFPGA, in particular to a connection method of IP and EFPGA ports and a preferred method thereof.
Background
At present, the requirement of integrated connection of an internal IP or a third-party IP and an EFPGA is often met in system integration, a port of the IP is connected with input and output IO of the EFPGA to integrate a new chip, the integrated performance is an important link which is considered by people, a large number of input and output IO are arranged on four sides of the EFPGA, the performance of the IO ports on the four sides of the EFPGA can be comprehensively evaluated through conventional integrated connection, and the defects that the overall layout and the detailed layout cannot be considered in connection are caused.
Disclosure of Invention
The invention aims to solve the defects in the prior art.
In order to achieve the above object, a first aspect of the present invention provides a method for connecting IP and EFPGA ports, including the steps of:
establishing a hierarchical design project by using a hardware description language, wherein the hierarchical design project comprises a logic relation of an IP on an EFPGA to be connected and a top-level module;
mapping an IO port of the IP to a port of a top module based on the logical relationship of the IP on the EFPGA to be connected;
performing logical synthesis on the operation of the hierarchical design project, and outputting a comprehensive result;
each IO in the comprehensive result selects any legal IO resource in the IO resources of the single-side port of the IO module to be connected with the EFPGA to be distributed;
and when each IO has a legal position, saving the position information of the IO resource.
The second aspect is a preferred port connection method of IP and EFPGA, comprising the steps of:
establishing a hierarchical design project by using a hardware description language, wherein the hierarchical design project comprises a logic relation of an IP on an EFPGA to be connected and a top module;
mapping an IO port of the IP to a port of a top module based on the logical relationship of the IP on the EFPGA to be connected;
performing logical synthesis on the operation of the hierarchical design project, and outputting a comprehensive result;
each IO in the comprehensive result selects any legal IO resource in the IO resources of the single-side port of the IO module to be connected with the EFPGA to be distributed;
when each IO has a legal position, saving the position information of the IO resource;
carrying out global layout, detailed layout and winding on the obtained position information of the IO resources to obtain a time sequence performance result of winding;
selecting any legal IO resource in the IO resources of the single-side port of the IO module to be connected with the EFPGA for distribution for each IO in the comprehensive result at least twice, and storing the position information of the IO resource each time and the corresponding time sequence performance result;
and sequencing the time sequence performance results, and selecting the position information of the IO resource with the optimal time sequence performance result.
Preferably, the IO resources of the single-side port of the IO module to be connected with the EFPGA are divided into an input resource group and an output resource group; and each IO in the comprehensive result selects any legal IO resource in the input resource group or the output resource group to be distributed according to the directionality.
Preferably, the above steps are repeated at least twice, and a single-sided port on the same side of the EFPGA is selected.
Preferably, the hardware description language is VHDL or Verilog language.
Preferably, the hierarchical design engineering is designed according to the EFPGA to be connected.
The invention has the advantages that: the performance of the integrated IP and EFPGA can be well ensured, the IP of a single position is replaced by a plurality of IO positions, the connection relation between the IO positions and the IP is not defined blindly, and the work of the integrated IP is standardized and streamlined.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for connecting IP and EFPGA ports;
fig. 2 is a flow chart of a preferred port connection method for IP and EFPGA.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart of a port connection method between IP and EFPGA. As shown in fig. 1, the steps include:
step S101: and establishing a hierarchical design project by using a hardware description language, wherein the hierarchical design project comprises a logic relation of the IP on the EFPGA to be connected, a top layer module and a bottom layer module.
Step S102: and mapping the IO port of the IP to the port of the top module based on the logical relationship of the IP on the EFPGA to be connected.
Step S103: and (5) performing logical synthesis on the operation of the hierarchical design project and outputting a comprehensive result.
Step S104: and each IO in the comprehensive result selects any legal IO resource in the IO resources of the single-side port of the IO module to be connected with the EFPGA to be distributed.
Step S105: and when each IO has a legal position, saving the position information of the IO resource.
In one embodiment, the hierarchical design engineering is designed according to a target EFPGA using Verilog language. And carrying out IO resource allocation by using the left port of the IO module of the EFPGA. And mapping the IO port of the IP to the port of the top module based on the logical relation of the IP on the EFPGA, further carrying out logical synthesis on the operation of the hierarchical design project and outputting a synthetic result. Meanwhile, dividing IO resources of a left port of an IO module of the EFPGA into an input resource group and an output resource group; and each IO in the comprehensive result selects any legal IO resource in the input resource group or the output resource group for distribution according to the directionality. And further obtaining the position information of the IO resources.
Similarly, the IO resources of the port on any side of the EFPGA except the left side may be divided into an input resource group and an output resource group, so that each IO in the integrated result is selected and allocated according to the directionality, and the position information of the IO resources is obtained.
Fig. 2 is a flow chart of a preferred port connection method for IP and EFPGA. As shown in fig. 2, the steps include:
step S101: and establishing a hierarchical design project by using a hardware description language, wherein the hierarchical design project comprises a logic relation of the IP on the EFPGA to be connected and a top-level module.
Step S102: and mapping the IO port of the IP to the port of the top module based on the logic relation of the IP on the EFPGA to be connected.
Step S103: and (5) performing logical synthesis on the operation of the hierarchical design project and outputting a comprehensive result.
Step S104: and each IO in the comprehensive result selects any legal IO resource in the IO resources of the single-side port of the IO module to be connected with the EFPGA to be distributed.
Step S105: and when each IO has a legal position, saving the position information of the IO resource.
Step S106: and carrying out global layout, detailed layout and winding on the obtained position information of the IO resources to obtain a time sequence performance result of winding.
After the steps S101 to S106 are completed once, the position information of 1 group of IO resources and the corresponding timing performance result are obtained, and after the steps S104 to S106 are repeated at least twice, the step S107 is executed after the position information of at least two groups of IO resources and the corresponding timing performance result are obtained.
Step S107: and sequencing the time sequence performance results, and selecting the position information of the IO resource with the optimal time sequence performance result.
In one embodiment, the hierarchical design project is designed according to the target EFPGA using Verilog language. After the steps S101 to S106 are performed once for one IP, 99 steps S104 to S106 are performed to obtain the location information of 100 groups of IO resources, and the connection location with the best integration performance of the IP and the EFPGA is found according to the timing performance result. And further determining the specific IO corresponding to the connection according to the port information of the IP and the connection position information with the best integration performance, wherein the integrated IP and the EFPGA form a whole system.
The invention provides a port connection method of IP and EFPGA and a preferred method thereof, which can well ensure the performance of the integrated IP and EFPGA, replace the IP of a single position by a plurality of IO positions, and not blindly define the connection relation between the IP and the EFPGA, so that the work of the integrated IP is standardized and streamlined.
The above embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. A method for connecting an IP port with an EFPGA port, comprising the steps of:
establishing a hierarchical design project by using a hardware description language, wherein the hierarchical design project comprises a logic relation of an IP on an EFPGA to be connected and a top-level module;
mapping an IO port of the IP to a port of the top module based on the logical relationship of the IP on the EFPGA to be connected;
performing logic synthesis on the operation of the hierarchical design project, and outputting a synthesis result;
each IO in the comprehensive result selects any legal IO resource from the IO resources of the single-side port of the IO module to be connected with the EFPGA to be distributed;
when each IO has a legal position, saving the position information of the IO resource;
carrying out global layout, detailed layout and winding on the obtained position information of the IO resources to obtain a time sequence performance result of winding;
selecting any legal IO resource in the IO resources of the single-side port of the IO module to be connected with the EFPGA for distribution for each IO in the comprehensive result at least twice, and storing the position information of the IO resource each time and the corresponding time sequence performance result;
and sequencing the time sequence performance results, and selecting the position information of the IO resource with the optimal time sequence performance result.
2. The method according to claim 1, wherein the IO resources of the single-side port of the IO module to which the EFPGA is to be connected are divided into an input resource group and an output resource group; and each IO in the comprehensive result selects any legal IO resource in the input resource group or the output resource group to be distributed according to the directionality.
3. The method according to claim 1, wherein the at least twice selecting, for each IO in the integrated result, any legal IO resource from IO resources of a single-side port of an IO module to be connected with the EFPGA to allocate, and storing the position information of the IO resource and the corresponding timing performance result of each time, comprises:
and selecting any legal IO resource in the IO resources of the single-side port to be connected with the same side of the EFPGA for distribution for each IO in the comprehensive result at least twice, and storing the position information of the IO resource each time and the corresponding time sequence performance result.
4. The method of claim 1, wherein the hardware description language is VHDL or Verilog language.
5. The method of claim 1, wherein the hierarchical design engineering is designed according to the to-be-connected EFPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811641453.7A CN109740247B (en) | 2018-12-29 | 2018-12-29 | IP and EFPGA port connection method and optimization method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811641453.7A CN109740247B (en) | 2018-12-29 | 2018-12-29 | IP and EFPGA port connection method and optimization method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109740247A CN109740247A (en) | 2019-05-10 |
| CN109740247B true CN109740247B (en) | 2023-04-18 |
Family
ID=66362518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811641453.7A Active CN109740247B (en) | 2018-12-29 | 2018-12-29 | IP and EFPGA port connection method and optimization method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109740247B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111224727B (en) * | 2020-04-24 | 2020-07-31 | 成都坤恒顺维科技股份有限公司 | Method for realizing self-adaptive topological structure based on channel simulator |
| CN111859827B (en) * | 2020-06-29 | 2022-06-17 | 山东云海国创云计算装备产业创新中心有限公司 | Chip IP integration method and device, electronic equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7890917B1 (en) * | 2008-01-14 | 2011-02-15 | Xilinx, Inc. | Method and apparatus for providing secure intellectual property cores for a programmable logic device |
| CN102184148A (en) * | 2011-04-18 | 2011-09-14 | 北京航空航天大学 | AT96 bus controller IP (internet protocol) core based on FPGA (field programmable gate array) and construction method thereof |
| CN102279838A (en) * | 2011-08-31 | 2011-12-14 | 公安部第三研究所 | System architecture reconfiguring method based on uniform hardware task interface |
| CN103258067A (en) * | 2012-02-20 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Method for keeping architecture, software and hardware conforming in configurable chip operating system |
| CN106528927A (en) * | 2016-09-29 | 2017-03-22 | 北京深维科技有限公司 | Input output I/O process mapping method and device |
-
2018
- 2018-12-29 CN CN201811641453.7A patent/CN109740247B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7890917B1 (en) * | 2008-01-14 | 2011-02-15 | Xilinx, Inc. | Method and apparatus for providing secure intellectual property cores for a programmable logic device |
| CN102184148A (en) * | 2011-04-18 | 2011-09-14 | 北京航空航天大学 | AT96 bus controller IP (internet protocol) core based on FPGA (field programmable gate array) and construction method thereof |
| CN102279838A (en) * | 2011-08-31 | 2011-12-14 | 公安部第三研究所 | System architecture reconfiguring method based on uniform hardware task interface |
| CN103258067A (en) * | 2012-02-20 | 2013-08-21 | 京微雅格（北京）科技有限公司 | Method for keeping architecture, software and hardware conforming in configurable chip operating system |
| CN106528927A (en) * | 2016-09-29 | 2017-03-22 | 北京深维科技有限公司 | Input output I/O process mapping method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109740247A (en) | 2019-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109740247B (en) | IP and EFPGA port connection method and optimization method thereof | |
| US10242146B2 (en) | Method and apparatus for placing and routing partial reconfiguration modules | |
| KR100887523B1 (en) | Allocation of combined or separate data and control planes | |
| CN102546435B (en) | A kind of frequency spectrum resource allocation method and device | |
| US8201130B1 (en) | Parallel signal routing | |
| CN105808328A (en) | Task scheduling method, device and system | |
| KR102552954B1 (en) | Computing system and method for operating computing system | |
| WO2016107421A1 (en) | Reconstruction method and apparatus for programmable logic device | |
| US8473881B1 (en) | Multi-resource aware partitioning for integrated circuits | |
| CN109670268B (en) | Method for connecting multiple IP and EFPGA ports | |
| US20230409799A1 (en) | Simultaneous placement and routing based method and apparatus for incremental design optimization, and computer device | |
| CN104765701A (en) | Data access method and device | |
| US20160335383A1 (en) | Area-efficient memory mapping techniques for programmable logic devices | |
| US9792395B1 (en) | Memory utilization in a circuit design | |
| CN109729731B (en) | Accelerated processing method and device | |
| CN100455131C (en) | Band-width resource distribution | |
| CN105760310A (en) | Address assignment method and DDR controller | |
| CN113836846B (en) | Integrated circuit pessimistic path analysis method for GPU (graphics processing Unit) accelerated computation | |
| CN203747793U (en) | Two-dimensional extendable cascade structure for multiplexer | |
| CN115496023A (en) | FPGA (field programmable Gate array) design method based on block design | |
| CN114297959A (en) | FPGA wiring method for improving wiring efficiency by splitting line network | |
| CN103746686A (en) | Two-dimensional extendable cascade structure for multiplexer | |
| CN112102860A (en) | Connection method of storage unit and processor | |
| JP6705401B2 (en) | Information processing apparatus, information processing apparatus control method, and information processing apparatus control program | |
| CN106385385B (en) | Resource allocation method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |