CN109709735A - Pixel arrangement structure, display panel and preparation method thereof - Google Patents
Pixel arrangement structure, display panel and preparation method thereof Download PDFInfo
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- CN109709735A CN109709735A CN201910173321.4A CN201910173321A CN109709735A CN 109709735 A CN109709735 A CN 109709735A CN 201910173321 A CN201910173321 A CN 201910173321A CN 109709735 A CN109709735 A CN 109709735A
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Abstract
The invention discloses a kind of pixel arrangement structures, including multi-strip scanning line；Multiple data lines；Multiple sub-pixels, it is limited and is formed by multi-strip scanning line and multiple data lines mutually insulated intersection, each sub-pixel is connected by TFT with corresponding scan line and data line, and each sub-pixel being connected with same data line is arranged alternately along data line direction in data line two sides；The each sub-pixel being connected with same data line includes the sub-pixel of tri- kinds of colors of R, G, B, and with every six sub-pixels be unit along data line direction repeated arrangement, six sub-pixels in unit include two adjacent R sub-pixels, two adjacent G sub-pixels and two adjacent B sub-pixels.Pixel arrangement structure provided by the invention reduces the display power consumption under Z-type column inversion mode, has saved cost by the arrangement mode of change R/G/B color blocking.The invention also discloses a kind of display panels and preparation method thereof.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of pixel arrangement structure, display panel and its production side
Method.
Background technique
As increasingly maturation, requirement of the people to image quality and power consumption of panel display technologies development are higher and higher.Exist at present
On inversion mode, including frame is driven reverse (frame inversion), line inversion driving (row inversion), column inversion drive
Dynamic (column inversion) and dot inversion driving (dot inversion).Wherein dot inversion driving is that display effect is best
Driving method.But during the display of every frame (frame) picture, dot inversion driving needs the polarity of voltage on data line
It is continually changed between positive polarity (+) and negative polarity (-), therefore the power consumption of dot inversion driving is maximum.In the prior art, mostly
Using column inversion or the driving method of Z-type column inversion (column&Z), wherein Z-type column inversion is able to achieve the display effect of dot inversion
Fruit, and each sub-pixel polarity having the same (electrode line or negative polarity) being connected with same data line, it is anti-lower than point
The power consumption turned can be cancelled out each other by the coupling that data line generates, and Vcom (reference voltage of liquid crystal molecule deflection) is relatively more stable,
Flashing (flicker) and crosstalk (crosstalk) phenomenon will weaken.
Fig. 1 is a kind of equivalent circuit diagram of existing Z-type column inversion driving, as shown in Figure 1, the Z-type column inversion pixel arrangement
Structure includes multi-strip scanning line 11 and multiple data lines 12, and scan line 11 and data line 12 intersect to form multiple sub-pixels
(sub-pixel) 14, each sub-pixel 14 is connected by TFT 13 with corresponding scan line 11 and data line 12.These sub-pixels
14 include R sub-pixel, G sub-pixel and B sub-pixel, and the column sub-pixel 14 between adjacent two datas line 12 has phase
Same color (as R sub-pixel, G sub-pixel or B sub-pixel).A sub- picture of column such as between adjacent two datas line D1, D2
Element 14 is R sub-pixel, and the column sub-pixel 14 between adjacent two datas line D2, D3 is G sub-pixel, is located at adjacent two
A column sub-pixel 14 between data line D3, D4 is B sub-pixel.
Under power consumption, such as pure color R/G/B picture, to the power consumption P=1/2 of Z-type column inversion than in the prior art
(CdataNxNy*2)V2(fNy) and column inversion power consumption P=1/2 (CdataNxNy)U2F, (N is resolution ratio, C in formuladataIt is one
Sub-pixel capacitor, f are the frequency of a frame picture, and U/V is that data line voltage changes, if select U as two times of liquid crystal voltages, V is
For liquid crystal voltage), the voltage switching times in a frame time on data line 12 are Ny(wherein NyFor scanning line number), calculating can
Know that Z-type column inversion power consumption is the N of column inversiony/ 2 times, and so under colour picture the power consumption of Z-type column inversion will be greater than column inversion
The power consumption of mode.And using the pixel arrangements of above-mentioned Z-type column inversion, due to being in the sub-pixel of left column and right column
Respectively R sub-pixel and B sub-pixel, this arrangement mode can also be easy to cause that display panel edge is rubescent, the problem of turning blue.
In order to reduce power consumption, industry generallys use following manner:
(1) Display panel frequency is reduced, but waiting time too long pixel electric leakage will lead to scintillation；
(2) double grid framework is used, reduces by a source line, but double grid framework reduces pixel aperture ratio；
(3) positivity liquid crystal (positivity liquid crystal drive voltage is lower) is used, but positivity LCD penetration is small.
Above-mentioned solution needs a kind of new solution still there are many deficiencies to reduce power consumption.
Summary of the invention
The purpose of the present invention is to provide a kind of pixel arrangement structures, display panel and preparation method thereof, by changing R/
The arrangement mode of G/B color blocking reduces the display power consumption under Z-type column inversion mode, has saved cost.
The present invention provides a kind of pixel arrangement structure, comprising:
Multi-strip scanning line；
Multiple data lines；
Multiple sub-pixels are limited and are formed by a plurality of scan line and a plurality of data line mutually insulated intersection, each
The sub-pixel is connected by TFT with the corresponding scan line and the data line, is connected with data line described in same
Each sub-pixel is arranged alternately along the data line direction in the data line two sides；
The each sub-pixel being connected with the same data line includes the sub-pixel of tri- kinds of colors of R, G, B, and with
Every six sub-pixels are unit along data line direction repeated arrangement, six sub- pictures in the unit
Element includes two adjacent R sub-pixels, two adjacent G sub-pixels and two adjacent B sub-pixels.
Further, six sub-pixels in the unit are arranged one of as follows:
(1)R,R,G,G,B,B；
(2)G,G,B,B,R,R；
(3)B、B、R、R、G、G。
Further, multiple arrangement of subpixels are at multirow and multiple row, per in sub-pixel described in adjacent two rows up and down,
The sub-pixel and the data line being located between adjacent two data line Dx, the D (x+1) in sub-pixel described in middle a line
D (x+1) is connected, the sub-pixel being located between adjacent two data line Dx, the D (x+1) in sub-pixel described in another row
It is connected with the data line Dx, wherein x is positive integer, and 1≤x≤(n-1), n are the total number of the data line.
Further, for the sub-pixel of odd-numbered line, it is located at described between adjacent two data line Dx, the D (x+1)
Sub-pixel is connected with the data line D (x+1)；For the sub-pixel of even number line, be located at the adjacent two data line Dx,
The sub-pixel between D (x+1) is connected with the data line Dx.
Further, for the sub-pixel of odd-numbered line, it is located between adjacent two data line Dx, the D (x+1)
The sub-pixel is connected with the data line Dx；For the sub-pixel of even number line, be located at the adjacent two data line Dx,
The sub-pixel between D (x+1) is connected with the data line D (x+1).
Further, each sub-pixel in every a line is connected in scan line described in same.
The present invention also provides a kind of display panels, including above-mentioned pixel arrangement structure.
The present invention also provides a kind of production methods of display panel, including make thin-film transistor array base-plate, wherein institute
Thin-film transistor array base-plate is stated equipped with multi-strip scanning line and multiple data lines, by a plurality of scan line and a plurality of number
Intersect to limit according to line mutually insulated and form multiple sub-pixels, each sub-pixel passes through TFT and corresponding scan line and data
Line is connected, and each sub-pixel being connected with data line described in same is arranged alternately along the data line direction described
Data line two sides；
Colored filter substrate is made, wherein the colored filter substrate is equipped with black matrix and by a variety of different colours
The color blocking array that is formed of color blocking material, the color blocking array arranges according to certain rule, so that by the colorized optical filtering
Plate base is corresponding with the thin-film transistor array base-plate when being grouped together into display panel, with data line described in same
Connected each sub-pixel includes the sub-pixel of tri- kinds of colors of R, G, B, and with every six sub-pixels for a unit
Along data line direction repeated arrangement, six sub-pixels in the unit include two adjacent R sub-pixels, two
A adjacent G sub-pixel and two adjacent B sub-pixels.
Further, six sub-pixels in the unit are arranged one of as follows:
(1)R,R,G,G,B,B；
(2)G,G,B,B,R,R；
(3)B、B、R、R、G、G。
Further, multiple arrangement of subpixels are at multirow and multiple row, per in sub-pixel described in adjacent two rows up and down,
The sub-pixel and the data line being located between adjacent two data line Dx, the D (x+1) in sub-pixel described in middle a line
D (x+1) is connected, the sub-pixel being located between adjacent two data line Dx, the D (x+1) in sub-pixel described in another row
It is connected with the data line Dx, wherein x is positive integer, and 1≤x≤(n-1), n are the total number of the data line.
Pixel arrangement structure provided by the invention passes through the arrangement mode for changing R/G/B color blocking, using two adjacent R
Pixel, two adjacent G sub-pixels and two adjacent B sub-pixels are the arrangement mode of a unit, in display pure color picture
When, voltage switching times be conventional architectures under 1/3, thus reduce pure color picture display when power consumption, and so on colour
The power consumption of picture can also reduce, and efficiently solve Z-type column inversion framework power consumption when showing R/G/B pure color picture and colour picture
Big problem has saved cost, and the sub-pixel of each column arrangement of the pixel arrangement structure is the mixing row of R, G, B color blocking
Column mode, moreover it is possible to avoid that display panel edge is rubescent, the phenomenon that turning blue.
Detailed description of the invention
Fig. 1 is a kind of equivalent circuit diagram of existing Z-type column inversion driving；
Fig. 2 is the equivalent circuit diagram of pixel arrangement structure in the embodiment of the present invention；
Fig. 3 is the equivalent circuit diagram of pixel arrangement structure in another embodiment of the present invention；
Fig. 4 is the data line signal waveform diagram of pixel arrangement structure in the embodiment of the present invention.
Specific embodiment
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.Implement below
Example is not intended to limit the scope of the invention for illustrating the present invention.
Fig. 2 is the equivalent circuit diagram of pixel arrangement structure in the embodiment of the present invention, as shown in Fig. 2, the pixel arrangement structure
Including multi-strip scanning line 11 (only illustrating G1~G6 in figure), multiple data lines 12 (only indicating D1~D10 in figure) and by a plurality of
Scan line 11 and 12 mutually insulated of multiple data lines intersect the multiple sub-pixels 24 for limiting and being formed, and each sub-pixel 24 passes through
TFT23 is connected with corresponding scan line 11 and data line 12, and each sub-pixel 24 being connected with same data line 12 is along number
It is arranged alternately according to line direction in data line two sides.
The each sub-pixel 24 being connected with same data line 12 includes the sub-pixel 24 of tri- kinds of colors of R, G, B, and with every
Six sub-pixels 24 are a unit along 12 direction repeated arrangement of data line, and six sub-pixels 24 in unit include two phases
Adjacent R sub-pixel, two adjacent G sub-pixels and two adjacent B sub-pixels.
The present invention is applied to Z-type column inversion and drives, show that its power consumption is P=1/ by changing R/G/B color blocking arrangement mode
2(CdataNxNy*3)V2(fNy* 1/3)=1/2 (CdataNxNy)V2(fNy), (N is resolution ratio, C in formuladataFor a sub-pixel
Capacitor, f be a frame picture frequency, U/V be 12 voltage change of data line, if select U be two times of liquid crystal voltages when, V is liquid
Brilliant voltage), compare pure color picture power consumption P=1/2 (C under existing framework color blocking arrangement modedataNxNy*2)V2(fNy) it is found that its
On the basis of his picture power consumption is constant, the power consumption of the pure color picture R/G/B of pixel arrangements provided by the invention is existing sets
The half of meter.
Specifically, six sub-pixels 24 in unit are arranged one of as follows: R, R, G, G, B, B；
G,G,B,B,R,R；B,B,R,R,G,G.For example, the arrangement mode for the sub-pixel 24 that scan line G1~G6 is connected with data line D2 is
R,R,G,G,B,B；The arrangement mode for the sub-pixel 24 that scan line G1~G6 is connected with data line D3 is G, G, B, B, R, R；Scanning
The arrangement mode for the sub-pixel 24 that line G1~G6 is connected with data line D4 is B, B, R, R, G, G.
Multiple sub-pixel 24 is arranged in multirow and multiple row, per adjacent up and down in two row sub-pixels 24, wherein a line picture
Sub-pixel 24 in element 24 between adjacent two datas line Dx, D (x+1) is connected with data line D (x+1), another row picture
Sub-pixel 24 in element 24 between adjacent two datas line Dx, D (x+1) is connected with data line Dx, and wherein x is positive integer,
And 1≤x≤(n-1).
In other words, for the column sub-pixel 24 between adjacent two datas line 12, it is in the son of odd positions
Pixel 24 is connected with the wherein data line 12 in the two datas line 12, is in the sub-pixel 24 of even number position and this two
Another data line 12 in data line 12 is connected.
To which each sub-pixel 24 being connected with same data line 12 is arranged alternately along 12 direction of data line in the number
According to 12 two sides of line, each sub-pixel 24 being connected with same data line 12 has identical polar (electrode line or negative polarity), because
This, the pixel arrangement structure of the present embodiment can take the driving method of column inversion (column inversion) in driving
It realizes the display effect of dot inversion (dot inversion), does not need to carry out frequent polarity switching, advantageously reduce driving
Power consumption.
In the present embodiment, as shown in Fig. 2, being directed to the sub-pixel 24 of odd-numbered line (G1, G3, G5......), it is located at adjacent
Sub-pixel 24 between two data line Dx, D (x+1) is connected with data line D (x+1)；For even number line (G2, G4,
G6...... sub-pixel 24), the sub-pixel 24 between adjacent two datas line Dx, D (x+1) are connected with data line Dx.
Specifically, the sub-pixel 24 in the sub-pixel 24 of scan line G1 and G3, between adjacent two datas line D1, D2
It is connected with data line D2, the sub-pixel 24 between adjacent two datas line D2, D3 is connected with data line D3, is located at adjacent two
Sub-pixel 24 between data line D3, D4 is connected with data line D4, and the rest may be inferred by analogy；In the sub-pixel 24 of scan line G2 and G4,
Sub-pixel 24 between adjacent two datas line D1, D2 is connected with data line D1, be located at adjacent two datas line D2, D3 it
Between sub-pixel 24 be connected with data line D2, the sub-pixel 24 between adjacent two datas line D3, D4 and data line D3 phase
Even, the rest may be inferred by analogy.
Fig. 3 is the equivalent circuit diagram of pixel arrangement structure in another embodiment of the present invention, as shown in figure 3, in another reality
It applies in example, the son for the sub-pixel 24 of odd-numbered line (G1, G3, G5 ...), between adjacent two datas line Dx, D (x+1)
Pixel 24 is connected with data line Dx；For the sub-pixel 24 of even number line (G2, G4, G6......), it is located at adjacent two datas line
Sub-pixel 24 between Dx, D (x+1) is connected with data line D (x+1).
Specifically, the sub-pixel 24 in the sub-pixel 24 of scan line G1 and G3, between adjacent two datas line D1, D2
It is connected with data line D1, the sub-pixel 24 between adjacent two datas line D2, D3 is connected with data line D2, is located at adjacent two
Sub-pixel 24 between data line D3, D4 is connected with data line D3, and the rest may be inferred by analogy；In the sub-pixel 24 of scan line G2 and G4,
Sub-pixel 24 between adjacent two datas line D1, D2 is connected with data line D2, be located at adjacent two datas line D2, D3 it
Between sub-pixel 24 be connected with data line D3, the sub-pixel 24 between adjacent two datas line D3, D4 and data line D4 phase
Even, the rest may be inferred by analogy.
Since each sub-pixel 24 being connected with same data line 12 includes the sub-pixel 24 of tri- kinds of colors of R, G, B, and
Every six sub-pixels 24 are a unit, six sub-pixels 24 in unit include two adjacent R sub-pixels, two it is adjacent
G sub-pixel and two adjacent B sub-pixels, along 12 direction repeated arrangement of data line, when showing pure color picture, such as Fig. 4
Shown, the voltage switching times in a frame time on data line 12 are Ny/ 3 (wherein NyFor scanning line number), with conventional architectures
Voltage switching times are NyCompared to reducing, the power consumption of pure color picture is also reduced therewith, and so on colour picture power consumption
It can reduce.Such as when being displayed in red picture, in scan line G1~G6, the R sub-pixel being connected with every data line 12 accounts for one
The 1/3 of unit, and be two adjacent R sub-pixels of same polarity, R sub-pixel is opened, remaining G sub-pixel and B sub-pixel are closed,
The voltage switching times of every data line 12 are the 1/3 of total scanning line number, to more save power consumption when showing pure color picture.
The embodiment of the present invention also provides a kind of display panel, including above-mentioned pixel arrangement structure.The display panel is specific
It can be liquid crystal display panel, which includes thin-film transistor array base-plate, colored filter substrate and set
Set the liquid crystal layer between thin-film transistor array base-plate and colored filter substrate.
The embodiment of the present invention also provides a kind of production method of display panel, including production thin-film transistor array base-plate,
Wherein thin-film transistor array base-plate is equipped with multi-strip scanning line 11 and multiple data lines 12, by multi-strip scanning line 11 and a plurality of number
Intersect to limit according to 12 mutually insulated of line and form multiple sub-pixels 24, each sub-pixel 24 passes through TFT23 and corresponding scan line 11
It is connected with data line 12, each sub-pixel 24 being connected with same data line 12 is arranged alternately along 12 direction of data line in number
According to 12 two sides of line；
Colored filter substrate is made, wherein colored filter substrate is equipped with black matrix and the color by a variety of different colours
The color blocking array that material is formed is hindered, color blocking array is arranged according to certain rule, so that by colored filter substrate and film
Transistor (TFT) array substrate is corresponding when being grouped together into display panel, each sub-pixel 24 being connected with same data line 12
Sub-pixel 24 including tri- kinds of colors of R, G, B, and be that a unit is repeated along 12 direction of data line with every six sub-pixels 24
It arranges, six sub-pixels 24 in unit include two adjacent R sub-pixels, two adjacent G sub-pixels and two adjacent B
Sub-pixel.
Specifically, six sub-pixels 24 in unit are arranged one of as follows:
(1)R,R,G,G,B,B；
(2)G,G,B,B,R,R；
(3)B、B、R、R、G、G。
Multiple sub-pixel 24 is arranged in multirow and multiple row, per adjacent up and down in two row sub-pixels 24, wherein a line picture
Sub-pixel 24 in element 24 between adjacent two datas line Dx, D (x+1) is connected with data line D (x+1), another row picture
Sub-pixel 24 in element 24 between adjacent two datas line Dx, D (x+1) is connected with data line Dx, and wherein x is positive integer,
And 1≤x≤(n-1), n are the total number of data line 12.
Pixel arrangement structure provided by the above embodiment is adjacent using two by changing the arrangement mode of R/G/B color blocking
R sub-pixel, two adjacent G sub-pixels and two adjacent B sub-pixels be a unit arrangement mode, display pure color
When picture, voltage switching times are 1/3 under conventional architectures, power consumption P=1/2 (C in a frame timedataNxNy)V2(fNy) be
The half of conventional architectures power consumption, to reduce the power consumption when display of pure color picture, and so on the power consumption of colour picture also can
It reduces, efficiently solves the problems, such as that Z-type column inversion framework power consumption when showing R/G/B pure color picture and colour picture is big, save
Cost.The driving method that display panel can use column inversion (column inversion) realizes dot inversion (dot
Inversion display effect) advantageously reduces the overall power of display panel, improves the display quality of picture.
Also, above-mentioned pixel arrangement structure is used, the sub-pixel 24 of each column arrangement is the mixing arrangement of R, G, B color blocking
Mode, for being located at the sub-pixel 24 of the pixel arrangement structure left column and right column, in the present embodiment, i.e. data line D1
With among D2 sub-pixel 24 and data line D9 and D10 among sub-pixel 24, color blocking arrangement mode be respectively R, B, G, R,
B, G..... and B, G, R, B, G, R......, R, G, B color blocking arrangement mode avoid conventional architectures and are in left column and most right
The sub-pixel 24 of column is respectively that R sub-pixel and B sub-pixel can bring display panel edge be rubescent, the problem of turning blue.
More than, it is only presently preferred embodiments of the present invention, is not intended to limit the present invention in any form, although this
Invention has been disclosed in a preferred embodiment above, and however, it is not intended to limit the invention, any person skilled in the art,
It does not depart within the scope of technical solution of the present invention, when the technology contents using the disclosure above make a little change or are modified to equivalent
The equivalent embodiment of variation, but without departing from the technical solutions of the present invention, according to the technical essence of the invention to the above reality
Any simple modification, equivalent change and modification made by example are applied, all of which are still within the scope of the technical scheme of the invention.
Claims (10)
1. a kind of pixel arrangement structure, comprising:
Multi-strip scanning line (11)；
Multiple data lines (12)；
Multiple sub-pixels (24) limit shape by a plurality of scan line (11) and a plurality of data line (12) mutually insulated intersection
At, each sub-pixel (24) is connected by TFT (23) with the corresponding scan line (11) and the data line (12), with
The connected each sub-pixel (24) of data line described in same (12) is arranged alternately along the data line (12) direction
Data line (12) two sides；
It is characterized in that, each sub-pixel (24) being connected with data line described in same (12) includes tri- kinds of face of R, G, B
The sub-pixel (24) of color, and be that a unit repeats to arrange along the data line (12) direction with every six sub-pixels (24)
It arranges, six sub-pixels (24) in the unit include two adjacent R sub-pixels, two adjacent G sub-pixels and two
A adjacent B sub-pixel.
2. pixel arrangement structure as described in claim 1, which is characterized in that six sub-pixels (24) in the unit
It is arranged one of as follows:
(1)R,R,G,G,B,B；
(2)G,G,B,B,R,R；
(3)B、B、R、R、G、G。
3. pixel arrangement structure as described in claim 1, which is characterized in that multiple sub-pixels (24) be arranged in multirow with
Multiple row is wherein located at described in adjacent two in sub-pixel described in a line (24) per in sub-pixel (24) described in adjacent two rows up and down
The sub-pixel (24) between data line Dx, D (x+1) is connected with the data line D (x+1), sub-pixel described in another row
(24) sub-pixel (24) being located between adjacent two data line Dx, the D (x+1) in is connected with the data line Dx,
Wherein x is positive integer, and 1≤x≤(n-1), n are the total number of the data line (12).
4. pixel arrangement structure according to claim 3, which is characterized in that for the sub-pixel (24) of odd-numbered line,
The sub-pixel (24) between adjacent two data line Dx, the D (x+1) is connected with the data line D (x+1)；Needle
Several rows of antithesis of the sub-pixel (24), the sub-pixel (24) being located between adjacent two data line Dx, the D (x+1)
It is connected with the data line Dx.
5. pixel arrangement structure according to claim 3, which is characterized in that for the sub-pixel (24) of odd-numbered line,
The sub-pixel (24) between adjacent two data line Dx, the D (x+1) is connected with the data line Dx；For idol
Several rows of the sub-pixel (24) is located at the sub-pixel (24) between adjacent two data line Dx, the D (x+1) and institute
Data line D (x+1) is stated to be connected.
6. pixel arrangement structure according to claim 1, which is characterized in that each sub-pixel (24) in every a line
It is connected on scan line described in same (11).
7. a kind of display panel, which is characterized in that including pixel arrangement structure such as claimed in any one of claims 1 to 6.
8. a kind of production method of display panel characterized by comprising
Thin-film transistor array base-plate is made, wherein the thin-film transistor array base-plate is equipped with multi-strip scanning line (11) and more
Data line (12), by a plurality of scan line (11) and a plurality of data line (12) mutually insulated intersection limit formed it is multiple
Sub-pixel (24), each sub-pixel (24) pass through TFT (23) and the corresponding scan line (11) and the data line
(12) it is connected, each sub-pixel (24) being connected with data line described in same (12) is along the data line (12) direction
It is arranged alternately in the data line (12) two sides；
Colored filter substrate is made, wherein the colored filter substrate is equipped with black matrix and the color by a variety of different colours
The color blocking array that material is formed is hindered, the color blocking array is arranged according to certain rule, so that by the colorized optical filtering chip base
Plate is corresponding with the thin-film transistor array base-plate when being grouped together into display panel, with data line described in same (12)
Connected each sub-pixel (24) includes the sub-pixel (24) of tri- kinds of colors of R, G, B, and with every six sub-pixels
(24) six sub-pixels (24) packets for being unit along the data line (12) direction repeated arrangement, in the unit
Include two adjacent R sub-pixels, two adjacent G sub-pixels and two adjacent B sub-pixels.
9. the production method of display panel according to claim 8, which is characterized in that six sons in the unit
Pixel (24) is arranged one of as follows:
(1)R,R,G,G,B,B；
(2)G,G,B,B,R,R；
(3)B、B、R、R、G、G。
10. the production method of display panel according to claim 8, which is characterized in that multiple sub-pixel (24) rows
Multirow and multiple row are arranged into, per in sub-pixel (24) described in adjacent two rows up and down, phase is wherein located in sub-pixel described in a line (24)
The sub-pixel (24) between adjacent two data line Dx, the D (x+1) is connected with the data line D (x+1), another row institute
State the sub-pixel (24) and the data line being located between adjacent two data line Dx, the D (x+1) in sub-pixel (24)
Dx is connected, and wherein x is positive integer, and 1≤x≤(n-1), n are the total number of the data line (12).
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| CN111061106A (en) * | 2020-01-02 | 2020-04-24 | 福州京东方光电科技有限公司 | Array substrate and display panel |
| CN111862830A (en) * | 2020-07-23 | 2020-10-30 | 福建华佳彩有限公司 | SPR display device |
| CN112068374A (en) * | 2020-09-15 | 2020-12-11 | 昆山龙腾光电股份有限公司 | Display panel, display device and driving method |
| CN112216219A (en) * | 2019-07-09 | 2021-01-12 | 成都辰显光电有限公司 | Pixel arrangement structure, display panel and display device |
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