CN109698198A - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
- Publication number
- CN109698198A CN109698198A CN201710995782.0A CN201710995782A CN109698198A CN 109698198 A CN109698198 A CN 109698198A CN 201710995782 A CN201710995782 A CN 201710995782A CN 109698198 A CN109698198 A CN 109698198A
- Authority
- CN
- China
- Prior art keywords
- fin
- ion
- ion implanting
- semiconductor substrate
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 40
- 238000009792 diffusion process Methods 0.000 claims abstract description 27
- 230000003139 buffering effect Effects 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims description 89
- -1 carbon ion Chemical class 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 53
- 229910052799 carbon Inorganic materials 0.000 claims description 32
- 229910052732 germanium Inorganic materials 0.000 claims description 24
- 238000002347 injection Methods 0.000 claims description 24
- 239000007924 injection Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 18
- 230000008569 process Effects 0.000 description 16
- 239000012212 insulator Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000031709 bromination Effects 0.000 description 1
- 238000005893 bromination reaction Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000012046 mixed solvent Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, which comprises provides semiconductor substrate, forms multiple fins on the semiconductor substrate；Isolation structure is formed in gap between the fin, the top surface of the isolation structure is lower than the top surface of the fin, to expose a part of the fin；First ion implanting is executed to the side wall of the fin of exposing；The side wall for the fin that etching removal part is exposed, to reduce the width of the exposed portion of the fin；Second ion implanting is executed to the fin of exposing, to form buffering diffusion layer in the fin.The production method of the semiconductor devices provided according to the present invention, etching removes the side wall for the fin that part is exposed to reduce its width after executing the first ion implanting by the side wall to fin, then the second ion implanting is executed to form buffering diffusion layer in the fin to the fin of exposing, to overcome short-channel effect, Exchange Settlement is avoided to reveal, the performance and yield of semiconductor devices are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof.
Background technique
Main devices metal-with the development of semiconductor technology, in integrated circuit especially super large-scale integration
The geometric dimension of Oxide-Semiconductor Field effect transistor (MOSFET) is constantly reducing always, the feature ruler of semiconductor devices
It is very little to have narrowed down to Nano grade.Semiconductor devices is under this characteristic size, the method for conventional planar production semiconductor devices
It can not be applicable in.Then there has been proposed various novel semiconductor device structures, wherein fin formula field effect transistor
It (FinFET) is advanced semiconductor device structure for 22nm and following process node, relative to existing planar transistor,
FinFET has more superior performance in terms of channel controls and reduces.
However as fin formula field effect transistor (FinFET) critical dimension reduction to 7nm~14nm process node, it is short
Channelling effect (SCE) is increasingly severe, also becomes its increasing challenge to the control of short-channel effect using doping process.
In order to overcome this problem, various manufacturing process are attempted in semiconductor fabrication, such as ultra-shallow junctions, abrupt junction, pre-amorphous note
Enter (PAI), stress technique etc. for optimizing LDD and halo doping profile to improve device performance, but in performance and short channel
Balance is obtained between effect increasingly becomes a big problem, meanwhile, these methods cannot all completely eliminate short-channel effect.This
Outside, FinFET is separated between each fin using isolation structure, in order to preferably overcome short-channel effect to mention
Being isolated between high fin and between fin and substrate, although this can further overcome short-channel effect, due to fin
The doping concentration of piece is higher than substrate, and for the ease of being subsequently formed contact, fin source-drain electrode meeting selective epitaxy technique is to grow
The source-drain electrode of biggish contact area is formed, in this way since substrate area doping concentration corresponding below fin is low, is be easy to cause
Diffusion from top to bottom results in knot leakage problem.
Therefore, it is necessary to which the production method for proposing a kind of new semiconductor devices, above-mentioned to solve the problems, such as.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention provides a kind of production method of semiconductor devices, comprising the following steps:
Semiconductor substrate is provided, forms multiple fins on the semiconductor substrate；
Isolation structure is formed in gap between the fin, the top surface of the isolation structure is lower than the top of the fin
Face, to expose a part of the fin；
First ion implanting is executed to the side wall of the fin of exposing；
The side wall for the fin that etching removal part is exposed, to reduce the width of the exposed portion of the fin；
Second ion implanting is executed to the fin of exposing, to form buffering diffusion layer in the fin.
Further, the step of forming multiple fins on the semiconductor substrate include:
The hard mask layer with fin pattern is formed on the semiconductor substrate；
The part semiconductor substrate is removed by mask etch of the hard mask layer, to form multiple fins.
Further, the step of forming the isolation structure in the gap between the fin include:
Depositing isolation material layer, with the gap being filled up completely between the fin；
It is etched back to the spacer material layer, to form isolation structure.
It further, further include removing the hard mask layer and execution third ion implanting after executing the second ion implanting
The step of with adjusting threshold voltage.
Further, the ion of first ion implanting injection include carbon ion and boron ion or carbon ion and phosphorus from
Son.
Further, the implant angle of first ion implanting is 0 °~5 °, the energy of ion implanting be 5keV~
20keV, the dosage of ion implanting are 5E12atom/cm2~5E13atom/cm2。
Further, the ion of the second ion implanting injection includes carbon ion and Nitrogen ion, germanium ion and Nitrogen ion, carbon
Ion and germanium ion, carbon ion or germanium ion.
Further, the implant angle of second ion implanting is 10 °~20 °, the energy of ion implanting be 5keV~
20keV, the dosage of ion implanting are 5E13atom/cm2~5E14atom/cm2。
Further, the buffering diffusion layer is formed in the bottom of the fin exposed portion and on the side wall of bottom.
Further, the side wall for the fin that removal part is exposed is etched using wet-etching technology.
The present invention also provides a kind of semiconductor devices, comprising:
Semiconductor substrate is formed with multiple fins in the semiconductor substrate；
Isolation structure is formed in gap between the fin, the top surface of the isolation structure is lower than the top of the fin
Face, to expose a part of the fin；
The width of the fin exposed portion is less than the width of non-exposed portion；
Buffering diffusion layer is formed in the fin.
Further, the Doped ions of the buffering diffusion layer include carbon ion and Nitrogen ion, germanium ion and Nitrogen ion, carbon from
Son and germanium ion, carbon ion or germanium ion.
Further, the buffering diffusion layer is formed in the bottom of the fin exposed portion and on the side wall of bottom.
The production method of the semiconductor devices provided according to the present invention executes the first ion implanting by the side wall to fin
The side wall for the fin that etching removal part is exposed afterwards to reduce its width, then to the fin of exposing execute second from
Son injection improves semiconductor to overcome short-channel effect, Exchange Settlement is avoided to reveal to form buffering diffusion layer in the fin
The performance and yield of device.
Detailed description of the invention
The embodiment of the present invention is described in more detail in conjunction with the accompanying drawings, the above and other purposes of the present invention,
Feature and advantage will be apparent.Attached drawing is used to provide to further understand the embodiment of the present invention, and constitutes explanation
A part of book, is used to explain the present invention together with the embodiment of the present invention, is not construed as limiting the invention.In the accompanying drawings,
Identical reference label typically represents same parts or step.
In attached drawing:
Fig. 1 is a kind of schematic flow chart of the production method of semiconductor devices according to an exemplary embodiment of the present invention.
Fig. 2A -2E is the device that the step of method according to an exemplary embodiment of the present invention is successively implemented obtains respectively
Schematic cross sectional view.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiments.
As the critical dimension reduction of fin formula field effect transistor (FinFET) is to 7nm~14nm process node, short channel
Effect (SCE) is increasingly severe, also becomes its increasing challenge to the control of short-channel effect using doping process.In order to
Overcome this problem, various manufacturing process are attempted in semiconductor fabrication, such as ultra-shallow junctions, abrupt junction, pre-amorphous injection
(PAI), stress technique etc. improves device performance for optimizing LDD and halo doping profile, but imitates in performance and short channel
Balance is obtained between answering increasingly becomes a big problem, meanwhile, these methods cannot all completely eliminate short-channel effect.This
Outside, FinFET is separated between each fin using isolation structure, in order to preferably overcome short-channel effect to mention
Being isolated between high fin and between fin and substrate, although this can further overcome short-channel effect, due to fin
The doping concentration of piece is higher than substrate, and for the ease of being subsequently formed contact, fin source-drain electrode meeting selective epitaxy technique is to grow
The source-drain electrode of biggish contact area is formed, in this way since substrate area doping concentration corresponding below fin is low, is be easy to cause
Diffusion from top to bottom results in knot leakage problem.
Therefore, it is necessary to which the production method for proposing a kind of new semiconductor devices, above-mentioned to solve the problems, such as.
In view of the above deficiencies, the present invention provides a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, forms multiple fins on the semiconductor substrate；
Isolation structure is formed in gap between the fin, the top surface of the isolation structure is lower than the top of the fin
Face, to expose a part of the fin；
First ion implanting is executed to the side wall of the fin of exposing；
The side wall for the fin that etching removal part is exposed, to reduce the width of the exposed portion of the fin；
Second ion implanting is executed to the fin of exposing, to form buffering diffusion layer in the fin.
Wherein, the step of forming multiple fins on the semiconductor substrate includes: to be formed on the semiconductor substrate
Hard mask layer with fin pattern；The part semiconductor substrate is removed by mask etch of the hard mask layer, to be formed
Multiple fins.The step of forming the isolation structure in gap between the fin includes: depositing isolation material layer, with complete
Gap between fin described in full packing；It is etched back to the spacer material layer, to form isolation structure.Executing the second ion note
Further include the steps that removing the hard mask layer after entering and executes third ion implanting with adjusting threshold voltage.Described first from
The ion of son injection injection includes carbon ion and boron ion or carbon ion and phosphonium ion.The injection of first ion implanting
Angle is 0 °~5 °, and the energy of ion implanting is 5keV~20keV, and the dosage of ion implanting is 5E12atom/cm2~
5E13atom/cm2.The ion of second ion implanting injection include carbon ion and Nitrogen ion, germanium ion and Nitrogen ion, carbon from
Son and germanium ion, carbon ion or germanium ion.The implant angle of second ion implanting is 10 °~20 °, the energy of ion implanting
Amount is 5keV~20keV, and the dosage of ion implanting is 5E13atom/cm2~5E14atom/cm2.The buffering diffusion layer is formed
On bottom in the fin exposed portion and the side wall close to bottom.Etch what removal part was exposed using wet-etching technology
The side wall of the fin.
The production method of the semiconductor devices provided according to the present invention executes the first ion implanting by the side wall to fin
The side wall for the fin that etching removal part is exposed afterwards to reduce its width, then to the fin of exposing execute second from
Son injection improves semiconductor to overcome short-channel effect, Exchange Settlement is avoided to reveal to form buffering diffusion layer in the fin
The performance and yield of device.
Below with reference to Fig. 1 and Fig. 2A -2E, wherein Fig. 1 is a kind of semiconductor devices according to an exemplary embodiment of the present invention
Production method schematic flow chart；Fig. 2A -2E is the step of method according to an exemplary embodiment of the present invention is successively implemented
The schematic cross sectional view of the device obtained respectively.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step packet of the preparation method
It includes:
Step S101: semiconductor substrate is provided, forms multiple fins on the semiconductor substrate；
Step S102: forming isolation structure in the gap between the fin, the top surface of the isolation structure is lower than institute
The top surface of fin is stated, to expose a part of the fin；
Step S103: the first ion implanting is executed to the side wall of the fin of exposing；
Step S104: the side wall for the fin that etching removal part is exposed, to reduce the exposed portion of the fin
Width；
Step S105: executing the second ion implanting to the fin of exposing, to form buffering diffusion in the fin
Layer.
In the following, being described in detail to the specific embodiment of the production method of semiconductor devices of the invention.
Firstly, executing step S101 provides semiconductor substrate 200 as shown in Figure 2 A, in the semiconductor substrate 200
Form multiple fins 202.
Illustratively, in the present invention the semiconductor substrate 200 can be in the following material being previously mentioned at least one
Kind: monocrystalline silicon, silicon-on-insulator (SOI), be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..In the present invention, the composition material of semiconductor substrate 200
Material selects monocrystalline silicon.
Then, the hard mask layer 201 with fin pattern is formed in the semiconductor substrate 200.
Illustratively, forming hard mask layer 201 on semiconductor substrate 200 can be familiar with using those skilled in the art
Various suitable techniques, such as chemical vapor deposition process.The hard mask layer 201 can be the oxidation being laminated from bottom to top
Nitride layer and silicon nitride layer, the present invention in, hard mask layer 201 be silicon nitride layer.The hard mask layer 201 is patterned, formation is used for
Semiconductor substrate 200 is etched to be formed on multiple exposure masks being isolated from each other of fin, in the present invention, using photoetching process
Implement the patterning process.
It then, is that mask etch removes the part semiconductor substrate 200 with the hard mask layer 201, it is multiple to be formed
Fin 202.
Illustratively, semiconductor substrate 200 can be etched using dry etch process or wet-etching technology.Wherein,
Dry method etch technology includes but is not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser are cut
It cuts.In the present invention, using plasma etching technics, the etching gas used is based on oxygen (O2- based) gas,
The range of flow of etching gas can be 50 cc/mins (sccm)~150 cc/min (sccm), in reaction chamber
Pressure can be 5 millitorrs (mTorr)~20 millitorr (mTorr).In addition, the etching gas of dry etching can also be bromination hydrogen
Body, carbon tetrafluoride gas or gas of nitrogen trifluoride.It should be noted that above-mentioned engraving method is only exemplary, not office
Limit and this method, those skilled in the art can also select other common methods.
Next, executing step S102, as shown in Figure 2 B, isolation structure 203, the isolation junction are formed in the gap
The top surface of structure 203 is lower than the top surface of the fin 202, to expose a part of the fin 202.Specifically, formed it is described every
It include: depositing isolation material layer 203 ' from the step of structure 203, with the gap being filled up completely between the fin 202；It is etched back to
The spacer material layer 203 ', to form isolation structure 203.The isolation structure 203 of formation can be shallow trench isolation (STI) knot
Structure.
Illustratively, the spacer material layer 203 ' can be any insulating materials with buffer action, such as aoxidize
Silicon, silicon oxynitride (SiON) etc., in the present invention, spacer material layer 203 ' are silicon oxide layer.Those skilled in the art can be used
Any deposition method known to member forms the spacer material layer 203 ', including but not limited to chemical vapour deposition technique (CVD), physics
Vapour deposition process (PVD) or atomic layer deposition method (ALD) etc..In the present invention, the chemical vapor deposition with flowability is selected
It is deposited described in product (FCVD) process implementing.Further, it the spacer material layer 203 ' fills up between fin 202 gap simultaneously overflows
Out, the top surface of post-depositional spacer material layer 203 ' is caused to be higher than the top surface of hard mask layer 201, therefore to spacer material layer 203 '
Surface planarized, flush the top surface of spacer material layer 203 ' and the top surface of hard mask layer 201, which can
To use chemical mechanical grinding (CMP) technique.
Illustratively, it is etched back to the spacer material layer 203 ', to form isolation structure 203, the isolation structure 203
Top surface is lower than the top surface of the fin 202, to expose a part of the fin 202.SiCoNi can be used by being etched back to technique
Etching or dry etching etc..Wherein, when carrying out SiCoNi etching, SiCoNi etching in situ or ex situ SiCoNi can be selected
Common dry etching can be used in dry etching by etching silicon of making a return journey；Also it can control etching intensity, use is low
The dry etching (soft dry etch) of bias low-power, to avoid excessive etching is caused to spacer material layer 203 '.It needs
What is illustrated is that above-mentioned engraving method is only exemplary, and limitation and this method, those skilled in the art can also not select
Other common methods.
Next, executing step S103, referring to Fig. 2 C, the first ion note is executed to the side wall of the fin 202 of exposing
Enter.
Illustratively, the ion that first ion implanting is injected into the side wall of 202 exposed portion of fin includes
Carbon ion and p-type doping ion (such as boron ion, gallium ion) or carbon ion and n-type doping ion (such as phosphonium ion, arsenic ion).
Specifically, in PMOS area, the injection ion of first ion implanting is carbon ion and boron ion, described in NMOS area
The injection ion of first ion implanting is carbon ion and phosphonium ion.Wherein, the implant angle of first ion implanting be 0 °~
5 °, the energy of ion implanting is 5keV~20keV, and the dosage of ion implanting is 5E12atom/cm2~5E13atom/cm2.Pass through
On the one hand the first ion implanting step improves the homogeneity and controllability of subsequent fin etch process, on the other hand, carbon
The injection of ion can inhibit the transient enhanced diffusion (TED) of silicon substrate intermediate ion, to overcome short-channel effect.
Next, step S104 is executed, the side wall for the fin 202 that etching removal part is exposed, to reduce the fin
The width of the exposed portion of piece 202.
Illustratively, the side wall of the exposed portion of the fin 202 is etched using wet-etching technology.It specifically, can be with
The silicon fin is etched using the mixed solvent of nitric acid and hydrofluoric acid, so as to reach target wide for the width of the fin 202 after etching
Degree.The width that fin 202 after etching is higher than the part (i.e. exposed portion) of 203 ' top surface of spacer material layer is less than lower than isolation
The width of the part (i.e. non-exposed portion) of 203 ' top surface of material layer, the fin 202 form " convex " font structure.
Next, executing step S105, as shown in Figure 2 D, the second ion implanting is executed to the fin 202 of exposing, with
Buffering diffusion layer 204 is formed in the fin 202.
Illustratively, be that exposure mask executes the second ion implanting to the fin 202 of exposing with hard mask layer 201, with
The bottom of 202 exposed portion of fin and the formation buffering diffusion layer 204 on the side wall of bottom.The second ion implanting injection
Ion include carbon ion and Nitrogen ion, germanium ion and Nitrogen ion, carbon ion and germanium ion, carbon ion or germanium ion.Specifically
Ground, being infused in FinFET for ion form buffering diffusion layer 204, to inhibit to be formed semiconductor substrate after source electrode and drain electrode
The horizontal proliferation of interior Doped ions (such as boron ion or phosphonium ion), to reduce short-channel effect.Wherein, second ion
The implant angle of injection is 10 °~20 °, and the energy of ion implanting is 5keV~20keV, and the dosage of ion implanting is
5E13atom/cm2~5E14atom/cm2.The injection depth of second ion implanting is 1nm~20nm, and concentration is
1E19atom/cm3~5E20atom/cm3。
Next, further including removing the hard mask layer 201, third ion implanting is executed with the step of adjusting threshold voltage
Suddenly.
Illustratively, hard mask layer 201 can be removed using dry etch process or wet-etching technology.Wherein, it does
Method etch process includes but is not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.
It should be noted that above-mentioned engraving method is only exemplary, limitation and this method, those skilled in the art can be with
Select other common methods.
Illustratively, third ion implanting is executed, with adjusting threshold voltage.The ion packet of the third ion implanting injection
Include n-type doping ion or p-type doping ion.Specifically, in PMOS area, the injection ion of the third ion implanting be boron from
Son, in NMOS area, the injection ion of the third ion implanting is phosphonium ion.Wherein, the third ion implanting can root
According to needing to select vertical ion injection, angle-tilt ion injection or multi-angle ion implanting, in the present invention, using multi-angle from
Son injection.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs later
The step of.
Illustratively, further include the steps that forming source-drain electrode (S/D) and metal gates (MG) after the above step, it can be with
The threshold voltage of formed device is further adjusted by work-function layer during forming metal gates.Wherein, gold is formed
Belong to gate structure method can use after after high k dielectric layer metal gates formation process and also using first high k dielectric layer after
Metal gate process, these process routes are without prejudice to connotation of the invention.
The structure of semiconductor devices provided by the invention is described in 2E with reference to the accompanying drawing.The semiconductor devices packet
Include the buffering diffusion layer 204 in semiconductor substrate 200, fin 202, isolation structure 203 and the fin.Wherein:
In the present invention, the semiconductor substrate 200 can be following at least one of the material being previously mentioned: monocrystalline
Silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) is laminated on insulator, on insulator for silicon, silicon-on-insulator (SOI)
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..In the present invention, the constituent material of semiconductor substrate 200 is selected single
Crystal silicon.
Multiple fins 202 are formed in the semiconductor substrate 200, the fin 202 includes being higher than the isolation junction
The exposed portion of 203 top surface of structure and non-exposed portion lower than 203 top surface of isolation structure.Wherein, the dew of the fin
The width of part is less than the width of the non-exposed portion of the fin out.Buffering diffusion layer is formed in the fin 202, it is described
The Doped ions buffered in diffusion layer 204 include carbon ion and Nitrogen ion, germanium ion and Nitrogen ion, carbon ion and germanium ion, carbon
Ion or germanium ion are formed in the bottom of 202 exposed portion of fin and on the side wall of bottom, to be formed with inhibiting
After source electrode and drain electrode in semiconductor substrate Doped ions (such as boron ion or phosphonium ion) horizontal proliferation, to reduce short channel
Effect.
For the isolation structure 203 in the gap between the fin, the isolation structure 203 can select any tool
There are insulating materials of buffer action, such as silica, silicon oxynitride (SiON) etc., in the present invention, the isolation structure 203
Material is silica.
The production method of the semiconductor devices provided according to the present invention executes the first ion implanting by the side wall to fin
The side wall for the fin that etching removal part is exposed afterwards to reduce its width, then to the fin of exposing execute second from
Son injection improves semiconductor to overcome short-channel effect, Exchange Settlement is avoided to reveal to form buffering diffusion layer in the fin
The performance and yield of device.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of production method of semiconductor devices, which comprises the following steps:
Semiconductor substrate is provided, forms multiple fins on the semiconductor substrate；
Isolation structure is formed in gap between the fin, the top surface of the isolation structure is lower than the top surface of the fin,
To expose a part of the fin；
First ion implanting is executed to the side wall of the fin of exposing；
The side wall for the fin that etching removal part is exposed, to reduce the width of the exposed portion of the fin；
Second ion implanting is executed to the fin of exposing, to form buffering diffusion layer in the fin.
2. the method according to claim 1, wherein the step of forming multiple fins on the semiconductor substrate
Include:
The hard mask layer with fin pattern is formed on the semiconductor substrate；
The part semiconductor substrate is removed by mask etch of the hard mask layer, to form multiple fins.
3. the method according to claim 1, wherein forming the isolation junction in gap between the fin
The step of structure includes:
Depositing isolation material layer, with the gap being filled up completely between the fin；
It is etched back to the spacer material layer, to form isolation structure.
4. according to the method described in claim 2, it is characterized in that, further including that removal is described hard after executing the second ion implanting
The step of mask layer and execution third ion implanting are with adjusting threshold voltage.
5. the method according to claim 1, wherein the ion of first ion implanting injection includes carbon ion
With boron ion or carbon ion and phosphonium ion.
6. the method according to claim 1, wherein the implant angle of first ion implanting be 0 °~5 °,
The energy of ion implanting is 5keV~20keV, and the dosage of ion implanting is 5E12atom/cm2~5E13atom/cm2。
7. the method according to claim 1, wherein the ion of second ion implanting injection includes carbon ion
With Nitrogen ion, germanium ion and Nitrogen ion, carbon ion and germanium ion, carbon ion or germanium ion.
8. the method according to claim 1, wherein the implant angle of second ion implanting be 10 °~
20 °, the energy of ion implanting is 5keV~20keV, and the dosage of ion implanting is 5E13atom/cm2~5E14atom/cm2。
9. the method according to claim 1, wherein the buffering diffusion layer is formed in the fin exposed portion
Bottom and close to bottom side wall on.
10. the method according to claim 1, wherein etching what removal part was exposed using wet-etching technology
The side wall of the fin.
11. a kind of semiconductor devices characterized by comprising
Semiconductor substrate is formed with multiple fins in the semiconductor substrate；
Isolation structure is formed in gap between the fin, the top surface of the isolation structure is lower than the top surface of the fin,
To expose a part of the fin；
The width of the fin exposed portion is less than the width of non-exposed portion；
Buffering diffusion layer is formed in the fin.
12. semiconductor devices according to claim 11, which is characterized in that it is described buffering diffusion layer Doped ions include
Carbon ion and Nitrogen ion, germanium ion and Nitrogen ion, carbon ion and germanium ion, carbon ion or germanium ion.
13. semiconductor devices according to claim 11, which is characterized in that the buffering diffusion layer is formed in the fin
On the side wall of the bottom of exposed portion and close bottom.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710995782.0A CN109698198A (en) | 2017-10-23 | 2017-10-23 | A kind of semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710995782.0A CN109698198A (en) | 2017-10-23 | 2017-10-23 | A kind of semiconductor devices and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109698198A true CN109698198A (en) | 2019-04-30 |
Family
ID=66226044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710995782.0A Pending CN109698198A (en) | 2017-10-23 | 2017-10-23 | A kind of semiconductor devices and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109698198A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571418A (en) * | 2021-05-31 | 2021-10-29 | 上海华力集成电路制造有限公司 | Super well forming method of FinFET |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101103443A (en) * | 2004-12-17 | 2008-01-09 | 应用材料有限公司 | Method of ion implantation to reduce transient enhanced diffusion |
| US20080102570A1 (en) * | 2006-11-01 | 2008-05-01 | Micron Technology, Inc. | Fin field emission transistor apparatus and processes |
| US20100327363A1 (en) * | 2008-05-22 | 2010-12-30 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
| CN104576385A (en) * | 2013-10-14 | 2015-04-29 | 中国科学院微电子研究所 | FinFET structure and manufacturing method thereof |
| CN104900498A (en) * | 2014-03-07 | 2015-09-09 | 格罗方德半导体公司 | Methods to improve FinFet semiconductor device behavior using co-implantation under the channel region |
| US20170194325A1 (en) * | 2015-06-30 | 2017-07-06 | International Business Machines Corporation | FINFET with U-Shaped Channel |
-
2017
- 2017-10-23 CN CN201710995782.0A patent/CN109698198A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101103443A (en) * | 2004-12-17 | 2008-01-09 | 应用材料有限公司 | Method of ion implantation to reduce transient enhanced diffusion |
| US20080102570A1 (en) * | 2006-11-01 | 2008-05-01 | Micron Technology, Inc. | Fin field emission transistor apparatus and processes |
| US20100327363A1 (en) * | 2008-05-22 | 2010-12-30 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
| CN104576385A (en) * | 2013-10-14 | 2015-04-29 | 中国科学院微电子研究所 | FinFET structure and manufacturing method thereof |
| CN104900498A (en) * | 2014-03-07 | 2015-09-09 | 格罗方德半导体公司 | Methods to improve FinFet semiconductor device behavior using co-implantation under the channel region |
| US20170194325A1 (en) * | 2015-06-30 | 2017-07-06 | International Business Machines Corporation | FINFET with U-Shaped Channel |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571418A (en) * | 2021-05-31 | 2021-10-29 | 上海华力集成电路制造有限公司 | Super well forming method of FinFET |
| CN113571418B (en) * | 2021-05-31 | 2024-03-08 | 上海华力集成电路制造有限公司 | Super well forming method of FinFET |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11721762B2 (en) | Fin field effect transistor (FinFET) device and method for forming the same | |
| US20220352374A1 (en) | P-Type Strained Channel in a Fin Field Effect Transistor (FinFET) Device | |
| CN103762236B (en) | Integrated circuit package and its manufacture method | |
| US10037924B2 (en) | Fin-FET device and fabrication method thereof | |
| CN106158753B (en) | The structures and methods of semiconductor devices | |
| US8614132B2 (en) | Integrated circuit device with well controlled surface proximity and method of manufacturing same | |
| US9837415B2 (en) | FinFET structures having silicon germanium and silicon fins with suppressed dopant diffusion | |
| US8569139B2 (en) | Method of manufacturing strained source/drain structures | |
| CN102931222B (en) | Semiconductor device and method for manufacturing the same | |
| US11205597B2 (en) | Semiconductor device and method | |
| TWI729539B (en) | Semiconductor device and the methods for forming the same | |
| KR20130061616A (en) | High gate density devices and methods | |
| CN105470133B (en) | Semiconductor device manufacturing method | |
| TWI681444B (en) | Method of manufacturing semiconductor devices and a semiconductor device | |
| TWI725557B (en) | Method for forming semiconductor device | |
| CN104752202B (en) | Method for manufacturing semiconductor device | |
| US9425311B2 (en) | MOS transistors and fabrication methods thereof | |
| CN109698198A (en) | A kind of semiconductor devices and preparation method thereof | |
| CN106328534B (en) | MOS transistor and forming method thereof | |
| US11217483B2 (en) | Semiconductor structure and fabrication method thereof | |
| CN105304491A (en) | Method for forming embedded silicon germanium | |
| CN108493240A (en) | Z-type hetero-junctions tunneling field-effect transistor with lightly doped drain structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190430 |
|
| RJ01 | Rejection of invention patent application after publication |