CN109697173B - Information security-oriented embedded computer SiP module design method and circuit - Google Patents
Information security-oriented embedded computer SiP module design method and circuit Download PDFInfo
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- CN109697173B CN109697173B CN201811511383.3A CN201811511383A CN109697173B CN 109697173 B CN109697173 B CN 109697173B CN 201811511383 A CN201811511383 A CN 201811511383A CN 109697173 B CN109697173 B CN 109697173B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention provides an information security-oriented embedded computer SiP module design method and a circuit, wherein the method comprises the following steps: executing a bootstrap program after the processor is powered on and started, and receiving an external command through an external bus interface; when an application program encryption instruction is received, receiving original data of an application program from an external bus interface, wherein the original data is not encrypted; the processor sends the original data to an algorithm security chip through an SPI bus; the algorithm security chip encrypts the original data through an SM4 algorithm coprocessor to form encrypted data of an application program, and solidifies an encryption key into a FLASH memory in the algorithm security chip; the processor receives the encrypted data through an SPI bus; the processor solidifies the encrypted data into the application program storage area in the connected FLASH.
Description
Technical Field
The invention belongs to the technical field of information security of embedded computers, and particularly relates to an information security-oriented embedded computer SiP module design method and circuit.
Background
In the field of embedded computers, siP (System in Package system in package) technology is a core technology for achieving miniaturization of embedded computers. The SiP technology can reduce the volume and weight of avionic equipment by tens of times, improve the reliability by tens of times, greatly shorten the manufacturing period and remarkably reduce the manufacturing cost, and is an important technical means for integrating and miniaturizing avionic products.
Confidentiality of information security may prevent an adversary from decrypting confidential information in the system. Encryption technology is a key technology for guaranteeing information security, and common encryption technologies include: symmetric key encryption, public key encryption, hash function encryption, and the like. The published cryptographic algorithms include: SM1 symmetric algorithm, SM2 asymmetric algorithm, SM3 Hash (Hash) algorithm, SM4 block encryption algorithm.
The algorithm security chip is a special chip for providing security functions such as security configuration, data encryption, security storage, key management, digital signature and the like for the system. The internal integration of the chip has the technical advantages that the encryption and decryption speed is high, secret data is solidified in the chip, data operation is completed in the chip, the external world cannot perceive and acquire the secret data, and a defense mechanism is used for preventing the secret data from leakage.
Disclosure of Invention
The invention provides an information security-oriented embedded computer SiP module design method and a circuit, which aim to solve the problem that an embedded computer SiP module lacks security measures of information security and core data and key application codes are easy to steal.
The invention provides an information security-oriented embedded computer SiP module design method, which comprises the following steps:
executing a bootstrap program after the processor is powered on and started, and receiving an external command through an external bus interface;
when an application program encryption instruction is received, receiving original data of an application program from an external bus interface, wherein the original data is not encrypted;
the processor sends the original data to an algorithm security chip through an SPI bus;
the algorithm security chip encrypts the original data through an SM4 algorithm coprocessor to form encrypted data of an application program, and solidifies an encryption key into a FLASH memory in the algorithm security chip;
the processor receives the encrypted data through an SPI bus;
the processor solidifies the encrypted data into the application program storage area in the connected FLASH.
Optionally, the application program includes application program 1 and application program 2, and after the processor solidifies the encrypted data into the application program storage area in the connected FLASH, the method further includes:
the processor reads the encrypted data a of the application program 1 from the storage area of the application program 1 of the connected FLASH memory through an SPI interface or a local bus interface;
the processor sends the encrypted data a to a secure encryption chip through an SPI interface, generates a decryption key [ A2] and an encryption key B2 according to an SM2 algorithm, and sends the encryption key B2 to the secure encryption chip through the SPI interface;
the security chip reads the decryption key [ A ] from the FLASH chip of the security chip, decrypts the encrypted data a, encrypts the decrypted data a through the encryption key B2 to form an encrypted ciphertext [ a ], and sends the encrypted ciphertext [ a ] to the processor through the SPI interface;
the processor adopts a decryption key [ A2] to decrypt the encrypted ciphertext [ a ], generates decryption data A, and stores the decryption data A into the SRAM of the processor.
Optionally, after storing the decrypted data a in an SRAM of the own processor, the method further comprises:
the processor reads the encrypted data b of the application program 2 from the application program 2 storage area of the FLASH memory of the processor through an SPI interface or a local bus interface;
the processor sends the encrypted data b to the security encryption chip through an SPI interface;
the security chip reads a decryption key [ B ] from the FLASH chip of the security chip, decrypts the encrypted data B, generates decryption data B, and stores the decryption data B in an SRAM in the security chip.
Optionally, after storing the decrypted data B in an SRAM inside the secure chip, the method further includes:
the processor jumps to an application program 1 in the SRAM of the processor to execute, and sends an execution command of an application program 2 to the algorithm security chip;
when the algorithm security chip receives the execution command of the application program 2, the algorithm security chip jumps to the application program 2 in the SRAM of the algorithm security chip to execute and generates the running result of the application program 2;
and the running result of the application program 2 is obtained through a function interface of the application program 1 in the processor.
Optionally, the code segment of the bootstrap program, the code segment of the application program 1 and the code segment of the application program 2 are stored in segments in a FLASH connected to the processor.
Optionally, the algorithm security chip is used for storing the decryption key [ a ] and the decryption key [ B ], and the algorithm security chip is internally integrated with SM2 and SM4 algorithm coprocessors.
Optionally, the processor and the algorithm security chip are interconnected by adopting an SPI bus or an internal bus, and data on the SPI bus is encrypted and protected by adopting a public key cryptographic algorithm.
The invention provides an information security-oriented embedded computer SiP circuit, which comprises a processor (1), a FLASH memory (2) and a security chip (3), wherein the processor (1) is connected with the FLASH memory (2), and the processor (1) is connected with the security chip (3).
Optionally, the processor (1), the FLASH memory (2) and the security chip (3) are packaged in a cavity and interconnected through bonding wires, a ceramic substrate or a plastic substrate.
In summary, in the method, the secret key of the security data is stored in the algorithm security chip, and the decrypted partial data is also stored in the algorithm security chip, so that the purpose that the outside cannot detect the decryption is achieved; all bare chips are integrated in one package body and interconnected through bonding wires, ceramic substrates or plastic substrates, so that the difficulty of physical detection is increased, and the internal bus communication is an encryption channel, so that the aim of difficult cracking of bus data can be achieved.
Drawings
FIG. 1 is a schematic diagram of a system structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of program partition in a FLASH memory according to an embodiment of the present invention.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The invention discloses an information security-oriented embedded computer SiP module design method and a circuit. The SiP module comprises a packaging body, a processor bare chip, a FLASH memory bare chip and an algorithm security chip bare chip, wherein the bare chip is packaged in one packaging body; the FLASH memory realizes long-term storage of the safety data, the algorithm safety chip realizes encryption and decryption of the safety data and key storage, and the processor reads the encrypted data from the FLASH memory and sends the encrypted data to the algorithm safety chip; after the algorithm security chip decrypts the encrypted data, a part of data is stored in the SRAM in the algorithm security chip, and the other part of data is sent to the processor through a software encryption channel with the processor, and after the processor decrypts, the data is placed in the SRAM in the processor. The decrypted codes are operated in a distributed mode, main codes are operated in an SRAM of the processor, partial codes with low calculation performance requirements are operated on the security chip, and the main processor and the security chip communicate information through an internal bus of the SiP module.
In the method, the secret key of the safety data is stored in the algorithm safety chip, and the decrypted partial data is also stored in the algorithm safety chip, so that the aim that the outside cannot detect and decrypt is fulfilled; all bare chips are integrated in one package body and interconnected through bonding wires, ceramic substrates or plastic substrates, so that the difficulty of physical detection is increased, and the internal bus communication is an encryption channel, so that the aim of difficult cracking of bus data can be achieved.
The scheme can solve the information security of key data and program codes of the embedded computer SiP module, and achieves the purposes of protecting intellectual property rights and preventing data from being stolen.
An information security oriented embedded computer SiP module working schematic diagram is shown in figure 1. Embodiments of the present invention include the following:
(1) The hardware composition of the SiP module comprises: 1 processor (SoPC), 1 DDR3 memory, 1 SPI interface FLASH memory and 1 algorithm security chip. The SiP module package adopts a plastic package BGA480, and the system composition is shown in the figure. Performance index:
1. a processor: main frequency 600MHz, internal integrated floating point processor, on-chip SRAM capacity 256KB,1 way SPI interface.
2. DDR3: storage capacity 1Gb,16-bit bus width, data rate 1333Mb/s.
3. FLASH: 128Mbit is stored, four-port SPI is supported, and the maximum four-data-bit reading speed is achieved: 50MHz.
4. Algorithm security chip: the main frequency is 100MHz, the capacity of an on-chip SRAM is 256KB, the capacity of an on-chip ROM is 64KB, the capacity of an on-chip FLASH is 1MB, and a 1-path SPI interface is integrated into the system, and a public key algorithm engine, an SM2 asymmetric algorithm coprocessor, an SM3 Hash (Hash) algorithm coprocessor and an SM4 packet encryption algorithm coprocessor are integrated into the system.
(2) The encryption implementation steps are as follows:
step 101: the processor executes the boot program after power-on and receives external commands through an external bus interface (RS 232 or other serial bus interface).
Step 102: when receiving the encryption instruction of the application 1, the original data a (not encrypted) of the application 1 is received from the external bus interface.
Step 103: the processor sends the received original data A (not encrypted) of the application program 1 to the algorithm security chip through the SPI bus.
Step 104: the algorithm security chip encrypts the original data A of the application program 1 through an internal integrated SM4 algorithm coprocessor to form encrypted data a of the application program 1, and the decryption key [ A ] is solidified into a FLASH memory in the algorithm security chip.
Step 105: the processor receives the encrypted data a of the application program 1 encrypted by the algorithm security chip through the SPI bus.
Step 106: the processor solidifies the encrypted data a of the application 1 into the application 1 storage area (data encrypted) in the FLASH.
Step 107: and repeating the steps 102-106, receiving the data of the application program 2, encrypting and solidifying the data into a storage area (the data is encrypted) of the application program 2 in the FLASH, and solidifying the decryption key [ B ] into a FLASH memory in the algorithm security chip.
(3) Application 1 encrypted data decryption process:
step 201: the processor reads the encrypted data a of the application 1 from the application 1 storage area (encrypted) of the FLASH memory via the SPI interface or the local bus interface.
Step 202: the processor sends the encrypted data a to the secure encryption chip through the SPI interface, generates a decryption key [ A2] and an encryption key B2 according to an SM2 algorithm, and sends the encryption key B2 to the secure encryption chip through the SPI interface.
Step 203: the security chip reads the decryption key [ A ] from the internal FLASH chip, decrypts the encrypted data a, encrypts the decrypted data a through the encryption key B2 to form an encrypted ciphertext [ a ], and sends the encrypted ciphertext [ a ] to the processor through the SPI interface.
Step 204: the processor adopts the decryption key [ A2] to decrypt the encrypted ciphertext [ a ], and decrypted data A of the decrypted decryption application program 1 is put into the SRAM of the processor.
(4) Application 2 encrypted data decryption process:
step 301: the processor reads the encrypted data b of the application 2 from the application 2 storage area (encrypted) of the FLASH memory via the SPI interface or the local bus interface.
Step 302: the processor sends the encrypted data b to the secure encryption chip through the SPI interface.
Step 303: the security chip reads the decryption key [ B ] from the internal FLASH chip, decrypts the encrypted data B and stores the encrypted data B in the SRAM in the security chip.
(5) Application distributed execution process:
step 401: the processor jumps to the application 1 in the SRAM for execution and notifies the security chip to execute the application 2.
Step 402: the security chip receives the execution command of the processor application program 2 and jumps to the application program 2 in the SRAM inside the security chip for execution.
Step 403: the result of the running of the application 2 in the security chip is obtained by means of a function call by executing the application 1 in the processor.
The invention aims to solve the problems that the functional circuits integrated inside the miniature embedded computer SiP module are more and more, but in actual use, partial functional circuits are in conditional operation or non-operation, and the long-time power-up operation of the partial circuits can cause the SiP module to consume energy and increase heat.
Claims (4)
1. An information security-oriented embedded computer SiP module design method is characterized by comprising the following steps:
executing a bootstrap program after the processor is powered on and started, and receiving an external command through an external bus interface;
when an application program encryption instruction is received, receiving original data of an application program from an external bus interface, wherein the original data is not encrypted;
the processor sends the original data to an algorithm security chip through an SPI bus;
the algorithm security chip encrypts the original data through an SM4 algorithm coprocessor to form encrypted data of an application program, and solidifies a decryption key into a FLASH memory in the algorithm security chip; the algorithm security chip is used for storing a decryption key [ A ] and a decryption key [ B ], and SM2 and SM4 algorithm coprocessors are integrated inside the algorithm security chip;
the processor receives the encrypted data through an SPI bus;
the processor solidifies the encrypted data into an application program storage area in the connected FLASH;
the application program comprises an application program 1 and an application program 2, and after the processor solidifies the encrypted data into an application program storage area in the connected FLASH, the method further comprises:
the processor reads the encrypted data a of the application program 1 from the storage area of the application program 1 of the connected FLASH memory through an SPI interface or a local bus interface;
the processor sends the encrypted data a to an algorithm security chip through an SPI interface, generates a decryption key [ A2] and an encryption key B2 according to an SM2 algorithm, and sends the encryption key B2 to the algorithm security chip through the SPI interface;
the algorithm security chip reads a decryption key [ A ] from a FLASH chip of the algorithm security chip, decrypts the encrypted data a, encrypts the decrypted data a through an encryption key B2 to form an encrypted ciphertext [ a ], and sends the encrypted ciphertext [ a ] to the processor through an SPI interface;
the processor adopts a decryption key [ A2] to decrypt the encrypted ciphertext [ a ], generates decryption data A, and stores the decryption data A into an SRAM of the processor;
after storing the decrypted data a in the SRAM of the own processor, the method further comprises:
the processor reads the encrypted data b of the application program 2 from the application program 2 storage area of the FLASH memory of the processor through an SPI interface or a local bus interface;
the processor sends the encrypted data b to the algorithm security chip through an SPI interface;
the algorithm security chip reads a decryption key [ B ] from a FLASH chip of the algorithm security chip, decrypts the encrypted data B, generates decryption data B, and stores the decryption data B in an SRAM (static random access memory) in the algorithm security chip;
after storing the decrypted data B in the SRAM inside the secure chip, the method further comprises:
the processor jumps to an application program 1 in the SRAM of the processor to execute, and sends an execution command of an application program 2 to the algorithm security chip;
when the algorithm security chip receives the execution command of the application program 2, the algorithm security chip jumps to the application program 2 in the SRAM of the algorithm security chip to execute and generates the running result of the application program 2;
and the running result of the application program 2 is obtained through a function interface of the application program 1 in the processor.
2. The method of claim 1, wherein the code segments of the boot program, the code segments of the application program 1, and the code segments of the application program 2 are stored in segments in a FLASH connected to the processor.
3. The method of claim 1, wherein the processor and the algorithmic security chip are interconnected using an SPI bus or an internal bus, and data on the SPI bus is cryptographically protected using a public key cryptographic algorithm.
4. An information security-oriented embedded computer SiP module design circuit is characterized in that the information security-oriented embedded computer SiP module design circuit is applied to the information security-oriented embedded computer SiP module design method according to claim 1, and comprises a processor (1), a FLASH memory (2) and an algorithm security chip (3), wherein the processor (1) is connected with the FLASH memory (2), and the processor (1) is connected with the algorithm security chip (3); the processor (1), the FLASH memory (2) and the algorithm security chip (3) are packaged in a cavity and interconnected through bonding wires, a ceramic substrate or a plastic substrate.
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| CN110909391A (en) * | 2019-12-04 | 2020-03-24 | 四川虹微技术有限公司 | RISC-V based safe storage method |
| CN113206775B (en) * | 2021-04-16 | 2023-04-07 | 中科开创（广州）智能科技发展有限公司 | Terminal access equipment with CAN bus function, application method and device |
| CN113746642B (en) * | 2021-11-08 | 2022-02-11 | 西安热工研究院有限公司 | Method and system for communication between computers |
| CN114996725B (en) * | 2022-05-06 | 2023-07-28 | 北京中科昊芯科技有限公司 | Method for protecting development program and processor |
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