CN109697146A - Processor verifies activation sequence generation method, device, equipment and storage medium - Google Patents
Processor verifies activation sequence generation method, device, equipment and storage medium Download PDFInfo
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- CN109697146A CN109697146A CN201811574035.0A CN201811574035A CN109697146A CN 109697146 A CN109697146 A CN 109697146A CN 201811574035 A CN201811574035 A CN 201811574035A CN 109697146 A CN109697146 A CN 109697146A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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Abstract
The invention discloses a kind of processor verifying activation sequence generation method, device, equipment and storage mediums, a kind of activation sequence generation method includes: the parameter of basis default base class and base class, generate the class for describing data packet, default base class is used for describe the class of different data packet and providing spread foundation, and the parameter of base class includes describing the relevant information of the class of different data packet；Instantiate the class for describing data packet, the class instantiated；The class of instantiation, by the data packet received according to the configuration of the class of instantiation, be stored in buffer queue with postponing；It calls data to generate activation sequence from buffer queue and is sent to processor to be verified.Processor verifying activation sequence generation method, device, equipment and storage medium disclosed by the invention, for reducing the workload for generating activation sequence.
Description
Technical field
The present embodiments relate to computer technology more particularly to a kind of processor verifying activation sequence generation methods, dress
It sets, equipment and storage medium.
Background technique
Network processing unit is a kind of programming device, it applies specifically to the various tasks of the communications field, such as at packet
Reason, protocal analysis, route querying, the convergence of sound/data, firewall, QoS etc..For network processing unit, designing and producing
During need repeatedly to verify it, each channel (object for being sent to network processing unit by generating multiple activation sequences
Manage port), so that whether the response for verifying network processing unit meets design objective.
But different scenes is divided into for the verifying of network processing unit, required activation sequence and excitation under different scenes
The transmission form of sequence is different, this results in needing to separately design corresponding activation sequence for unused verifying scene, with
And corresponding sending method, design efforts would is big, and it is not convenient for safeguarding, and time-consuming for debugging.
Summary of the invention
The present invention provides a kind of processor verifying activation sequence generation method, device, equipment and storage medium, is swashed with reducing
Encourage the generation workload of sequence.
In a first aspect, the embodiment of the present invention provides a kind of processor verifying activation sequence generation method, comprising:
According to the parameter of default base class and base class, the class for describing data packet is generated, base class is preset and is used for as description not
Class with data packet provides spread foundation, and the parameter of base class includes describing the relevant information of the class of different data packet；
Instantiate the class for describing data packet, the class instantiated；
The class of instantiation, by the data packet received according to the configuration of the class of instantiation, be stored in slow with postponing
It deposits in queue；
It calls data to generate activation sequence from buffer queue and is sent to processor to be verified.
In a kind of possible implementation of first aspect, according to the parameter of default base class and base class, generate for describing
Before the class of data packet, method further include:
The parameter of a default base class and base class is defined, the parameter of base class includes the handle of base class and the letter of data cell
Breath；
Define the class for describing data packet, the class for describing data packet include buffer queue, configuration interface, storage connect
Mouth and dispatch interface.
In a kind of possible implementation of first aspect, the class of instantiation is carried out with postponing, the data that will be received
Packet is stored in buffer queue according to the configuration of the class of instantiation, comprising:
By the configuration for configuring the class of interface adjustment instantiation；
According to the configuration of the class of instantiation, the data packet received by memory interface is stored in buffer queue；
It calls data to generate activation sequence from buffer queue and is sent to processor to be verified, comprising:
It calls data to generate activation sequence from buffer queue by dispatch interface and is sent to processor to be verified.
In a kind of possible implementation of first aspect, according to the configuration of the class of instantiation, it will be connect by memory interface
The data packet received is stored in buffer queue, comprising:
According to the configuration of the class of instantiation, the data packet received by memory interface is directly stored in buffer queue
In, or by the data packet cutting received by memory interface be data cell after be stored in buffer queue.
In a kind of possible implementation of first aspect, the configuration of the class of instantiation, comprising: form, the data of excitation
At least one of the size of unit, excitation scheduling parameter.
In a kind of possible implementation of first aspect, calls data to generate activation sequence from buffer queue and send
To processor to be verified, comprising:
Data are called to generate activation sequence from buffer queue, and to be verified by being sent in activation sequence driving to bus
Processor.
Second aspect, the embodiment of the invention also provides a kind of processors to verify activation sequence generating means, comprising:
Class generation module presets base for generating the class for describing data packet according to the parameter for presetting base class and base class
Class is used for describe the class of different data packet and providing spread foundation, and the parameter of base class includes describing the correlation of the class of different data packet
Information；
Class instantiates module, for instantiating the class for describing data packet, the class instantiated；
Data processing module, for carrying out the class of instantiation with postponing, by the data packet received according to instantiation
The configuration of class, is stored in buffer queue；
Activation sequence scheduler module, for from buffer queue call data generate activation sequence and be sent to it is to be verified from
Manage device.
In a kind of possible implementation of second aspect, class definition module, for defining the ginseng of default base class and base class
Number, the parameter of base class includes the handle of base class and the information of data cell；The class for describing data packet is defined, for describing number
Class according to packet includes buffer queue, configuration interface, memory interface and dispatch interface.
The third aspect, the embodiment of the invention also provides a kind of processors to verify activation sequence generating device, comprising:
One or more processors；
Storage device, for storing one or more programs,
When one or more programs are executed by one or more processors, so that one or more processors realize such as first
The processor of any implementation of aspect verifies activation sequence generation method.
Fourth aspect, the embodiment of the invention also provides a kind of computer readable storage mediums, are stored thereon with computer
Program, which is characterized in that realize that the processor such as any implementation of first aspect is verified when the program is executed by processor
Activation sequence generation method
Processor verifying activation sequence generation method, device, equipment and storage medium provided in an embodiment of the present invention, first
According to the parameter of default base class and base class, the class for describing data packet is generated, it is right after instantiating the class for describing data packet
The class of instantiation, by the data packet received according to the configuration of the class of instantiation, be stored in buffer queue with postponing, from
And data can be called to generate activation sequence from buffer queue and be sent to be verified by the dispatch interface of the class of instantiation
Processor reduces the workload for generating activation sequence, and convenient for safeguarding.
Detailed description of the invention
Fig. 1 is the flow chart of activation sequence generation method embodiment one provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of activation sequence generating means embodiment one provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of activation sequence generating device provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
In the verifying of network processing unit, there are the following two kinds scenes:
The first be verifying network processing unit inner buffer structure, service quality (Quality of Service,
When QoS), need to control the excitation in the multiple channels (physical port) for being sent to network processing unit, such as randomly send out to each channel
Excitation is sent, is sent and is motivated to some channel with certain rate, with poll/Weight Queue (Round-Robin/Weighted Fair
Queuing, RR/WFQ) mode to each channel send excitation etc..It is for second that network processing unit can handle data packet and more
Small data cell (cell), each channel reception of network processing unit to data be that data packet, processor enter mouth mold one by one
Data packet can be cut into data cell one by one by block.Therefore in system and verifying (send and motivate to the physical port of processor)
When with certain module level verification (sending and motivate to module interface), it is different for sending the form of excitation.
For the first scene, the scheduling of activation sequence can be in respective verification environment (such as signal generator
(generator), signal driver (dirver)) in realize, can also be realized in use-case, will lead in this way needs each
In the verification environment of module, system verification environment, it will realize this dispatching method in all related examples, heavy workload,
It is unfavorable for safeguarding.For second of scene, data packet can be cut into number in signal generator, signal driver, use-case
According to unit, stored according to each port is corresponding, different authentication module testers has different activation sequence scheduling modes.
Therefore, at present in the verification process to network processing unit, the generation of activation sequence and scheduling mode needs are directed to
Different scenes are respectively set, and need to be repeatedly performed many identical work, and be easy error, and maintenance workload is larger, adjusts
Examination takes a long time.Therefore the embodiment of the present invention provides a kind of generation method of activation sequence, to solve the above problems.
Fig. 1 is the flow chart of activation sequence generation method embodiment one provided in an embodiment of the present invention, as shown in Figure 1, this
Embodiment provide method include:
Step S101 generates the class for describing data packet according to the parameter of default base class and base class, and default base class is used for
Spread foundation is provided to describe the class of different data packet, the parameter of base class includes describing the relevant information of the class of different data packet.
In order to solve in the prior art in the verification process of network processing unit, need for different scenes using different
Mode generates the problem of activation sequence, and activation sequence generation method provided in this embodiment is that the generation of activation sequence and scheduling are built
Class has been found, and has established required class according to demand in specific scheduling process, and the class of foundation is instantiated, to realize excitation sequence
The generation and scheduling of column.In a class realize activation sequence generation and scheduling, greatly reduce each module, system building,
The related work that debugging verification environment is related to, saves debug time, is also convenient for safeguarding.
Firstly, being needed according to the parameter for presetting base class and base class, generation is used for during carrying out activation sequence generation
The class of data packet is described.The class for describing data packet generated is the data packet or data of the activation sequence generated needed for meeting
The set of unit.Preset base class is the basis of the class of the data packet of required transmission in various verification environments, various verification environments
In the class of the data packet to be sent expanded from base class.In object-oriented programming, the essence of class is a kind of
Data type, different classes is for indicating different data types.Due to no matter to processor verified used in which kind of
Activation sequence centainly with the feature of a part of general character, therefore the feature extraction of these general character can be come out, and be abstracted
For a class, as base class.Other different features are added to the base class, then available a variety of different classes, correspond to not
Same data type, that is, correspond to the feature of different activation sequences.That is, default base class is to describe different numbers
Spread foundation provided by class according to packet.
And the parameter of base class includes the handle of base class and the information of data cell etc., that is, a variety of different data class
Personalized feature possessed by type is formed different for describing by the way that a variety of different parameters are added in base class
The class of data packet, that is, correspond to different activation sequences.Default base class only one, and the parameter of base class can be more
Kind, the characteristics of according to the activation sequence of required generation, the parameter of base class includes describing the relevant information of the class of different data packet, will
Base class is combined from different base class parameters, so as to obtain the class for describing data packet.
Before generating the class for describing data packet according to the parameter for presetting base class and base class, it is also necessary to define the base class
With the parameter of base class.It specifically includes: defining the parameter of a base class and base class, the parameter of base class includes the handle and data of base class
The information of unit；The class for describing data packet is defined, the class for describing data packet includes buffer queue, configuration information, matches
Set interface, memory interface and dispatch interface.Wherein the parameter of base class is referred to as the skin (wrapper) of base class, base class
Wrapper defines the handle of a base class, can also include some information of data cell, such as whether data cell is first
Data cell, belong to it is no be the last one data cell of data packet, data cell serial number in the packet, have in data cell
How many byte effectively etc. information.Then it also needs to define the class for describing data packet, defines the class packet for describing data packet
It includes and defines a buffer queue, which uses come the class example of the parameter based on channel information storage base class.It further include configuration
Information, (each channel is swashed for form (data packet or data cell), the size of data cell including excitation, excitation scheduling parameter
Encourage transmission sequence, rate etc.).Interface is configured, various configurations can be carried out by the configuration interface, including control whether data
Packet cutting is data cell, the size of data cell, Dispatching Form Headway etc..Memory interface, the interface can be called data packet or
Data cell is stored in buffer queue.Dispatch interface, the example for calling the interface to obtain a class are realized in the interface
Specific scheduling is useless, by scheduling parameter, the example that different dispatching algorithms can be selected to obtain class.
Step S102 instantiates the class for describing data packet, the class instantiated.
It after generating the class for describing data packet, needs to instantiate such, instantiation refers in object-oriented
In programming, with the process of class creation object.After namely generating class according to the parameter of base class and base class, created into specific
Deal with objects.The parameter of base class and base class is the parameter abstracted, because its essence is type, rather than data,
It so being not present in memory, cannot directly be operated, when being only instantiated as object, can just become operate.Instantiation
One object is exactly to be that object opens up memory headroom, then instantiating such just after generating the class for describing data packet
It is to open up a memory headroom for the class for describing data packet of generation, then this can be stored in actual data packet
In memory headroom.Since the class for describing data packet is generated according to the parameter of base class and base class comprising data packet
Certain feature, that is, data packet corresponding to the class that instantiates are the data packets with these features.
Step S103 carries out with postponing the class of instantiation, by the data packet received according to the configuration of the class of instantiation,
It is stored in buffer queue.
It is also only to have centainly due to generated for describing the class of data packet according to the parameter for presetting base class and base class
Feature class, that is, correspond to the data type with certain feature, and the parameter of base class is limited, according to preset
The parameter of base class and base class is generated for describing the class of data packet, it is difficult to be adapted to heterogeneous networks processor in different rings
The generation of verifying activation sequence under border.It therefore, can also be to example after being instantiated to the class for describing data packet
The class of change carries out personalized configuration, adapts to the class of the instantiation by configuration more to particular network processor in specific field
Verifying activation sequence under scape.And these configuration include excitation form (data packet or data cell), the size of data cell,
Motivate scheduling parameter (the excitation transmission sequence in each channel, rate etc.).It further include controlling whether data packet cutting to be data sheet
Member, the size of data cell, Dispatching Form Headway etc..
The class of instantiation should match data type corresponding to the class of the instantiation postponed with postponing and just meet
Verify to network processing unit the various features of required activation sequence, then can be by the data packet received according to example
The configuration of the class of change is stored in buffer queue corresponding to the class of instantiation.Certainly, before storing, need according to example
The configuration of the class of change performs corresponding processing the data packet received, such as controls whether data packet being cut into data sheet
Member, the size of data cell, the Dispatching Form Headway of data etc..
Specifically, by the data packet received according to the configuration of the class of instantiation, being stored in buffer queue includes: that will connect
The data packet received is directly stored in buffer queue according to the configuration of the class of instantiation, or the data packet received is cut
It is stored in buffer queue after being divided into data cell.
Further, for describing the class of data packet, including buffer queue, configuration interface, memory interface and dispatch interface.
It is possible to which the configuration by the class for configuring interface adjustment instantiation will pass through memory interface according to the configuration of the class of instantiation
The data packet received is stored in buffer queue, then calls data to generate excitation sequence from buffer queue by dispatch interface
It arranges and is sent to processor to be verified.
Step S104 calls data to generate activation sequence from buffer queue and is sent to processor to be verified.
After being all stored in all received data packets in buffer queue, data can be called from buffer queue, it is raw
At final activation sequence and it is sent to processor to be verified, to realize the verifying to network processing unit.Due to the present embodiment
The activation sequence generation method of offer is that the parameter of the base class and base class by pre-establishing is generated for describing data packet
Class, and by such instantiate after by configuring, storing accordingly and scheduling process realizes the generation and scheduling of activation sequence, only
It needs a base class that the verifying to the network processing unit of several scenes can be realized, greatly reduces the work for generating activation sequence
Amount, and it is convenient for safeguarding.
Specifically, it is typically all to be sent through the bus due to sending activation sequence to network processing unit, is postponing
Deposit after calling data packet or data cell to generate activation sequence in queue, can will be sent in activation sequence driving to bus to
Verification processing device.
Activation sequence generation method provided in this embodiment, first according to the parameter for presetting base class and base class, generation is used for
The class of data packet is described, after instantiating class for describing data packet, the class of instantiation is carried out with postponing, the number that will be received
According to packet according to the configuration of the class of instantiation, it is stored in buffer queue, so as to pass through the dispatch interface of the class instantiated, from
It calls data to generate activation sequence in buffer queue and is sent to processor to be verified, reduce the work for generating activation sequence
Amount, and it is convenient for safeguarding.
For the two kinds of different scenes verified in the prior art to network processing unit, wherein the first, is verifying net
When the inner buffer structure of network processor, QoS, due to needing to control the excitation in the multiple channels for being sent to network processing unit, then
It can increase in the parameter of base class to the different parameters that are described of excitation sending methods, in this way according to base class and base class
Parameter generates after the various classes for describing data packet, so that it may respectively and corresponding to different excitation sending methods, logical
After configuration interface is crossed to the class progress individual cultivation of instantiation, the activation sequence sent in various ways can be obtained, be not necessarily to
Under various verification environments, to the configuration that the dispatching method of verifying sequence is distinguished, the formation efficiency of activation sequence is improved,
And it is easy to maintain.For second of scene, when carrying out whole-system verification or module level verification to network processing unit, it may be necessary to
Data cell after directly sending datagram to processing or need to send cutting to processor, then can be in the parameter of base class
It is middle to increase the different modes that cutting is carried out to data packet, in this way various for describing number according to the generation of the parameter of base class and base class
After the class of packet, so that it may it is corresponding with required different data packet slit mode respectively, by configuring interface to instantiation
Class carry out individual cultivation after, can be obtained with the corresponding activation sequence of various data packet slit modes, without being tested various
It demonstrate,proves under environment, cutting processing is carried out to data packet respectively in different ways, avoids being write by different verifying personnel
Different verifying sequences used by data packet slit mode it is different and the maintenance to activation sequence and debugging bring are difficult.
Fig. 2 is the structural schematic diagram of activation sequence generating means embodiment one provided in an embodiment of the present invention, such as Fig. 2 institute
Show, activation sequence generating means provided in this embodiment include:
Class generation module 21 is preset for generating the class for describing data packet according to the parameter for presetting base class and base class
Base class is used for describe the class of different data packet and providing spread foundation, and the parameter of base class includes describing the phase of the class of different data packet
Close information；
Class instantiates module 22, for instantiating the class for describing data packet, the class instantiated；
Data processing module 23, for carrying out the class of instantiation with postponing, by the data packet received according to instantiation
Class configuration, be stored in buffer queue；
Activation sequence scheduler module 24, for calling data to generate activation sequence from buffer queue and being sent to be verified
Processor.
Activation sequence generating means provided in this embodiment generate for realizing the activation sequence that embodiment illustrated in fig. 1 provides
Method, it is similar that the realization principle and technical effect are similar, and details are not described herein again.
Further, activation sequence generating means further include class definition module on the basis of embodiment shown in Fig. 2, are used for
The parameter of default base class and base class is defined, the parameter of base class includes the handle of base class and the information of data cell；Definition is for retouching
The class for stating data packet, the class for describing data packet include buffer queue, configuration interface, memory interface and dispatch interface.
Further, on the basis of embodiment shown in Fig. 2, data processing module 23, specifically for by configuring interface
Adjust the configuration of the class of instantiation；According to the configuration of the class of instantiation, the data packet received by memory interface is stored in
In buffer queue.Activation sequence scheduler module 24 is specifically used for that data generation is called to swash from buffer queue by dispatch interface
It encourages sequence and is sent to processor to be verified
Further, on the basis of embodiment shown in Fig. 2, data processing module 23, specifically for passing through memory interface
It by the data packet received according to the configuration of the class of instantiation, is directly stored in buffer queue, or the data that will be received
Packet cutting be data cell after be stored in buffer queue.
Fig. 3 is the structural schematic diagram of activation sequence generating device provided in an embodiment of the present invention, as shown in figure 3, the excitation
Sequence generating device includes processor 31 and memory 32；The quantity of processor 31 can be one in activation sequence generating device
Or it is multiple, in Fig. 3 by taking a processor 31 as an example；Processor 31 and memory 32 in activation sequence generating device can pass through
Bus or other modes connect, in Fig. 3 for being connected by bus.
Memory 32 is used as a kind of computer readable storage medium, can be used for storing software program, journey can be performed in computer
Sequence and module, if the corresponding program instruction/module of activation sequence generation method in the application Fig. 1 embodiment is (for example, excitation
Class generation module 21, class in sequence generator instantiate module 22, data processing module 23, activation sequence scheduler module
24).Software program, instruction and module of the processor 31 by operation storage in memory 32, so that activation sequence generates
The various function application and data processing of equipment realize above-mentioned activation sequence generation method.
Memory 32 can mainly include storing program area and storage data area, wherein storing program area can store operation system
Application program needed for system, at least one function；Storage data area can be stored is created according to using for activation sequence generating device
The data etc. built.In addition, memory 32 may include high-speed random access memory, it can also include nonvolatile memory,
A for example, at least disk memory, flush memory device or other non-volatile solid state memory parts.
The embodiment of the present application also provides a kind of storage medium comprising computer executable instructions, computer executable instructions
When being executed by computer processor for executing a kind of activation sequence generation method, this method comprises:
According to the parameter of default base class and base class, the class for describing data packet is generated, base class is preset and is used for as description not
Class with data packet provides spread foundation, and the parameter of base class includes describing the relevant information of the class of different data packet；
Instantiate the class for describing data packet, the class instantiated；
The class of instantiation, by the data packet received according to the configuration of the class of instantiation, be stored in slow with postponing
It deposits in queue；
It calls data to generate activation sequence from buffer queue and is sent to processor to be verified.
By the description above with respect to embodiment, it is apparent to those skilled in the art that, the present invention
It can be realized by software and required common hardware, naturally it is also possible to which by hardware realization, but in many cases, the former is more
Good embodiment.Based on this understanding, technical solution of the present invention substantially in other words contributes to the prior art
Part can be embodied in the form of software products, which can store in computer readable storage medium
In, floppy disk, read-only memory (Read-Only Memory, ROM), random access memory (Random such as computer
Access Memory, RAM), flash memory (FLASH), hard disk or CD etc., including some instructions are with so that a computer is set
Standby (can be personal computer, server or the network equipment etc.) executes method described in each embodiment of the present invention.
It is worth noting that, included each unit and module are only in the embodiment of above-mentioned activation sequence generating means
It is to be divided according to the functional logic, but be not limited to the above division, as long as corresponding functions can be realized；Separately
Outside, the specific name of each functional unit is also only for convenience of distinguishing each other, the protection scope being not intended to restrict the invention.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of processor verifies activation sequence generation method characterized by comprising
According to the parameter of default base class and base class, the class for describing data packet is generated, the default base class is used for as description not
Class with data packet provides spread foundation, and the parameter of the base class includes describing the relevant information of the class of different data packet；
Instantiation is described for describing the class of data packet, the class instantiated；
The class of the instantiation is carried out with postponing, by the data packet received according to the configuration of the class of the instantiation, storage
In buffer queue；
It calls data to generate activation sequence from the buffer queue and is sent to processor to be verified.
2. generating and using the method according to claim 1, wherein the basis presets the parameter of base class and base class
Before the class of description data packet, the method also includes:
The parameter of the default base class and base class is defined, the parameter of the base class includes the handle of base class and the letter of data cell
Breath；
Definition is described for describing the class of data packet, and the class for describing data packet includes buffer queue, configuration interface, deposits
Store up interface and dispatch interface.
3. according to the method described in claim 2, it is characterized in that, the class to the instantiation will connect with postponing
The data packet received is stored in buffer queue according to the configuration of the class of the instantiation, comprising:
The configuration for adjusting the class of the instantiation by configuring interface；
According to the configuration of the class of the instantiation, the data packet received by memory interface is stored in buffer queue；
It is described that data is called to generate activation sequence and be sent to processor to be verified from the buffer queue, comprising:
It calls data to generate activation sequence from the buffer queue by dispatch interface and is sent to processor to be verified.
4. according to the method described in claim 3, it is characterized in that, the configuration of the class according to the instantiation, will pass through
The data packet that memory interface receives is stored in buffer queue, comprising:
According to the configuration of the class of the instantiation, the data packet received by memory interface is directly stored in buffer queue
In, or by the data packet cutting received by memory interface be data cell after be stored in buffer queue.
5. the method according to claim 3 or 4, which is characterized in that the configuration of the class of the instantiation, comprising: excitation
At least one of form, the size of data cell, excitation scheduling parameter.
6. method according to any one of claims 1 to 4, which is characterized in that described to call number from the buffer queue
According to generation activation sequence and it is sent to processor to be verified, comprising:
Call data to generate activation sequence from the buffer queue, and will activation sequence driving to be sent in bus to
Verification processing device.
7. a kind of processor verifies activation sequence generating means characterized by comprising
Class generation module, for generating the class for describing data packet, the default base according to the parameter for presetting base class and base class
Class is used for describe the class of different data packet and providing spread foundation, and the parameter of the base class includes describing the class of different data packet
Relevant information；
Class instantiates module, described for describing the class of data packet, the class instantiated for instantiating；
Data processing module, for carrying out the class of the instantiation with postponing, by the data packet received according to the example
The configuration of the class of change, is stored in buffer queue；
Activation sequence scheduler module, for from the buffer queue call data generate activation sequence and be sent to it is to be verified from
Manage device.
8. device according to claim 7, which is characterized in that further include:
Class definition module, for defining the parameter of the default base class and base class, the parameter of the base class includes the handle of base class
With the information of data cell；Definition is described for describing the class of data packet, and the class for describing data packet includes caching team
Column, configuration interface, memory interface and dispatch interface.
9. a kind of processor verifies activation sequence generating device characterized by comprising
One or more processors；
Storage device, for storing one or more programs,
When one or more of programs are executed by one or more of processors, so that one or more of processors are real
Now the processor as described in any in claim 1~6 verifies activation sequence generation method.
10. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the program is by processor
Realize that the processor as described in any in claim 1~6 verifies activation sequence generation method when execution.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811574035.0A CN109697146A (en) | 2018-12-21 | 2018-12-21 | Processor verifies activation sequence generation method, device, equipment and storage medium |
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