CN109684657A - A kind of dedicated SoC memory layout method based on Cortex-M3 processor - Google Patents
A kind of dedicated SoC memory layout method based on Cortex-M3 processor Download PDFInfo
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- CN109684657A CN109684657A CN201811314736.0A CN201811314736A CN109684657A CN 109684657 A CN109684657 A CN 109684657A CN 201811314736 A CN201811314736 A CN 201811314736A CN 109684657 A CN109684657 A CN 109684657A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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Abstract
The invention discloses a kind of SoC memory layout methods based on Cortex-M3 processing.Cortex-M3 processor and conventional ARM processor have very big difference, there is ICode, DCode, System three-bus interface.According to its feature, reasonable SoC memory layout is devised.Wherein, the design of SoC memory layout specifically includes that ROM on Code bus on hardware；Flash on Code bus；SRAM on Code bus；SRAM on System bus, scatter-loading file designs when corresponding on software.SRAM on Code bus can make CM3 from SRAM rather than instruction fetch in Flash is therefore based in the case of hongli 0.13um Eflash technique flow that dedicated SoC system can be made to reach maximum performance.
Description
Technical field
The present invention relates to computer system engineering fields, and in particular to a kind of dedicated SoC system storage layout method.
Background technique
With the rapid development of information technology, Internet of Things and intelligent terminal, the development of traditional microprocessor system is
The trend being out of step with the times, therefore SoC is more as a kind of function, performance is strong, and chip low in energy consumption obtains more and more extensive answer
With.At present in the terminal chip field of performance and sensitive power consumption, SoC has occupied leading position.The application of SoC is expanding to more
Wide field, SoC also have more and more applications in unmanned air vehicle technique, automatic Pilot, the industries such as deep learning, with one piece of single
Piece can be achieved with complete electronic system, be the developing direction of IC industry future.
The full name of SoC is System on Chip, is exactly to integrate an entire information processing on one chip as its name suggests
System, referred to as system on chip or system level chip.SoC also represents a kind of technology, be it is a kind of using determine system function as target,
The software-hardware synergism of modules is developed, and finally development is integrated into the technology of chip piece.SoC is feature-rich, thereon
The various modules such as CPU, GPU, RAM, ADC/DAC, high-speed dsp are integrated with, the complete function of entire digital display circuit is had.It
It is a kind of ASIC, including complete control system and has Embedded software.SoC has penetrated into side's aspect of life
Face, people can propose more flexible demands to the SoC of customization.
SoC can be divided into, according to use, two types: be specific integrated circuit to system-level collection one is dedicated SoC chip
At organic growth.Another kind is exactly general SoC chip, by most of common component, such as CPU, SRAM, DMA, I/O
It integrates on one chip.The design of SoC memory layout directly determines the framework and performance of SoC system.
Summary of the invention
The present invention, which is directed to, is using Cortex-M3 processing as the dedicated SoC design of CPU, using 0.13um hongli
The case where Eflash technique, proposes a kind of dedicated SoC memory layout design, this can be designed so that dedicated SoC system reaches
Maximum performance.Specific technical solution is as follows:
A kind of dedicated SoC memory layout method based on Cortex-M3 processor, it is characterised in that: be based on hongli 0.13um
In the case of Eflash technique flow, for the dedicated SoC for using Cortex-M3 processor, according to Cortex-M3 processor
Corresponding scatter-loading file is arranged by designing reasonable memory layout on SoC hardware in bus feature on software,
Dedicated SoC system can be made to reach best performance.
Memory layout method specifically includes that SoC memory layout designs on hardware；Corresponding dispersion load text on software
Part design.Wherein, the design of SoC memory layout specifically includes that ROM on Code bus on hardware；Flash on Code bus；
SRAM on Code bus；SRAM on System bus.
ROM on the Code bus of the SoC system hardware memory layout, the address space of this ROM are
0x1FFF_0000~0x1FFF_3FFF, total 16KB.Its major function is the code update after SoC is powered on, and can be led to after powering on
It crosses and executes in the flash storage that code is transported on Code bus by the program inside ROM by UART port.
Flash on the Code bus of the SoC system hardware memory layout, the address space of flash storage
For 0x0800_0000~0x0803_FFFF, total 256KB.Its major function is started and opens from Flash after SoC is powered on every time
Begin to execute program code (removing non-update code, just start from ROM).
SRAM on the Code bus of the SoC system hardware memory layout, the address space of this SRAM memory
For 0x1000_0000~0x1000_FFFF, total 64KB.Its major function is read-only (RO) number for the program for being used to store execution
According to.
The address of SRAM on the System bus of the SoC system hardware memory layout, this SRAM memory are empty
Between be 0x2000_0000~0x2000_FFFF, total 64KB.Its major function be used to store execution program it is read-write
(RW) data.
The SoC system scatter-loading file design is to be set in software program compiling by scatter-loading file
Meter, the operation area of the instruction of code and read-only data is placed in the SRAM on Code bus；By the read-write number in program
According in the SRAM being transported on System Bus.
The invention has the benefit that first, according to Cortex-M3 processor bus design feature and flow technique, choosing
Suitable SoC memory layout is selected, so that SoC system reaches maximum performance.After second, SoC hardware structure determine, software is compiled
When translating, executable file can be mapped in conjunction with hardware by scatter-loading file by different operation areas.Third, it is soft or hard
Part combines design, can simplify hardware resource, lifting system performance to greatest extent.
Detailed description of the invention
Fig. 1 is dedicated SoC memory layout figure.
Fig. 2 is scatter-loading file design drawing.
Fig. 3 is that dedicated SoC program updates flow diagram.
Fig. 4 is that dedicated SoC powers on rear program execution flow schematic diagram.
Specific embodiment
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawing, so that advantages and features of the invention energy
It is easier to be readily appreciated by one skilled in the art, so as to make a clearer definition of the protection scope of the present invention.
It is as shown in Figure 1 the dedicated SoC memory layout figure based on Cortex-M3 processor, in Cortex-M3 processor
That hangs on Code bus has ROM, Flash and SRAM module；What is hung on System bus is SRAM module.
ROM on the Code bus of the SoC system hardware memory layout, the address space of this ROM are
0x1FFF_0000~0x1FFF_3FFF, total 16KB.Its major function is the code update after SoC is powered on, and can be led to after powering on
It crosses and executes in the flash storage that code is transported on Code bus by the program inside ROM by UART port.
Flash on the Code bus of the SoC system hardware memory layout, the address space of flash storage
For 0x0800_0000~0x0803_FFFF, total 256KB.Its major function is started and opens from Flash after SoC is powered on every time
Begin to execute program code (removing non-update code, just start from ROM).
SRAM on the Code bus of the SoC system hardware memory layout, the address space of this SRAM memory
For 0x1000_0000~0x1000_FFFF, total 64KB.Its major function is read-only (RO) number for the program for being used to store execution
According to.
The address of SRAM on the System bus of the SoC system hardware memory layout, this SRAM memory are empty
Between be 0x2000_0000~0x2000_FFFF, total 64KB.Its major function be used to store execution program it is read-write
(RW) data.
It is illustrated in figure 2 scatter-loading file design drawing, the area CODE mapping address is corresponding since 0x1000_0000
SRAM on exactly Code bus, simple_test are the titles of corresponding test code, and+RO represents simple_test program
Read-only data operation area be Code bus on SRAM.The corresponding address in the area DATA is corresponding since 0x2000_0000
The SRAM exactly on System bus, * (+RW ,+ZI) represents the read-write data of all programs and the variable of no initializtion
Operation area is the SRAM on System bus.
It is illustrated in figure 3 flow chart when dedicated SoC updates operation program every time.The instruction fetch from ROM after SoC is powered on,
Code is that program outside piece is transported in the Flash of internal Code bus by UART port in ROM.Then, SoC is powered on behind
Afterwards, just directly start from Flash, run updated code.
It is illustrated in figure 4 dedicated SoC and powers on rear program execution flow figure.After dedicated SoC electrifying startup, processor can be first
The read-only data for being located at program in Eflash (instruction and character constant) is transported to the SRAM on Code Bus, it will be in program
Read-write data are transported in the SRAM on System Bus.Then Cortex-M3 processor is from SRAM fetching on Code Bus
Order and character constant, evidence of fetching from System Bus, for Flash, SRAM speed is sufficiently fast, and CPU is not needed yet
It is inserted into latent period, greatly enhances the performance of dedicated SoC system.
The present invention provides a kind of SoC memory layout methods based on Cortex-M3 processing, are being based on hongli 0.13um
In the case of Eflash technique flow, for the dedicated SoC for using Cortex-M3 processor, according to Cortex-M3 processor
Bus feature is arranged on software according to hardware structure design and corresponds to by designing reasonable memory layout on SoC hardware
Scatter-loading file dedicated SoC system can be made to reach so that Cortex-M3 processor is instructed from SRAM rather than in Flash
To best performance.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Any modifications, equivalent replacements, and improvements etc. done within mind and principle, should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of dedicated SoC memory layout method based on Cortex-M3 processor, it is characterised in that: be based on hongli
In the case of 0.13um Eflash technique flow, for the dedicated SoC for using Cortex-M3 processor, according to Cortex-
Corresponding dispersion is arranged on software and adds by designing reasonable memory layout on SoC hardware for M3 processor bus feature
Published article part, can make dedicated SoC system reach best performance；The memory layout method specifically includes that SoC on hardware
Memory layout designs, corresponding scatter-loading file design on software；Wherein, the design of SoC memory layout is main on hardware
It include: ROM on Code bus；Flash on Code bus；SRAM on Code bus；SRAM on System bus.
2. a kind of dedicated SoC memory layout method based on Cortex-M3 processor according to claim 1, special
Sign is: the address space of the ROM on the Code bus of SoC system hardware memory layout, this ROM are 0x1FFF_0000
~0x1FFF_3FFF, total 16KB；Its major function is the code update after SoC is powered on, can be by executing in ROM after powering on
Code is transported in the flash storage on Code bus by the program in face by UART port.
3. a kind of dedicated SoC memory layout method based on Cortex-M3 processor according to claim 1, special
Sign is: the Flash on the Code bus of SoC system hardware memory layout, the address space of flash storage are
0x0800_0000~0x0803_FFFF, total 256KB；Its major function be start since Flash after SoC is powered on every time and
Execute program code (removing non-update code, just start from ROM).
4. a kind of dedicated SoC memory layout method based on Cortex-M3 processor according to claim 1, special
Sign is: the SRAM on the Code bus of SoC system hardware memory layout, the address space of this SRAM memory are
0x1000_0000~0x1000_FFFF, total 64KB；Its major function is to be used to store read-only (RO) data of the program of execution.
5. a kind of dedicated SoC memory layout method based on Cortex-M3 processor according to claim 1, special
Sign is: the SRAM on the System bus of SoC system hardware memory layout, the address space of this SRAM memory are
0x2000_0000~0x2000_FFFF, total 64KB；Its major function is read-write (RW) number for the program for being used to store execution
According to.
6. a kind of dedicated SoC memory layout method based on Cortex-M3 processor according to claim 1, special
Sign is: when SoC system software program compiles, being designed by scatter-loading file, by the fortune of the instruction of code and read-only data
Row region is placed in the SRAM on Code bus；Read-write data in program are transported in the SRAM on System Bus.
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| CN105446843A (en) * | 2014-05-30 | 2016-03-30 | 展讯通信（上海）有限公司 | SOC chip function test system and method |
| US20170199672A1 (en) * | 2016-01-07 | 2017-07-13 | Samsung Electronics Co., Ltd. | Data storage device and data processing system including the data storage device |
| US20170235511A1 (en) * | 2016-02-12 | 2017-08-17 | Knuedge Incorporated | Memory-Attached Computing Resource in Network on a Chip Architecture |
| CN206226452U (en) * | 2016-12-01 | 2017-06-06 | 中国船舶重工集团公司第七一六研究所 | A kind of intelligent dual redundant gigabit ethernet card based on Cortex A9 |
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