CN109672890A - Video coding device and encoder - Google Patents
Video coding device and encoder Download PDFInfo
- Publication number
- CN109672890A CN109672890A CN201811197684.3A CN201811197684A CN109672890A CN 109672890 A CN109672890 A CN 109672890A CN 201811197684 A CN201811197684 A CN 201811197684A CN 109672890 A CN109672890 A CN 109672890A
- Authority
- CN
- China
- Prior art keywords
- encoder
- frame
- information
- prediction
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
- H04N19/159—Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/124—Quantisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/154—Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/172—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/189—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding
- H04N19/196—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
- H04N19/197—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters including determination of the initial value of an encoding parameter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
- H04N19/51—Motion estimation or motion compensation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
- H04N19/51—Motion estimation or motion compensation
- H04N19/513—Processing of motion vectors
- H04N19/517—Processing of motion vectors by encoding
- H04N19/52—Processing of motion vectors by encoding by predictive encoding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
- H04N19/51—Motion estimation or motion compensation
- H04N19/567—Motion estimation based on rate distortion criteria
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/593—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
Abstract
The present invention provides a kind of Video coding device.The Video coding device includes: the first encoder, including prediction module, and the prediction module is to multiple first onblock executing intra predictions operation included in first frame and inter prediction operating；And second encoder, second frame different from first frame is encoded, it and does not include prediction module, wherein if to the first onblock executing inter prediction operating, then prediction module transmits the first information operated about moltion estimation to second encoder, and second encoder includes prediction block generation module, the prediction block generation module receives the first information and by generating prediction block to multiple second onblock executing operation of motion compensation included in the second frame based on the first information.A kind of encoder is also provided.
Description
[cross reference of related application]
It is excellent this application claims on October 16th, 2017 South Korea patent application filed an application the 10-2017-0133921st
It first weighs and from all authority that the South Korea patent application derives, the disclosure full text of the South Korea patent application is simultaneously
Enter the application for reference.
Technical field
Exemplary embodiment is related to Video coding device and/or encoder.
Background technique
People are to such as fine definition (high definition, HD) image and ultrahigh resolution (ultra-high
Definition, UHD) high-resolution, the demand of high quality image such as image increasing, and using for handling this height
Resolution ratio, the high performance video compress technique of high quality image.
Recently, such as the moving devices such as mobile phone, smart phone have been used widely, even and if pair with small big
In small and moving device with limited use environment (for example, using battery) also can to high-resolution, high quality image into
The mode of row Efficient Compression is studied.
In addition, carrying out coding in growth to image with high frame rate or frame/(frames per second, FPS) per second
Trend.However, can only currently encode with limited frame rate to image, and single encoder is difficult with high frame speed
Rate encodes image.
By using multiple encoders, can high frame rate image is encoded.However, when using multiple encoders
When, the size of entire code devices increases, and the size for being wherein embedded with the device of code devices also will increase.
Summary of the invention
The exemplary embodiment of the disclosure encodes image using multiple encoders, while will be by the multiple coding
Device occupies space-minimized.
The exemplary embodiment of the disclosure uses full coding device (full encoder) and code segment device (partial
Encoder) image is encoded, while the quality deterioration of image being minimized.
However, the exemplary embodiment of the disclosure is not limited only to exemplary embodiment described herein.By referring to
To some detailed description of illustrative embodiments in exemplary embodiment given below, to one in disclosure fields
As for technical staff, above and other exemplary embodiments of the disclosure will become more apparent from.
According to an exemplary embodiment of the present disclosure, a kind of Video coding device can include: the first encoder, including prediction electricity
Road, the prediction circuit are configured to: to multiple first onblock executing intra predictions operation included in first frame and interframe
One or more of predicted operation, and if the prediction circuit grasps inter-prediction described in first onblock executing
Make, then transmits the first information operated about moltion estimation；And second encoder, including prediction block generation circuit, it is described
Prediction block generation circuit is configured to: receiving the first information from first encoder, and by based on described the
One information generates prediction block, second frame to multiple second onblock executing operation of motion compensation included in the second frame
It is the frame different from the first frame.
According to an exemplary embodiment of the present disclosure, a kind of encoder can be configured to encode first frame without
For executing the prediction circuit of one or more of intra prediction and inter-prediction.The encoder can include: prediction block
Generation circuit is configured to receive the first information and the second information from the first encoder, and generates prediction block, first letter
Breath the second information associated and described with moltion estimation operation is associated with intra prediction operation, and first encoder is different from
The encoder；And post processing circuitry, it is configured to detect quality deterioration based on reconstructed frame and the first frame, institute
Stating reconstructed frame is obtained by carrying out inverse quantization to the data encoded by the encoder.
According to an exemplary embodiment of the present disclosure, a kind of Video coding device can include: the first encoder；Second coding
Device, the second encoder are different from first encoder；And processor, it is configured to: by first frame and the second frame point
It is not assigned to the first encoder and second encoder, the first frame and second frame are included multiple in input picture
Different frame in frame, second frame is the frame after the first frame, and if is compiled from by the second encoder
Quality deterioration is detected in the image of code, then the processor is configured to: completing the first frame in first encoder
Coding after, second frame is re-assigned to first encoder, and third frame is assigned to second coding
Device, the third frame are the frames after second frame.
By reading described further below, schema and claims, other features and exemplary embodiment can be shown and easy
See.
Detailed description of the invention
The exemplary embodiment of the disclosure, the above and other exemplary implementation of the disclosure are elaborated by referring to accompanying drawing
Example and feature will become more apparent from, in the accompanying drawings:
Fig. 1 is the block diagram for showing the video coding system according to some exemplary embodiments of the disclosure.
Fig. 2 is the block diagram for showing the example of the first encoder included in video coding system shown in Fig. 1.
Fig. 3 is the block diagram for showing the example of second encoder included in video coding system shown in Fig. 1.
Fig. 4 is the block diagram for showing another example of second encoder included in video coding system shown in Fig. 1.
Fig. 5 is the block diagram for showing another example of second encoder included in video coding system shown in Fig. 1.
Fig. 6 is shown according to some exemplary embodiments of the disclosure in response to detecting quality in video coding apparatus
It deteriorates to redistribute the flow chart of the method for the frame for being input into the first encoder and second encoder.
Fig. 7 is shown according to some exemplary embodiments of the disclosure in response to detecting quality in video coding apparatus
It deteriorates to redistribute the figure of the method for the frame for being input into the first encoder and second encoder.
Fig. 8 is shown according to some exemplary embodiments of the disclosure in response to detecting quality in video coding apparatus
It deteriorates to redistribute the figure of the method for the frame for being input into the first encoder and second encoder.
[explanation of symbol]
10: video coding system；
50: video source；
100: Video coding device；
110: preprocessor circuit；
130: processor；
140: first memory；
150: display controller；
160: Memory Controller；
170: bus；
180: modem；
190: user interface；
200: display；
210: input device；
220: second memory；
310: the first encoders；
311,321: division unit；
312: prediction module；
312a: moltion estimation module；
312b: motion compensating module；
312c: intra-framed prediction module；
312d: switch；
313,323: compression module；
313a, 323a: conversion module；
313b, 323b: quantifying unit；
313c, 323c: inverse quantization module；
313d, 323d: inverse transform block；
314,324: Rate control module；
315: decoded picture buffering device (DPB)；
316,325: filter cell；
317,327: entropy code unit；
318,328: subtracter；
319,329: adder；
320: second encoder；
322: prediction block generation module；
326: post-processing module；
A: block；
1: the first bit stream of BIT STREAM；
2: the second bit stream of BIT STREAM；
F1: first frame；
F2: the second frame；
F3: third frame；
F4: the four frame；
FI1: the second data；
FI2: third data；
I1: the first information；
I2: the second information；
I3: third information；
I4: the four information；
IM: the first data；
S410, S420, S430, S440, S450: operation.
Specific embodiment
Fig. 1 is the block diagram for showing the video coding system according to some exemplary embodiments of the disclosure.
Referring to Fig.1, video coding system 10 may include that can shoot video, processing video and show, store or transmit institute
The various devices of the video of processing.
For example, video coding system 10 can be implemented as one of following: TV (television, TV), number
Word TV (digital TV, DTV), Internet protocol television (Internet protocol TV, IPTV), personal computer
(personal computer, PC), desktop computer (desktop computer), laptop computer (laptop
Computer), computer workstation, tablet personal computer, video gaming platforms/video game machine, server and mobile meter
Calculate device.The mobile computing device can be implemented as mobile phone, smart phone, mathematic for business assistant (enterprise
Digital assistant, EDA), digital camera (digital still camera), digital camera (digital
Video camera), portable media player (portable multimedia player, PMP), personal navigator
Part/portable navigation device (personal/portable navigation device, PND), mobile Internet device
(mobile Internet device, MID), wearable computer, Internet of Things (Internet of things, IOT) device
Part, all things on earth interconnection (Internet of everything, IOE) device or e-book (electronic book, e-book).
However, exemplary embodiment is not limited only to this.
Video coding system 10 may include video source 50, Video coding device 100, display 200, input device 210 and
Second memory 220 (" memory 2 ").
Video source 50, Video coding device 100, display 200, input device 210 and second memory 220 are for realizing
It is not necessarily all essential for video coding system 10, and video coding system 10 may include more than element shown in Fig. 1
Or less element.
Video coding device 100 can be implemented as System on Chip/SoC (system-on-chip, SoC).
Video source 50 can be implemented as equipped with such as charge-coupled device (charge-coupled device, CCD) or
Complementary metal oxide semiconductor (complementary metal-oxide-semiconductor, CMOS) imaging sensor
Camera.
Video source 50 can be generated the first data IM about target by the image of photographic subjects and can be by the first data
IM is provided to Video coding device 100.
First data IM can be Still image data or moving image data.In some exemplary embodiments, video source
50 may include in host.In this case, the first data IM can be the image data provided by host.
Video coding device 100 can control the general operation of video coding system 10.
For example, Video coding device 100 may include that can be executed according to some exemplary embodiments of the disclosure
The integrated circuit (integrated circuit, IC) of operation, motherboard, application processor (application processor,
) and/or mobile application processor AP.
Video coding device 100 can carry out the first data IM exported by video source 50 to handle and can pass through display
200 displays will be handled data and be stored in second memory 220 and/or will be handled data transmission to separately through handling data
One data processing system.
Video coding device 100 may include preprocessor circuit 110, the first encoder 310 (" encoder 1 "), second
Encoder 320 (" encoder 2 "), processor 130, first memory 140 (" memory 1 "), display controller 150, memory
Controller 160, bus 170, modem 180 and user interface (interface, I/F) 190.
Preprocessor circuit 110, the first encoder 310, second encoder 320, processor 130, first memory
140, display controller 150, Memory Controller 160, bus 170, modem 180 and user interface 190 are for realizing
It is not necessarily all essential for Video coding device 100, and Video coding device 100 may include more than element shown in Fig. 1
More or less element.
First encoder 310, processor 130, first memory 140, display controller 150, is deposited at second encoder 320
Memory controller 160, modem 180 and user interface 190 can be by buses 170 come exchanging data with one another.
For example, bus 170 can be implemented as at least one of following: peripheral component interconnection (peripheral
Component interconnect, PCI) bus, quick (PCI express, the PCIe) bus, advanced micro- of peripheral component interconnection
Controller bus framework (advanced microcontroller bus architecture, AMBA), Advanced High-Performance Bus
(advanced high performance bus, AHB), advanced peripheral bus (advanced peripheral bus,
APB), Advanced extensible Interface (advanced extensible interface, AXI) bus, and combinations thereof, but the disclosure
It is not limited only to this.
Preprocessor circuit 110 may include for example image-signal processor (image signal processor,
ISP).The first data IM with the first data format can be converted into the second data FI1 and third data FI2 by ISP.
For example, the first data IM can be the data with Bayer pattern (Bayer pattern), and the second data
FI1 and third data FI2 can be yuv data.However, exemplary embodiment is not limited only to this example.
Preprocessor circuit 110 can receive the first data IM exported by video source 50.Preprocessor circuit 110 can
To the first data IM carry out processing and can by by the first data IM carry out processing acquisition the second data FI1 and third data
FI2 is provided respectively to the first encoder 310 and second encoder 320.
It can frame (or picture) be for example unit to mention in the environment wherein driven to Video coding device 100
For the first data IM, the second data FI1 and third data FI2.
For example, the first data IM can be for multiple first frames to the data group of the 4th frame F1, F2, F3 and F4.
Second frame F2 can be the frame after first frame F1.Third frame F3 can be the frame after the second frame F2.4th frame F4 can
For the frame after third frame F3.
Be sent to the first encoder 310 the second data FI1 can for comprising about first frame F1 into the 4th frame F4
The data group of the data of odd-numbered frame (for example, first frame F1 and third frame F3).It is sent to the third number of second encoder 320
It can be the data comprising the even frame (for example, second frame F2 and the 4th frame F4) about first frame F1 into the 4th frame F4 according to FI2
Data group.
Preprocessor circuit 110 is shown as implementing in Fig. 1 in the inside of Video coding device 100, but exemplary
Embodiment is not limited only to this.That is, preprocessor circuit 110 can be embodied in the outside of Video coding device 100.
For example, the first encoder 310 can encode odd-numbered frame (for example, first frame F1 and third frame F3).?
In this example, second encoder 320 can encode the second frame F2, and the second frame F2 is the frame after first frame F1.So
And exemplary embodiment is not limited only to this example.That is, alternatively, if even frame (for example, the
Two frame F2 and the 4th frame F4) be assigned to or be redistributed into the first encoder 310, then the first encoder 310 can be to second
Frame F2 and the 4th frame F4 are encoded.
At least one of the first information, the second information and third information can be transmitted to the second volume by the first encoder 310
Code device 320, the first information, the second information and third information are to included multiple in first frame F1 (or third frame F3)
It is that each of block obtains during being encoded and related to moltion estimation, related with intra prediction respectively and with it is logical
It is related to cross the quantization parameter value that Rate control module (not shown) determines.
Second encoder 320 can be during encoding each of multiple blocks included in the second frame F2 not
At least one of execute motion prediction, intra prediction and quantization parameter value is adjusted.But second encoder 320 can
At least one of the first information, the second information and third information are received, and can be the multiple included by the second frame F2
Each of block generates prediction block.
In some exemplary embodiments, the first encoder 310 can be full coding device, and second encoder 320 can be portion
Constituent encoder.That is, some elements in the element of the first encoder 310 can be not provided in second encoder 320.
For example, the first encoder 310 may include processing circuit to execute in Rate control module, moltion estimation module and/or frame
The function of prediction module, and second encoder 320 may not include and execute Rate control module, moltion estimation module and intra prediction
The processing circuit of the function of at least one of module.
For example following video code model: joint photographic experts group can be used in first encoder 310 and second encoder 320
(Joint Picture Expert Group, JPEG), motion characteristics planning (Motion Picture Expert Group,
MPEG), MPEG-2, MPEG-4, Video coding (video coding, VC) -1, H.264, H.265 or efficient video coding
(high efficiency video coding, HEVC), but exemplary embodiment is not limited only to this.
Processor 130 can control the operation of Video coding device 100.
Processor 130 may include processing circuit and memory (not shown).
Memory (not shown) may include volatile memory, nonvolatile memory, random access memory
In (random access memory, RAM), flash memories (flash memory), hard disk drive and CD drive
At least one.
Processing circuit can be but be not limited to processor, central processing unit (Central Processing Unit, CPU), control
Device processed, arithmetic logic unit (arithmetic logic unit, ALU), digital signal processor (digital signal
Processor), microcomputer, field programmable gate array (field programmable gate array, FPGA), application
Specific integrated circuit (Application Specific Integrated Circuit, ASIC), System on Chip/SoC (System-
On-Chip, SoC), programmable logic cells, microprocessor or can with institute's definition mode execute operation any other device.
Processor 130 can receive user's input to run one or more application (for example, software application).By handling
Some applications in application that device 130 is run can apply (video call application) for video call.In addition, by
The application that reason device 130 is run may include operating system (operating system, OS), the application of word processing device, media player
Using, video game application and/or graphical user interface (graphic user interface, GUI) application, but the disclosure is simultaneously
It is non-to be only limitted to this.
Processor 130 can be by layout designs or can by executing the computer that is stored in memory (not shown)
Reading instruction and be configured to special purpose computer to control preprocessor circuit 110 for odd-numbered frame (for example, first frame F1 and third
Frame F3) it is assigned to the first encoder 310 and even frame (for example, second frame F2 and the 4th frame F4) is assigned to second encoder
320.That is, processor 130 can determine whether that those frames will be assigned to the first encoder 310 and second encoder 320.Cause
This, processing circuit can improve the function of Video coding device 100 itself in the following manner: by frame from second encoder 320
The first encoder 310 is re-assigned to so that the frame can be by the first encoder with circuit corresponding with prediction module
310 are recompiled, to correct the image quality deterioration of the frame.
Frame data can be assigned to the first encoder 310 and second encoder 320 in various ways by processor 130.Citing
For, even frame (for example, second frame F2 and the 4th frame F4) can be assigned to the first encoder 310 and by odd number by processor 130
Frame (for example, first frame F1 and third frame F3) is assigned to second encoder 320.
In some exemplary embodiments, if from and being decoded to the image encoded by second encoder 320
The frame of acquisition detects quality deterioration, then processor 130 can divide again the frame obtained and being encoded by second encoder 320
It is fitted on the first encoder 310 and the frame for being located at after the frame that is obtained and being encoded by second encoder 320 can be assigned to the
Two encoders 320.In this case, the frame for being assigned to the first encoder 310 and second encoder 320 can change.
As an example it is assumed that the first encoder 310 carries out coding and second encoder 320 to the second frame F2 to first frame F1
It is encoded, then if detecting quality deterioration from the data obtained and being decoded to encoded second frame, processing
Second frame F2 can be re-assigned to the first encoder 310 by device 130.Then, processor 130 can will be located at after the second frame F2
Frame (for example, third frame F3) is assigned to second encoder 320.
First memory 140 can will be about the second data FI1 and third data under the control of Memory Controller 160
FI2's is currently just being transmitted to the first encoder by the information for the present frame that the first encoder 310 and second encoder 320 encode
310 and second encoder 320.
Memory Controller 160 can will be by under the control of the first encoder 310, second encoder 320 or processor 130
First encoder 310 and the data encoded of second encoder 320 or the data (for example, bit stream) exported by processor 130 write-in
To second memory 220.
First memory 140 can be implemented as volatile memory, but exemplary embodiment is not limited only to this.Volatibility
Memory can be used as random access memory (random access memory, RAM), static random access memory
(static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), Synchronous Dynamic Random Access Memory
(synchronous DRAM, SDRAM), thyristor random access memory (thyristor RAM, T-RAM), zero capacitor with
Machine accesses memory (zero capacitor RAM, Z-RAM) or pair transistor random access memory (twin
Transistor RAM, TTRAM) it provides.Alternatively, first memory 140 can be implemented as non-volatile deposit
Reservoir.
Second memory 220 can be implemented as nonvolatile memory, but exemplary embodiment is not limited only to this.It is non-easy
The property lost memory can be by as Electrically Erasable Programmable Read-Only Memory (electrically erasable programmable
Read-only memory, EEPROM), flash memories, magnetic RAM (magnetic RAM, MRAM), from
Rotation moves torque magnetic RAM (spin-transfer torque MRAM), ferroelectric RAM
(ferroelectric RAM, FeRAM), phase change random access memory devices (phase change RAM, PRAM) or resistance-type with
Machine accesses memory (resistive RAM, RRAM) and provides.In addition, nonvolatile memory can be used as multimedia card
(multimedia card, MMC), embedded multi-media card (embedded MMC, eMMC), Common Flash Memory storage
(universal flash storage, UFS), solid state drive (solid-state drive, SSD) or solid-state disk
(solid-state disk, SSD), universal serial bus (universal serial bus, USB) flash drive or hard disk
Driver (hard disk drive, HDD) provides.Alternatively, second memory 220 can be implemented as volatile
Property memory.
Fig. 1 shows wherein second memory 220 and the example outside Video coding device 100, but exemplary implementation is arranged in
Example is not limited only to this.In another example, second memory 220 may be provided inside Video coding device 100.
Display controller 150 can pass the data exported by the first encoder 310, second encoder 320 or processor 130
It is sent to display 200.It is aobvious that display 200 can be implemented as monitor, televimonitor, projection device, tft liquid crystal
Show device (thin film transistor-liquid crystal display, TFT-LCD), light emitting diode (light-
Emitting diode, LED) display, Organic Light Emitting Diode (organic LED, OLED) display, active matrix be organic
Light emitting diode (active-matrix OLED, AMOLED) display or flexible display.
For example, display controller 150 can pass through Mobile Industry Processor Interface (mobile industry
Processor interface, MIPI) display serial line interface (display serial interface, DSI) passes data
It is sent to display 200.
Input device 210 can receive user's input from user and may be in response to received user's input for input signal
It is transmitted to user interface 190.
Input device 210 can be implemented as touch panel, touch screen, speech recognition device, felt pen, keyboard, mouse or rail
Mark point (track point), but exemplary embodiment is not limited only to this.For example, input device 210 is to touch wherein
In the situation of screen, input device 210 may include touch panel and touch panel controller.Input device 210 may be connected to display
It device 200 and can be performed separately with display 200.
Input signal can be transmitted to user interface 190 by input device 210.
The data transmission that user interface 190 can receive input signal and can will be generated by input signal from input device 210
To processor 130.
Modem 180 can be used wireless communication technique will be by the first encoder 310, second encoder 320 or processing
The data that device 130 encodes are output to outside.Modem 180 can be used wireless communication technique, such as (for example) WiFi,
WiMAX (wireless broadband, Wibro), 3G wireless communication, long term evolution (Long Term Evolution,
LTE), senior long term evolution (Long Term Evolution-Advanced, LTE-A) or broadband senior long term evolution, but show
Example property embodiment is not limited only to this.
Fig. 2 is the block diagram for showing the example of the first encoder included in Video coding device shown in Fig. 1.
Referring to Fig. 2, the first encoder 310 can be to include and division unit 311, prediction module 312, compression module 313, speed
Rate control module 314,315, filter cell 316, entropy decoded picture buffering device (decoding picture buffer, DPB)
Coding unit 317, the field programmable gate array (FPGA) of subtracter 318 and the corresponding processing circuit of adder 319, using special
With integrated circuit (ASIC), System on Chip/SoC (SoC).
Element shown in Fig. 2 is not necessarily all essential, and the first encoder for realizing the first encoder 310
310 may include element more more or fewer than element shown in Fig. 2.
The current present frame (for example, first frame F1) just encoded of second data FI1 can be divided by division unit 311
Multiple blocks.
Prediction module 312 can execute intra prediction or inter-prediction to first frame F1.
Intra prediction is the prediction mode for executing prediction only with reference to present frame, and inter-prediction is not only with reference to present frame
But also the prediction mode of prediction is executed with reference to other frames.
Prediction module 312 may include moltion estimation module 312a, motion compensating module 312b, intra-framed prediction module 312c and
Switch 312d.
Present frame can be divided into proper number block of a size suitable by moltion estimation module 312a, to generate most
Small distortion simultaneously minimizes the number of produced position.Moltion estimation module 312a can be from various moltion estimation modes (for example, normal
Mode, merging patterns etc.) in selection can generate minimal distortion and minimum number of bits purpose moltion estimation mode.Moltion estimation module
312a can be by searching for the reference picture being stored in DPB 315 to find and be input into the block of prediction module 312 most
Matched region obtains motion vector.
Motion compensating module 312b can by using by moltion estimation module 312a and be stored in DPB 315 with reference to figure
Prediction block is generated as the motion vector execution motion compensation of acquisition.
Present frame can be divided into proper number block of a size suitable to generate most by intra-framed prediction module 312c
Small distortion simultaneously minimizes the number of produced position.Intra-framed prediction module 312c can be from various intra prediction modes (for example, DC mould
Formula and plane mode (planar mode)) in selection can generate minimal distortion and minimum number of bits purpose intra prediction mode.In frame
Prediction module 312c can be by using the pixel for being encoded block near the current block of present frame currently just encoded
Value executes spatial prediction to generate prediction block.
After executing intra prediction and inter-prediction the two, prediction module 312 can be used to be calculated by following equation (1)
Value at cost J come determine execute intra prediction or execute inter-prediction:
J=D+A*R ... (1)
Wherein D indicates the distortion index of coded images, and A indicates the constant value proportional to quantization parameter value, and R is indicated
The bits number generated by intra prediction or inter-prediction.
If determining that execution inter-prediction is suitable based on value at cost J, switch 312d can be used to execute for prediction module 312
Inter-prediction.If determining that execution intra prediction is suitable based on value at cost J, switch 312d can be used to hold for prediction module 312
Row intra prediction.
In some exemplary embodiments, in the situation for wherein executing inter-prediction in the first encoder 310, first
Encoder 310 can transmit the first information I1 about moltion estimation to second encoder 320, and first information I1 includes in following
At least one: the information about the block for having undergone moltion estimation is (for example, undergone the size and number of the block of moltion estimation
Mesh), the information about used moltion estimation mode, the information and motion vector information about reference frame.
In some exemplary embodiments, in the situation for wherein executing intra prediction in the first encoder 310, first
Encoder 310 can transmit the second information I2 about intra prediction to second encoder 320, and the second information I2 includes in following
At least one: the information about the block for having undergone intra prediction is (for example, undergone the size and number of the block of intra prediction
Mesh), the information about used intra prediction mode and the information about reference block.
Subtracter 318 can difference between current block based on present frame and the prediction block generated by prediction module 312
Different generation remains block.Remaining block can be the block of the difference between the current block and prediction block of expression present frame.
Prediction block can be used to control each of multiple blocks included in present frame in Rate control module 314
Quantization parameter value.
In some exemplary embodiments, the first encoder 310 can transmit third information I3 to second encoder 320, the
Three information I3 are related with the quantization parameter value determined by Rate control module 314.
Compression module 313 may include conversion module 313a, quantifying unit 313b, inverse quantization module 313c and inverse transform block
313d。
Conversion module 313a can form the block data come from residual block transform.Conversion module 313a can be used discrete
Cosine transform (discrete cosine transform, DCT) or wavelet transformation (wavelet transform).By transformation mould
The transformation coefficient that block 313a is generated may pass to quantifying unit 313b.
Quantifying unit 313b can be according to the quantization parameter value determined by Rate control module 314 come to the transformation coefficient amount of progress
Change, and exportable quantized coefficient.Quantifying unit 313b can reduce bits number by being quantified to transformation coefficient.It crosses herein
Cheng Zhong, Rate control module 314 can carry out adjustment quantization degree by adjusting quantization parameter value.
Quantized coefficient can be by inverse quantization module 313c inverse quantization and can be by inverse transform block 313d inverse transformation.Through inverse quantization
And the coefficient of inverse transformation can be added to prediction block by adder 319, to generate reconstructed block.
Reconstructed block can be filtered out by filter cell 316.Filter cell 316 can be to reconstructed block
Adaptively deviate using de-blocking filtering device (deblocking filter), sample (sample adaptive offset,
SAO) at least one of filter and auto-adaptive loop filter (adaptive loop filter, ALF).Pass through filter
The reconstructed block that unit 316 filters out is storable in DPB 315.
Entropy code unit 317 can be joined according to based on the value calculated by quantifying unit 313b or the coding calculated during coding
The probability distribution of numerical value carries out symbol entropy coding and can therefore exporting the first bit stream " BIT STREAM 1 ".Entropy coding is one
Kind receives the symbol with various values and is decodable binary sequence by the symbolic formulation, can eliminate statistical redundancy simultaneously
The method of (statistical redundancy).
Symbol can refer to syntax elements to be encoded, coding parameter or residual block.As needed for progress encoding and decoding
The coding parameter of parameter can be not only comprising being encoded by code devices and being transferred to the information of decoding device (for example, syntax is first
Element), but also include the information that will be inferred to during coding or decoding, and coding parameter can be that image is encoded or solved
Information necessary to code.The example of coding parameter include value or statistical information, such as intra prediction mode/inter-frame forecast mode,
Motion vector, encoded block pattern, whether there is residual area at reference picture index (reference picture indexes)
Block, transformation coefficient, quantified transformation coefficient, quantization parameter value, block size and block division information.
It, can be by the way that the bit allocation of peanut will be counted to the symbol with high probability of occurrence and greatly when application entropy coding
Purpose bit allocation reduces the bit stream size of symbol to be encoded to the symbol with lower probability of occurrence.Therefore, pass through entropy coding
The compression performance of Video coding can be enhanced.
For entropy coding, such as Exp-Golomb (exponential Golomb), context-adaptive can be used
Variable length code (context-adaptive variable length coding, CAVLC) or context-adaptive two into
The coding methods such as arithmetic coding (context-adaptive binary arithmetic coding, CABAC) processed.Citing comes
It says, the table for executing entropy coding can be stored in entropy code unit 317 (for example, variable length code/code (variable
Length coding/code, VLC) table), and stored VLC table can be used to execute entropy coding for entropy code unit 317.Separately
Outside, entropy code unit 317 can export aiming symbol binarizing method (binarization method) and aiming symbol/
The probabilistic model of position (bin) and binarizing method or probabilistic model derived from institute can be used then to execute entropy coding.
Fig. 3 to Fig. 5 is the block diagram for showing the example of second encoder included in Video coding device shown in Fig. 1.
Referring to Fig. 3, second encoder 320 can be to include and division unit 321, prediction block generation module 322, compression mould
Block 323, filter cell 325, post-processing module 326, entropy code unit 327, subtracter 328 and the corresponding place of adder 329
Manage field programmable gate array (FPGA), application specific integrated circuit (ASIC), the System on Chip/SoC (SoC) of circuit.
Element shown in Fig. 3 is not necessarily all essential, and second encoder for realizing second encoder 320
320 may include element more more or fewer than element shown in Fig. 3.
The second frame F2 included in third data FI2 can be divided into multiple blocks by division unit 321.Second frame F2 can
For the frame after the first frame F1 encoded by the first encoder 310.
Different from the first encoder 310 shown in Fig. 2, second encoder 320 be may not include with prediction module (for example, Fig. 2 institute
Show prediction module 312) corresponding processing circuit.But second encoder 320 may include prediction block generation module 322.
Prediction block generation module 322 can receive first information I1 or the second information I2 from the first encoder 310 and can produce
Raw prediction block.
Second frame F2 is the frame after the first frame F1 and therefore probably similar to first frame F1.Therefore, second
Encoder 320 can under conditions of without intra-framed prediction module or moltion estimation module only by with the first encoder 310
It is pre- to generate to be shared in the information for executing to first frame F1 and being generated during intra prediction or moltion estimation by the first encoder 310
Survey block.
For example, wherein from the situation that the first encoder 310 receives about the first information I1 of moltion estimation,
Prediction block generation module 322 can be mended by being moved based on first information I1 to multiple onblock executings included in the second frame F2
It repays to generate prediction block, first information I1 includes at least one of following: the letter about the block for having undergone moltion estimation
Cease (for example, size and number for having undergone the block of moltion estimation), about used moltion estimation mode information, about
The information and motion vector information of reference frame.
In another example, wherein receiving the second information I2's about intra prediction from the first encoder 310
In situation, prediction block generation module 322 can be each in block included in the second frame F2 based on the second information I2
Block generates prediction block, and the second information I2 includes at least one of following: the letter about the block for having undergone intra prediction
Cease (for example, size and number for having undergone the block of intra prediction), about used intra prediction mode information and
Information about reference frame.
In general, moltion estimation module has maximum size in typical encoder.Therefore, by not compiled second
Moltion estimation module is provided in code device 320 and intra-framed prediction module, the size of second encoder 320 are significantly reduced.Therefore, may be used
Image is encoded with high frame rate using multiple encoders while the size for making code devices minimizes.
In some exemplary embodiments, moltion estimation module shown in Fig. 2 can be only not provided in second encoder 320
312a.In this case, intra prediction can be performed without executing inter-prediction in prediction block generation module 322.Therefore, it predicts
Block generation module 322 only can receive first information I1 from the first encoder 310.
Subtracter 328 can current current block just encoded based on the second frame F2 with by prediction block generation module
Difference between 322 prediction blocks generated generates residual block.Remain block can for indicate the second frame F2 current block with
The block of difference between prediction block.
Compression module 323 may include conversion module 323a, quantifying unit 323b, inverse quantization module 323c and inverse transform block
323d。
Conversion module 323a can form the block data come from residual block transform.DCT can be used in conversion module 323a
Or wavelet transformation.Quantifying unit 323b may pass to by the transformation coefficient that conversion module 323a is generated.
In some exemplary embodiments, quantifying unit 323b can receive third information I3, third information I3 with by first
The quantization parameter value that the Rate control module 314 of encoder 310 determines is related.Quantifying unit 323b can be based on from the first encoder
310 received third information I3 carry out adjusting quantization parameter value.Quantifying unit 323b can according to adjusted quantization parameter value come pair
Transformation coefficient carries out quantization and exportable quantized coefficient.
As illustrated above, the second frame F2 is the frame after the first frame F1 and therefore probably and first frame
F1 is similar.Therefore, even if using identical quantization parameter value, also far less likely to occur problem.Therefore, by not in the second coding
Rate control module is provided in device 320 and by determining quantization based on the third information I3 received from the first encoder 310
Parameter value can reduce the size of second encoder 320.
Referring to Fig. 4, in some exemplary embodiments, second encoder 320 may include Rate control module 324.At this
In kind situation, it is different from example shown in Fig. 3, quantifying unit 323b can not receive third information I3 from the first encoder 310.Rate
Prediction block can be used to adjust the quantization parameter of each of multiple blocks included in present frame in control module 324
Value.Quantifying unit 323b can quantify transformation coefficient according to the quantization parameter value determined by Rate control module 324, and can
Export quantized coefficient.Other than Rate control module 324, all elements of second encoder 320 shown in Fig. 4 are and Fig. 3
The corresponding counter element of shown second encoder 320 is identical, and therefore by description is omitted.
Referring again to Fig. 3, quantized coefficient can be by inverse quantization module 323c inverse quantization and can be anti-by inverse transform block 323d
Transformation.Coefficient through inverse quantization and inverse transformation can be added to prediction block by adder 329, to generate reconstructed block.
Reconstructed block can be filtered out by filter cell 325.Filter cell 325 can be to reconstructed block
Using at least one of de-blocking filtering device, SAO filter and ALF.It is filtered out by filter cell 325 reconstructed
Block may pass to post-processing module 326.
Post-processing module 326 can receive reconstructed block and frame can be reconstructed.Post-processing module 326 can will through weight
The frame of structure is compared with the second frame F2 encoded by second encoder 320.If the comparison indicate that quality deterioration, then locate afterwards
Reason module 326 can will indicate that the 4th information I4 for quality deterioration occurred is transmitted to processor 130 shown in Fig. 1.If reconstructed
Frame and the second frame F2 between difference be more than predefined level, then post-processing module 326, which can determine, has there is quality deterioration.
Referring to Fig. 5, post-processing module 326 can be received multiple block A by the first encoder 310 and can produce third frame.
The multiple block A can to carry out being obtained by dividing block to first frame F1 by division unit 311 as shown in Figure 2, or
It can be the block reconstructed by filter cell 316 shown in Fig. 2.Post-processing module 326 can be used through filter list shown in Fig. 5
First 325 received reconstruct blocks generate the 4th frame.
Post-processing module 326 can be compared third frame with the 4th frame and if difference between third frame and the 4th frame
It is (or alternatively, predefined) horizontal more than desired, then it can determine quality deterioration occurred.Locate afterwards wherein
Reason module 326 determines in the situation for quality deterioration occurred that expression the 4th of quality deterioration by post-processing module 326 can occur
Information I4 is transmitted to processor 130.
Other than Rate control module 324, all elements of second encoder 320 shown in Fig. 5 are with shown in Fig. 4 second
The corresponding counter element of encoder 320 is identical, and therefore, by description is omitted.
In some exemplary embodiments, wherein receive indicate occurred quality deterioration the 4th information I4 situation
In, frame can be re-assigned to the first encoder 310 and second encoder 320 by processor 130.This will later in reference to Fig. 6 extremely
Fig. 8 is illustrated.
Referring again to Fig. 3, entropy code unit 327 can be according to based on the value calculated by quantifying unit 323b or during coding
The probability distribution of the encoded parameter values of calculating carries out symbol entropy coding and can therefore exporting the second bit stream " BIT STREAM
2".Entropy coding is a kind of to receive the symbol with various values and be decodable binary sequence, simultaneously by the symbolic formulation
The method that statistical redundancy can be eliminated.
It, can be by the way that the bit allocation of peanut will be counted to the symbol with high probability of occurrence and greatly when application entropy coding
Purpose bit allocation reduces the bit stream size of symbol to be encoded to the symbol with lower probability of occurrence.Therefore, pass through entropy coding
The compression performance of Video coding can be enhanced.
For entropy coding, the coding method such as Exp-Golomb, CAVLC or CABAC can be used.For example,
The table (for example, VLC table) for executing entropy coding can be stored in entropy code unit 327, and institute can be used in entropy code unit 327
The VLC table of storage executes entropy coding.In addition, entropy code unit 327 can export the binarizing method and target of aiming symbol
The probabilistic model of symbol/position (bin) and binarizing method or probabilistic model derived from institute can be used then to execute entropy coding.
Fig. 6 is shown according to some exemplary embodiments of the disclosure in response to detecting quality in video coding apparatus
It deteriorates to redistribute the flow chart of the method for the frame for being input into the first encoder and second encoder, and Fig. 7 and Fig. 8 are to show
It is redistributed out according to some exemplary embodiments of the disclosure in response to detecting quality deterioration in video coding apparatus
It is input into the figure of the method for the frame of the first encoder and second encoder.
According to some exemplary embodiments of the disclosure in response to detecting quality deterioration in video coding apparatus come weight
The method for newly distributing the frame for being input into the first encoder and second encoder will be described below, and will be no longer to figure
1 gives repeated explanation to exemplary embodiment shown in Fig. 5.
Referring to Fig. 6, in operation S410, included processor 130 can be to quilt in Video coding device shown in Fig. 1 100
The first encoder 310 and the frame of second encoder 320 shown in Fig. 3 is input to be allocated.
For example, in the situation that wherein input data includes multiple frames, processor 130 can distribute the multiple frame
At making, odd-numbered frame is input into the first encoder 310 and even frame is input into second encoder 320.If the multiple frame exists
Being distributed between first encoder 310 and second encoder 320, which makes different frames be assigned to the first encoder 310 and second, compiles
Different encoder in code device 320, then the frame rate of Video coding device can increase.
For example, referring to Fig. 7, first frame F1 can be assigned to the first encoder 310 and can be by the second frame by processor 130
F2 (that is, being located at the frame after first frame F1) is assigned to second encoder 320.
Referring again to Fig. 6, in operation S420, the first encoder 310 and second encoder 320 can the opposite frames that it is distributed
It is encoded.
In operation S430, the included detectable quality deterioration of post-processing module 326 in second encoder 320.
As discussed above with reference to Fig. 1 to Fig. 5, can be not provided in second encoder 320 execute intra prediction or
The prediction module of inter-prediction.But second encoder 320 can be received from the first encoder 310 about intra prediction or interframe
The information of prediction and it can produce prediction block.
Referring to Fig. 7, if what the second frame F2 encoded by second encoder 320 was different from being encoded by the first encoder 310
First frame F1 (for example, if the brightness of the second frame F2 different from first frame F1 brightness or if the second frame F2 fortune
Moving vector is different from the motion vector of first frame F1), then it is possible that quality is bad in the frame encoded by second encoder 320
Change.
It has been expounded above by reference to Fig. 3 and Fig. 5 by the method that post-processing module 326 identifies quality deterioration, and because
This will description is omitted.
Referring again to Fig. 6, if post-processing module 326 identifies quality deterioration (S430, yes), then in operation S440,
Expression can have been identified that the information of quality deterioration is transmitted to processor 130 by post-processing module 326.
For example, referring to Fig. 8, if receiving the information for indicating quality deterioration occurred from post-processing module 326,
Second frame F2 can be re-assigned to the when the coding carried out by the first encoder 310 to first frame F1 is completed by processor 130
One encoder 310, and third frame F3 (that is, frame after being located at the second frame F2) can be assigned to second encoder 320.Namely
It says, when being completed by the first encoder 310 to the coding that first frame F1 is carried out, even frame can be assigned to first by processor 130
Encoder 310 and odd-numbered frame can be assigned to second encoder 320.That is, processor 130 can detect quality deterioration
Change the method for salary distribution of frame later.
Referring again to Fig. 6, the first encoder 310 can opposite direction its second frame F2 redistributed encoded, and second compiles
Code device 320 can third frame F3 of its opposite distribution encoded.Different from second encoder 320, the first encoder 310 may include
Prediction module.Therefore, it can be solved by being recompiled in the first encoder 310 to the second frame F2 in the second frame F2
The quality deterioration of middle appearance.
In some exemplary embodiments, if post-processing module 326 detects quality deterioration, processor 130 can be incited somebody to action
The second bit stream " BIT STREAM 2 " generated by second encoder 320 is deleted, without storing or transmitting the second bit stream " BIT
STREAM 2”。
If post-processing module 326 is unidentified out quality deterioration (S430, no), then in operation S450, processor 130 can
Judge whether the frame encoded by the first encoder 310 or second encoder 320 is most end frame.
It is if being most end frame (S450, yes) by the frame that the first encoder 310 or second encoder 320 encode, then achievable
Video coding.On the other hand, if by the frame that the first encoder 310 or second encoder 320 encode be not most end frame (S450,
It is no), then processor 130 can repeat subsequent frame to operate S410, S420, S430, S440 and S450.
The exemplary embodiment of the disclosure is elaborated with reference to attached drawing, however the those skilled in the art in fields can manage
Solution, the disclosure can be executed in other specific forms by the those skilled in the art in fields, and this will not change the disclosure
Technological concept or essential characteristic.In addition, the above exemplary embodiments are only that example is limited without the interest field to the disclosure
System.
Claims (20)
1. a kind of Video coding device, comprising:
First encoder, including prediction circuit, the prediction circuit are configured to:
To one of multiple first onblock executing intra predictions operation included in first frame and inter prediction operating or more
Person, and
If the prediction circuit operates inter prediction operating described in first onblock executing, transmission about moltion estimation
The first information；And
Second encoder, including prediction block generation circuit, the prediction block generation circuit are configured to:
The first information is received from first encoder, and
By being generated based on the first information to multiple second onblock executing operation of motion compensation included in the second frame
Prediction block, second frame are the frames different from the first frame.
2. Video coding device according to claim 1, wherein the first information includes at least one of following: closing
Information in the block for having undergone moltion estimation operation, the information of the mode about moltion estimation operation, about ginseng
Examine the information and motion vector information of frame.
3. Video coding device according to claim 1, wherein
If the prediction circuit is configured to first encoder and executes the intra prediction operation, will be about the frame
Second information of interior prediction operation is transmitted to the second encoder, and
The prediction block generation circuit is configured to receive second information, and is described second based on second information
Included second block generates prediction block and operates without directly using prediction circuit to execute the intra prediction in frame.
4. Video coding device according to claim 3, wherein second information includes at least one of following: closing
Information in the block for having undergone intra prediction operation, the information of the mode about intra prediction operation and about
The information of reference block.
5. Video coding device according to claim 1, wherein
First encoder further includes rate control circuits, and the rate control circuits are configured to determine first block
Quantization parameter value, and
The second encoder further includes compressor circuit, and the compressor circuit includes quantifying unit, and the quantifying unit is configured
At receiving third information and executing quantization operation, the third information is related to the quantization parameter value of first block
Connection.
6. Video coding device according to claim 1, wherein
First encoder further includes first rate control circuit, and the first rate control circuit is configured to determine described
The quantization parameter value of first block, and
The second encoder further includes the second rate control circuits, and second rate control circuits are configured to determine described
The quantization parameter value of second block.
7. Video coding device according to claim 1, further includes:
Processor is configured to the first frame and second frame being separately dispensed into first encoder and described second
Encoder, the first frame and second frame are the frames in multiple frames included in the input image.
8. Video coding device according to claim 7, if wherein the second encoder be configured to from by pair
The reconstructed frame that the data encoded by the second encoder carry out inverse quantization and obtain detects quality deterioration, then by the 4th
Information is transmitted to the processor.
9. Video coding device according to claim 8, wherein if the processor receives the 4th information,
The processor is configured to:
When first encoder completes the coding of the first frame, second frame is divided again from the second encoder
It is fitted on first encoder, and
Third frame is assigned to the second encoder, the third frame is the frame after second frame.
10. a kind of encoder is configured to encode first frame without for executing intra prediction and inter-prediction
One or more of prediction circuit, the encoder includes:
Prediction block generation circuit is configured to receive the first information and the second information from the first encoder, and generates Target area
Block, the first information the second information associated and described with moltion estimation operation is associated with intra prediction operation, and described
One encoder is different from the encoder；And
Post processing circuitry is configured to detect quality deterioration based on reconstructed frame and the first frame, described reconstructed
Frame is obtained by carrying out inverse quantization to the data encoded by the encoder.
11. encoder according to claim 10, wherein the first information is about the fortune executed to the second frame
The information of dynamic estimation operation, second frame are the frames before the first frame.
12. encoder according to claim 11, wherein the first information includes at least one of following: about
Undergo the block of moltion estimation operation information, about moltion estimation operation mode information, about reference frame
Information and motion vector information.
13. encoder according to claim 10, wherein second information is about the frame executed to the second frame
The information of interior prediction operation, second frame are the frames before the first frame.
14. encoder according to claim 13, wherein second information includes at least one of following: about
Undergo the block of intra prediction operation information, about intra prediction operation mode information and about reference area
The information of block.
15. encoder according to claim 10, if wherein the post processing circuitry be configured to the first frame with
Difference between the reconstructed frame is more than to define level, then detects and the quality deterioration has occurred.
16. a kind of Video coding device, comprising:
First encoder；
Second encoder, the second encoder are different from first encoder；And
Processor is configured to:
First frame and the second frame are separately dispensed into the first encoder and second encoder, the first frame and second frame are
Different frame in input picture in included multiple frames, second frame are the frames after the first frame, and
If detecting quality deterioration from the image encoded by the second encoder, the processor is configured to:
After first encoder completes the coding of the first frame, second frame is re-assigned to first coding
Device, and
Third frame is assigned to the second encoder, the third frame is the frame after second frame.
17. Video coding device according to claim 16, wherein first encoder includes prediction circuit, it is described pre-
Slowdown monitoring circuit is configured to:
To one of multiple first onblock executing intra predictions operation included in the first frame and inter prediction operating
Or more persons,
If the first information is transmitted to institute to inter prediction operating described in first onblock executing by first encoder
Second encoder is stated, the first information is associated with moltion estimation operation, and
If first encoder operates intra prediction described in first onblock executing, the second information is transmitted to institute
Second encoder is stated, second information is associated with intra prediction operation.
18. Video coding device according to claim 17, wherein the second encoder is configured to from described first
Encoder receives one or more of the first information and second information, and the second encoder includes:
Prediction block generation circuit, be configured to based on one or more of the first information and second information be
Included multiple second blocks generate prediction block in second frame.
19. Video coding device according to claim 16, if wherein the second encoder is configured to described
Two encoders detect the quality deterioration in second frame, then the 4th information are transmitted to the processor.
20. Video coding device according to claim 19, if wherein the processor is configured to the processor
Receive the 4th information, it is determined that the quality deterioration has occurred.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2017-0133921 | 2017-10-16 | ||
| KR1020170133921A KR102347598B1 (en) | 2017-10-16 | 2017-10-16 | Video encoding device and encoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109672890A true CN109672890A (en) | 2019-04-23 |
| CN109672890B CN109672890B (en) | 2023-04-07 |
Family
ID=66096274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811197684.3A Active CN109672890B (en) | 2017-10-16 | 2018-10-15 | Video encoding device and encoder |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10674160B2 (en) |
| KR (1) | KR102347598B1 (en) |
| CN (1) | CN109672890B (en) |
| TW (1) | TWI816684B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115633176A (en) * | 2022-12-08 | 2023-01-20 | 北京蔚领时代科技有限公司 | Method, device and storage medium for dynamically adjusting length of picture group |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11190810B2 (en) * | 2018-01-26 | 2021-11-30 | Samsung Electronics Co., Ltd. | Device and method for compressing image data using quantization parameter and entropy tables |
| CN115767245A (en) * | 2021-08-30 | 2023-03-07 | 瑞昱半导体股份有限公司 | Video processing system and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6356589B1 (en) * | 1999-01-28 | 2002-03-12 | International Business Machines Corporation | Sharing reference data between multiple encoders parallel encoding a sequence of video frames |
| CN101411203A (en) * | 2006-04-04 | 2009-04-15 | 高通股份有限公司 | Adaptive encoder-assisted frame rate up conversion |
| CN102301717A (en) * | 2009-01-29 | 2011-12-28 | 微软公司 | Video encoding using previously calculated motion information |
| CN106973297A (en) * | 2015-09-22 | 2017-07-21 | 联发科技股份有限公司 | Method for video coding and hybrid video coders |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5978029A (en) | 1997-10-10 | 1999-11-02 | International Business Machines Corporation | Real-time encoding of video sequence employing two encoders and statistical analysis |
| KR100791299B1 (en) | 2006-04-11 | 2008-01-04 | 삼성전자주식회사 | Multi-layer based video encoding method and apparatus thereof |
| EP2025159A4 (en) * | 2006-05-30 | 2013-04-10 | Google Inc | Apparatus, arrangement, method and computer program product for digital video processing |
| JP5437066B2 (en) | 2006-07-10 | 2014-03-12 | トムソン ライセンシング | Method and apparatus for performance improvement in a multi-pass video encoder |
| US20080152014A1 (en) * | 2006-12-21 | 2008-06-26 | On Demand Microelectronics | Method and apparatus for encoding and decoding of video streams |
| KR20110047310A (en) * | 2009-10-30 | 2011-05-09 | 삼성전자주식회사 | Video encoding apparatus and method thereof |
| US20110150074A1 (en) | 2009-12-23 | 2011-06-23 | General Instrument Corporation | Two-pass encoder |
| US8681858B2 (en) | 2009-12-23 | 2014-03-25 | General Instrument Corporation | Rate control for two-pass encoder |
| US9319716B2 (en) * | 2011-01-27 | 2016-04-19 | Qualcomm Incorporated | Performing motion vector prediction for video coding |
| US20130259137A1 (en) * | 2012-03-30 | 2013-10-03 | Google Inc. | System and Method for Multi-Core Hardware Video Encoding And Decoding |
| US8948529B1 (en) | 2012-10-30 | 2015-02-03 | Google Inc. | Multi-pass encoding |
| US9363473B2 (en) | 2012-12-17 | 2016-06-07 | Intel Corporation | Video encoder instances to encode video content via a scene change determination |
| KR20150035318A (en) | 2013-09-27 | 2015-04-06 | 삼성테크윈 주식회사 | Apparatus and method for encoding, camera including the encoding apparatus |
| KR102264840B1 (en) * | 2014-11-27 | 2021-06-15 | 삼성전자주식회사 | Video frame encoding circuit, encoding method thereof and video data transmitting and receiving system including the same |
| KR102483269B1 (en) * | 2016-08-29 | 2023-01-02 | 삼성전자주식회사 | Server apparatus, user terminal apparatus, control methods thereof and streaming system |
| US10115223B2 (en) * | 2017-04-01 | 2018-10-30 | Intel Corporation | Graphics apparatus including a parallelized macro-pipeline |
-
2017
- 2017-10-16 KR KR1020170133921A patent/KR102347598B1/en active IP Right Grant
-
2018
- 2018-04-25 US US15/962,217 patent/US10674160B2/en active Active
- 2018-07-18 TW TW107124713A patent/TWI816684B/en active
- 2018-10-15 CN CN201811197684.3A patent/CN109672890B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6356589B1 (en) * | 1999-01-28 | 2002-03-12 | International Business Machines Corporation | Sharing reference data between multiple encoders parallel encoding a sequence of video frames |
| CN101411203A (en) * | 2006-04-04 | 2009-04-15 | 高通股份有限公司 | Adaptive encoder-assisted frame rate up conversion |
| CN102301717A (en) * | 2009-01-29 | 2011-12-28 | 微软公司 | Video encoding using previously calculated motion information |
| CN106973297A (en) * | 2015-09-22 | 2017-07-21 | 联发科技股份有限公司 | Method for video coding and hybrid video coders |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115633176A (en) * | 2022-12-08 | 2023-01-20 | 北京蔚领时代科技有限公司 | Method, device and storage medium for dynamically adjusting length of picture group |
| CN115633176B (en) * | 2022-12-08 | 2023-03-21 | 北京蔚领时代科技有限公司 | Method, device and storage medium for dynamically adjusting length of picture group |
Also Published As
| Publication number | Publication date |
|---|---|
| US10674160B2 (en) | 2020-06-02 |
| TW201918070A (en) | 2019-05-01 |
| CN109672890B (en) | 2023-04-07 |
| US20190116362A1 (en) | 2019-04-18 |
| TWI816684B (en) | 2023-10-01 |
| KR102347598B1 (en) | 2022-01-05 |
| KR20190042234A (en) | 2019-04-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9351003B2 (en) | Context re-mapping in CABAC encoder | |
| US9392292B2 (en) | Parallel encoding of bypass binary symbols in CABAC encoder | |
| US9762919B2 (en) | Chroma cache architecture in block processing pipelines | |
| US10448027B2 (en) | Method of encoding video data, video encoder performing the same and electronic system including the same | |
| US9473778B2 (en) | Skip thresholding in pipelined video encoders | |
| US9224187B2 (en) | Wavefront order to scan order synchronization | |
| US11019337B2 (en) | Video encoding apparatus | |
| US10291925B2 (en) | Techniques for hardware video encoding | |
| US9336558B2 (en) | Wavefront encoding with parallel bit stream encoding | |
| US20160007046A1 (en) | Estimating rate costs in video encoding operations using entropy encoding statistics | |
| CN109672890A (en) | Video coding device and encoder | |
| US10841659B2 (en) | Video encoding apparatus and video encoding system | |
| TWI688260B (en) | Methods, systems, and devices including an encoder for image processing | |
| US20170013262A1 (en) | Rate control encoding method and rate control encoding device using skip mode information | |
| US10694178B2 (en) | Video processing device for encoding frames constituting hierarchical structure | |
| US10931952B2 (en) | Multi-codec encoder and multi-codec encoding system including the same | |
| TWI834621B (en) | Video encoding apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |