CN109669341B - Method for collecting BPM short wave signal for display and time correction - Google Patents
Method for collecting BPM short wave signal for display and time correction Download PDFInfo
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- CN109669341B CN109669341B CN201811612430.3A CN201811612430A CN109669341B CN 109669341 B CN109669341 B CN 109669341B CN 201811612430 A CN201811612430 A CN 201811612430A CN 109669341 B CN109669341 B CN 109669341B
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- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
- G04R20/06—Decoding time data; Circuits therefor
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Abstract
The invention discloses a method for collecting BPM short wave signals to display and correct time, which comprises the following steps: s1, receiving the short-wave time service signal by using the short-wave receiver; s2, reprocessing the short wave digital signal through the preselector and sending the signal to the FPGA processor; s3, the FPGA processor performs waveform shaping, signal screening and pulse counting on the received short wave digital signals, and sends counting information to a display for displaying; s4, the operator adjusts the threshold level of the short wave digital signal through the threshold adjuster according to the information displayed by the display, filters the clutter, and keeps the effective BPM signal until the regular second time number of one second is displayed on the display; and S5, when the sub-mark time arrives, the FPGA processor automatically calibrates the time and displays the calibrated time through the display. When the method is applied, the problems that the current BPM short wave time correction is difficult and the time correction speed is slow can be solved, and the speed and the efficiency of the BPM short wave time correction are effectively improved.
Description
Technical Field
The invention relates to the technical field of digital signal processing, in particular to a method for collecting BPM (broadband pulse-width modulation) short-wave signals to display and correct time.
Background
Currently, there are various satellite navigation systems in the world, including GPS in the united states, GLONASS in russia, beidou in china, GALILEO in europe, etc., which are called Global Navigation Satellite Systems (GNSS), and can be used to provide services such as time alignment to the world. The GNSS system mainly depends on a satellite to broadcast a time base signal, so that most countries use short-wave time service as an auxiliary means to carry out short-wave time service in a suitable scene.
The short wave information is complex, the types are various, besides the BPM short wave signals, dozens of short wave information such as BSF, ATA, JJY, MSF, WWV/H and the like exist, and the acquisition and identification of the BPM short wave are particularly important in China.
The commonly used BPM short wave timing mode at present mainly monitors the second time by adjusting the receiving threshold level. Because of no intuitive observation mode, the control is mainly carried out by depending on the personal experience of an operator, the synchronization can be completed in a long time, the required time is long, and the time correction efficiency is low.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a method for collecting BPM short wave signals to display and correct time, which can solve the problems of difficult time correction and slow time correction speed of the current BPM short wave and effectively improve the speed and efficiency of the time correction of the BPM short wave.
The invention is realized by the following technical scheme:
a method for collecting BPM short wave signals to display and correct time comprises the following steps:
s1, receiving the short-wave time service signal by using the short-wave receiver, and carrying out amplitude limiting processing;
s2, selecting a short wave digital signal of a frequency band where the BPM signal is located in the short wave time service signal processed by the short wave receiver through the preselector, reprocessing the short wave digital signal, and sending the signal to the FPGA processor;
s3, the FPGA processor performs waveform shaping, signal screening and pulse counting on the received short wave digital signals, and sends counting information to a display for displaying: the signal screening process of the FPGA processor comprises the steps of screening signals which accord with a second time number format and a branch mark format in BPM signals, and the pulse counting process comprises the step of counting the second time numbers;
s4, the operator compares the counting information displayed by the display, adjusts the threshold level of the short wave digital signal in the step S2 through the threshold adjuster, filters the clutter, and keeps the effective BPM signal until the regular second time number of one second is displayed on the display;
and S5, when the sub-mark time arrives, the FPGA processor automatically calibrates the time and displays the calibrated time through the display.
Preferably, in step S1, the short-wave receiver is provided with a short-wave antenna capable of receiving signals of 2.5MHz, 5MHz, 10MHz and 15 MHz.
Preferably, in step S2, the preselector selects the desired signal, suppresses out-of-band interference and image frequency signals, mixes the desired signal with a local oscillator in the mixer to obtain an intermediate frequency signal, sends the intermediate frequency signal to the logarithmic detection amplifier for detection and outputting an amplitude signal, and compares the intermediate frequency signal with the local oscillator by the comparator to output a digital TTL level signal.
Preferably, in step S3, after receiving the TTL level signal, the FPGA processor shapes the TTL level signal waveform, synthesizes the signals connected together, compares the pulse widths of the synthesized signals according to the second time standard 10ms of the BPM signal and the minute standard 300ms of the BPM signal, performs pulse screening with a tolerance of 20%, and counts pulses that are screened and conform to the second time format.
Preferably, in step S5, the FPGA processor performs time calibration by determining the time lag of the second time sign, and the process of automatically calibrating the time includes:
s51, judging the screened signals, and judging whether the signals conform to the sub-label format;
s52, carrying out time delay judgment on the signals conforming to the sub-label format, judging whether the time delay conforms to the requirement, and clearing the second time number count if the time delay does not conform to the requirement;
s53, if the time delay meets the requirement, judging whether the second time number count meets the requirement, if the second time number count does not meet the requirement, resetting the second time number count;
and S54, if the second time number count meets the requirement, performing sub-calibration according to the accumulation condition of the second time number, and finally completing the automatic calibration of the time.
The invention has the following advantages and beneficial effects:
1. the invention relates to a method for acquiring BPM (broadband pulse modulation) short wave signals to display and correct time, which can display the BPM short wave signals processed by an FPGA (field programmable gate array) processor in real time through a display and accelerate the BPM receiving threshold level adjustment speed.
2. The invention relates to a method for collecting BPM short wave signals to display and correct time, which can finish time calibration without monitoring BPM second time signals.
3. The invention relates to a method for collecting BPM (broadband pulse-width modulation) short wave signals to display and correct time, which screens the characteristics of the short wave signals, inherits and adopts the marked signals, accelerates the time correction speed, can finish time correction within 1 minute and effectively improves the speed and efficiency of BPM short wave time correction.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a block diagram of the steps of the present invention;
FIG. 2 is a process flow diagram of the FPGA processor of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Examples
A method for collecting BPM short wave signals to display and correct time comprises the following steps:
s1, receiving the short-wave time service signal by using the short-wave receiver, and carrying out amplitude limiting processing;
s2, selecting a short wave digital signal of a frequency band where the BPM signal is located in the short wave time service signal processed by the short wave receiver through the preselector, reprocessing the short wave digital signal, and sending the signal to the FPGA processor;
s3, the FPGA processor performs waveform shaping, signal screening and pulse counting on the received short wave digital signals, and sends counting information to a display for displaying: the signal screening process of the FPGA processor comprises the steps of screening signals which accord with a second time number format and a branch mark format in BPM signals, and the pulse counting process comprises the step of counting the second time numbers;
s4, the operator compares the counting information displayed by the display, adjusts the threshold level of the short wave digital signal in the step S2 through the threshold adjuster, filters the clutter, and keeps the effective BPM signal until the regular second time number of one second is displayed on the display; generally, the clutter power at the current selection frequency is lower than the power of the BPM signal, and the power of the BPM signal is consistent, so that the clutter can be filtered as much as possible by the threshold adjuster, and a valid BPM signal can be retained;
and S5, when the sub-mark time arrives, the FPGA processor automatically calibrates the time and displays the calibrated time through the display.
During concrete implementation, the operator only needs to observe the second time number that the display shows in a contrast way, through adjusting threshold adjustment ware, make show on the display once every second regular second time number can, FPGA treater just can accomplish time calibration automatically afterwards, through this kind of audio-visual observation mode, the operator need not monitor the second time number, just too much individual experience who relies on the operator that just does not also need, and simultaneously, filter to shortwave signal characteristic, inherit the adoption to the signal that has marked, accelerate the timing speed, can accomplish time calibration in 1 minute the fastest, can effectively improve speed and the efficiency of BPM shortwave timing.
In step S1, the short wave receiver is provided with a short wave antenna, and can receive signals of 2.5MHz, 5MHz, 10MHz, and 15MHz, and the common short wave receiver is connected to the short wave antenna through a radio frequency cable to receive and process the short wave time service signal, and the short wave antenna is a broadband whip antenna with a working frequency of 2MHz to 30 MHz.
In step S2, the preselector selects a desired signal, suppresses out-of-band interference and image frequency signals, mixes the selected signal with a local oscillator in a mixer to obtain an intermediate frequency signal, sends the intermediate frequency signal to a logarithmic detection amplifier for detection and outputting an amplitude signal, and compares the intermediate frequency signal with a comparator to output a digital TTL level signal.
In step S3, the FPGA processor shapes the waveforms of the TTL level signals after receiving the TTL level signals, synthesizes the signals connected together, compares the pulse widths of the synthesized signals according to the second time standard 10ms of the BPM signal and the minute mark signal 300ms standard, performs pulse screening with a tolerance of 20%, and counts the pulses that are screened and conform to the second time format. The BPM time signal leads the UTC time by 20ms, and the comprehensive characteristics of the sub-mark signal width (300 ms) and the second time signal width (10 ms) have uniqueness, so that the invention uniquely determines the BPM short-wave signal mainly by screening the characteristics.
When the set frequency is consistent with the frequency of the received BPM short wave signal, the threshold adjuster is adjusted to ensure that the received signal is mainly the BPM short wave signal to a certain extent.
When a plurality of signals are received within 1 second, the current chaotic signals are more, when only 1 signal is received within 1 second and the regular occurrence is presented within each second, the BPM short wave signal is correctly received, and at the moment, the time calibration can be carried out by judging the delay of the second time signal.
And according to the timing scheme, carrying out delay comparison on the second time numbers meeting the requirements, and judging that the current second time number is a normal second time number when the delay is 1s +/-2 ms.
Because the second time signals are lost and signals similar to the second time signal format can appear in normal second time signals, the second pulse accumulation is carried out through an accumulation algorithm, the accuracy of the sub-signals is confirmed according to the accumulation condition of the second time signals at the sub-mark time, and the aim of calibrating the sub-signals is fulfilled.
In step S5, the FPGA processor performs time calibration by determining the time lag of the second time, and the process of automatically calibrating time includes:
s51, judging the screened signals, and judging whether the signals conform to the sub-label format;
s52, carrying out time delay judgment on the signals conforming to the sub-label format, judging whether the time delay conforms to the requirement, and clearing the second time number count if the time delay does not conform to the requirement;
s53, if the time delay meets the requirement, judging whether the second time number count meets the requirement, if the second time number count does not meet the requirement, resetting the second time number count;
and S54, if the second time number count meets the requirement, performing sub-calibration according to the accumulation condition of the second time number, and finally completing the automatic calibration of the time.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (3)
1. A method for collecting BPM short wave signals to display and correct time is characterized by comprising the following steps:
s1, receiving the short-wave time service signal by using the short-wave receiver, and carrying out amplitude limiting processing;
s2, selecting a short wave digital signal of a frequency band where the BPM signal is located in the short wave time service signal processed by the short wave receiver through the preselector, reprocessing the short wave digital signal, and sending the signal to the FPGA processor;
s3, the FPGA processor performs waveform shaping, signal screening and pulse counting on the received short wave digital signals, and sends counting information to a display for displaying: the signal screening process of the FPGA processor comprises the steps of screening signals which accord with a second time number format and a branch mark format in BPM signals, and the pulse counting process comprises the step of counting the second time numbers;
s4, the operator compares the counting information displayed by the display, adjusts the BPM receiving threshold level of the short wave digital signal in the step S2 through the threshold adjuster, filters the clutter, and keeps the effective BPM signal until the regular second time number of one second is displayed on the display;
s5, when the sub-mark moment comes, the FPGA processor automatically calibrates the time and displays the calibrated time through the display;
in step S2, the preselector selects a desired signal, suppresses out-of-band interference and image frequency signals, mixes the signal with a local oscillator in the mixer to obtain an intermediate frequency signal, sends the intermediate frequency signal to a logarithmic detection amplifier for detection and outputs an amplitude signal, and compares the intermediate frequency signal with the local oscillator by the comparator to output a digital TTL level signal;
in step S3, the FPGA processor shapes the waveforms of the TTL level signals after receiving the TTL level signals, synthesizes the signals connected together, compares the pulse widths of the synthesized signals according to the second time standard 10ms of the BPM signal and the minute mark signal 300ms standard, performs pulse screening with a tolerance of 20%, and counts the pulses that are screened and conform to the second time format.
2. The method of claim 1, wherein in step S1, the short wave receiver is provided with a short wave antenna for receiving signals of 2.5MHz, 5MHz, 10MHz and 15 MHz.
3. The method of claim 1, wherein in step S5, the FPGA processor performs time calibration by determining the time lag of the second time sign, and the process of automatically calibrating the time comprises:
s51, judging the screened signals, and judging whether the signals conform to the sub-label format;
s52, carrying out time delay judgment on the signals conforming to the sub-label format, judging whether the time delay conforms to the requirement, and clearing the second time number count if the time delay does not conform to the requirement;
s53, if the time delay meets the requirement, judging whether the second time number count meets the requirement, if the second time number count does not meet the requirement, resetting the second time number count;
and S54, if the second time number count meets the requirement, performing sub-calibration according to the accumulation condition of the second time number, and finally completing the automatic calibration of the time.
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| CN111142366B (en) * | 2019-12-19 | 2021-02-12 | 中国电波传播研究所（中国电子科技集团公司第二十二研究所） | Novel short wave time service method |
| CN111638640B (en) * | 2020-05-27 | 2021-07-06 | 中国科学院国家授时中心 | BPM shortwave time service signal simulator |
| CN112269312A (en) * | 2020-10-21 | 2021-01-26 | 四川汉星航通科技有限公司 | Automatic alignment device for wireless time service signals |
| CN112612319B (en) * | 2021-02-01 | 2024-05-03 | 西安空天电子技术有限公司 | BPM shortwave time number generator |
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