CN109658968A - The operating method of non-volatile memory device - Google Patents

Abstract

The embodiment conceived according to the present invention is related to a kind of method of operating nonvolatile memory device.The described method includes: executing the first programming operation to the first illusory memory cell；Verification operation is executed to the first illusory memory cell using verifying voltage；Determine whether first threshold voltage is higher than verifying voltage；The second programming operation is executed reducing the threshold voltage of the first illusory memory cell from first threshold voltage to the first illusory memory cell in the case where determining that first threshold voltage is higher than verifying voltage.

Description

The operating method of non-volatile memory device

Technical field

Inventive concept is related to a kind of semiconductor memory, more particularly, to a kind of non-volatile memory device and one The operating method of kind non-volatile memory device.

Background technique

Storage device can be deposited in response to the control of host apparatus (computer, smart phone, Intelligent flat etc.) Store up data.Storage device may include the hard disk drive (HDD) of the storing data on disk, or in nonvolatile memory The semiconductor memory of middle storing data.Semiconductor memory can be solid state drive (SSD) or storage card.

Nonvolatile memory may include read-only memory (ROM), programming ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, phase change random access memory devices (PRAM), resistance RAM (RRAM), ferroelectric RAM (FRAM) etc..

Summary of the invention

The embodiment conceived according to the present invention is related to a kind of method of operating nonvolatile memory device.It is described non-volatile Property memory device includes multiple strings, and each string includes along the direction vertical with the surface for being provided with unit string of substrate Stack at least one string select transistor, multiple memory cells, at least one illusory memory cell and at least one Ground selection transistor.The described method includes: executing the first programming to the first illusory memory cell in the multiple unit string Operation, after the first programming operation, the first illusory memory cell has first threshold voltage；Using verifying voltage to the first void If memory cell executes verification operation, verifying voltage is target threshold of the first illusory memory cell after the first programming operation The upper limit of threshold voltage；Determine whether first threshold voltage is higher than verifying voltage；Determining first threshold voltage higher than verifying voltage In the case where, the second programming operation is executed with by the threshold voltage of the first illusory memory cell to the first illusory memory cell It is reduced from first threshold voltage, after the second programming operation, the first illusory memory cell has second threshold voltage.Second threshold Threshold voltage is lower than first threshold voltage.

Another embodiment conceived according to the present invention is related to a kind of method of operating nonvolatile memory device.It is described non- Volatile memory devices include multiple strings, and each string includes along vertical with the surface for being provided with unit string of substrate At least one string select transistor that direction stacks, multiple memory cells, at least one illusory memory cell and at least One ground selection transistor.The described method includes: determining whether to meet inspection condition；Determining the case where meeting inspection condition Under, verifying read operation is executed to the first ground selection transistor in the multiple unit string using the first verifying voltage；It determines Whether the first threshold voltage of the first ground selection transistor is higher than the first verifying voltage；Determining the of the first ground selection transistor In the case that one threshold voltage is higher than the first verifying voltage, to the first, selection transistor executes the first programming operation, to reduce The first threshold voltage of first ground selection transistor.

The another embodiment conceived according to the present invention is related to a kind of method of operating nonvolatile memory device.It is described non- Volatile memory devices include multiple strings, and each string includes along vertical with the surface for being provided with unit string of substrate At least one string select transistor that direction stacks, multiple memory cells, at least one illusory memory cell and at least One ground selection transistor.The described method includes: the first programming operation is executed to the memory cell in the multiple unit string, To improve the first threshold voltage of memory cell, according to the first threshold voltage programmed, programmed memory cell tool There are one of erase status and multiple programming states state；When the ground selection transistor in the multiple unit string, string selection It is right when at least one second threshold voltage of at least one of transistor and illusory memory cell is higher than the first verifying voltage At least one described second programming operation of execution in ground selection transistor, string select transistor and illusory memory cell, with Reduce ground selection transistor, in string select transistor and illusory memory cell it is described at least one it is described at least one the Two threshold voltages；When at least one described second threshold voltage is lower than the second verifying voltage, selection transistor, string are selected over the ground In transistor and illusory memory cell it is described at least one execute third programming operation, with improve it is described at least one second Threshold voltage.

Detailed description of the invention

Describe the exemplary embodiment of inventive concept, the above and other feature of inventive concept in detail by referring to accompanying drawing It will be apparent.

Fig. 1 is the block diagram for showing the nonvolatile memory of the exemplary embodiment according to inventive concept.

Fig. 2 is the circuit diagram for showing the memory block of the exemplary embodiment according to inventive concept.

Fig. 3 is the process for showing the operating method of nonvolatile memory of the exemplary embodiment according to inventive concept Figure.

Fig. 4 shows the threshold value of the cell transistor in the operating method of Fig. 3 of the exemplary embodiment according to inventive concept The variation of voltage.

Fig. 5 is the flow chart for showing the first programming operation of the exemplary embodiment according to inventive concept.

Fig. 6 is to show the electricity for being supplied to memory block in the first programming operation according to the exemplary embodiment of inventive concept The table of pressure.

Fig. 7 is to show the electricity for being supplied to memory block in the first programming operation according to the exemplary embodiment of inventive concept The table of pressure.

Fig. 8 is the flow chart for showing the second programming operation of the exemplary embodiment according to inventive concept.

Fig. 9 is to show the electricity for being supplied to memory block in the second programming operation according to the exemplary embodiment of inventive concept The table of pressure.

Figure 10 shows the unit string for being applied to selection in the second programming operation according to the exemplary embodiment of inventive concept Voltage.

Figure 11 is shown is applied to non-selected unit according to the exemplary embodiment of inventive concept in the second programming operation The voltage of string.

Figure 12 is shown is applied to non-selected unit according to the exemplary embodiment of inventive concept in the second programming operation The voltage of string.

Figure 13 is shown is applied to non-selected unit according to the exemplary embodiment of inventive concept in the second programming operation The voltage of string.

Figure 14 is to show to be supplied to memory block in the second programming operation according to the exemplary embodiment of inventive concept The table of voltage.

Figure 15 shows the unit string for being applied to selection in the second programming operation according to the exemplary embodiment of inventive concept Voltage.

Figure 16 is the flow chart for showing the second programming operation of the exemplary embodiment according to inventive concept.

Figure 17 is to show the level for passing through voltage in the second programming operation according to the exemplary embodiment of inventive concept The timing diagram of control.

Figure 18 is the process for showing the operating method of nonvolatile memory of the exemplary embodiment according to inventive concept Figure.

Figure 19 is the process for showing the operating method of nonvolatile memory of the exemplary embodiment according to inventive concept Figure.

Figure 20 shows the threshold value of cell transistor in the operating method of Figure 19 of the exemplary embodiment according to inventive concept The change of voltage.

Figure 21 is the block diagram for showing the storage device of the exemplary embodiment according to inventive concept.

Figure 22 is the block diagram for showing the Memory Controller of the exemplary embodiment according to inventive concept.

Figure 23 is the block diagram for showing the computing device of the exemplary embodiment according to inventive concept.

Figure 24 shows the perspective view for showing the structure of memory block of the embodiment according to inventive concept.

Figure 25 is the cross-sectional view for showing the structure of memory block of the embodiment according to inventive concept.

Figure 26 shows the example that cell transistor corresponding with interconnecting piece is used as illusory memory cell.

Figure 27 shows the threshold voltage of memory cell when executing programming operation and erasing operation to memory cell Variation.

Figure 28 is the flow chart for showing the method that programming operation is executed to memory cell.

Figure 29 is the flow chart for showing the method that erasing operation is executed to memory cell.

Figure 30 show when executing the first programming operation illusory memory cell, selection transistor or string select transistor Threshold voltage variation.

Figure 31 be show nonvolatile memory check illusory memory cell, selection transistor or string select transistor Threshold voltage and execute the first programming operation method flow chart.

Figure 32 shows the example for being applied to the voltage of memory block.

Figure 33 show when executing the second programming operation illusory memory cell, selection transistor or string select transistor Threshold voltage variation.

Figure 34 be show nonvolatile memory check illusory memory cell, selection transistor or string select transistor Threshold voltage and execute the second programming operation method flow chart.

Figure 35 shows the example for being applied to the voltage of memory block.

Figure 36 shows the example of the inspection condition according to the embodiment of inventive concept.

Figure 37 shows the application example of the memory block of Figure 26.

Specific embodiment

Hereinafter invention structure will be more fully described referring to the attached drawing for the exemplary embodiment for showing inventive concept now Think.However, the invention design can be implemented in many different forms and should not be construed as limited to illustrate herein Embodiment.In the accompanying drawings, for clarity, the size and relative size of layer and region can be exaggerated.Same appended drawing reference Same element is always shown in attached drawing and written explanation.

Fig. 1 is the block diagram for showing the nonvolatile memory 110 according to the exemplary embodiment of inventive concept.Referring to Fig.1, Nonvolatile memory 110 includes memory cell array 111, address (ADDR) decoder circuit 113, page buffer circuit 115, data input/output (I/O) circuit 117 and control logic circuit 119.

Memory cell array 111 includes multiple memory block BLK1-BLKz, in multiple memory block BLK1-BLKz Each memory block has multiple memory cells.Each memory block can by least one selection line GSL, a plurality of word The string of line WL and at least one selection line SSL is connected to address decoder circuit 113.Each memory block can pass through multiple bit lines BL is connected to page buffer circuit 115.Memory block BLK1-BLKz can be commonly connected to bit line BL.Memory block BLK1- The memory cell of BLKz can have identical structure.Each of memory block BLK1-BLKz can be erasing operation unit. Memory cell in memory cell array 111 can be according to a memory block cell erasure.Belong to same memory block Memory cell can be by disposable all erasings.In the exemplary embodiment of inventive concept, each memory block can be with It is divided into multiple sub-blocks.Each sub-block can be erasing operation unit.

Address decoder circuit 113 is connected by a plurality of ground selection line GSL, a plurality of wordline WL with a plurality of string selection line SSL To memory cell array 111.Address decoder circuit 113 is operated according to the control of control logic circuit 119.Address decoding Device circuit 113 can receive the first address AD DR1 from Memory Controller.Address decoder circuit 113 will receive first Address AD DR1 decoding and the voltage that wordline WL is applied to according to the control of decoded address.

For example, program voltage VPGM can be applied to by the first address by address decoder circuit 113 in programming operation The wordline of the selection of the memory block of the selection of ADDR1 instruction, and the memory block of selection will be applied to by voltage VPASS Non-selected wordline.In read operation, selection can be read voltage VRD and is applied to by first by address decoder circuit 113 The wordline of the selection of the memory block of the selection of address AD DR1 instruction, and non-selection voltage VREAD is applied to the storage of selection The non-selected wordline of device block.In erasing operation, address decoder circuit 113 can by erasing voltage (for example, ground voltage or Low-voltage with level similar with ground voltage) be applied to by the first address AD DR1 instruction selection memory block choosing The wordline selected.

Page buffer circuit 115 is connected to memory cell array 111 by multiple bit lines BL.Page buffer circuit 115 Data input/output circuit 117 is connected to by multiple data lines DL.Page buffer circuit 115 is according to control logic circuit 119 Control operation.

Page buffer circuit 115 can store the data that will be programmed in the memory cell of memory cell array 111 Or the data read from the memory cell of memory cell array 111.In programming operation, page buffer circuit 115 can Store the data that will be programmed in a memory cell.Page buffer circuit 115 can make bit line on the basis of the data of storage BL biasing.In programming operation, page buffer circuit 115 can be used as write driver.In read operation, page buffer electricity It is capable of the voltage of sense bit line BL and stores sensing result in road 115.In read operation, page buffer circuit 115 can be used as Sensing amplifier.

Data input/output circuit 117 is connected to page buffer circuit 115 by multiple data lines DL.Data input/defeated Circuit 117 can exchange the first data DATA1 with Memory Controller out.

Data input/output circuit 117 can be stored temporarily from the received first data DATA1 of Memory Controller.Number First data DATA1 of storage can be transferred to Memory Controller according to input/output circuitry 117.Data input/output electricity Road 117 can be used as buffer storage.

Control logic circuit 119 receives the first order CMD1 and control signal CTRL from Memory Controller.Control logic Circuit 119 is by received first order CMD1 decoding and can control the whole of nonvolatile memory 110 according to decoded order Gymnastics is made.

In read operation, logic control circuit 119 can from it is received control signal CTRL in reading enable signal/ RE generates data strobe signal DQS and output data strobe signal DQS.In write operation, control logic circuit 119 can connect Receipts include the data strobe signal DQS in control signal CTRL.

Control logic circuit 119 includes programming Control circuit PC.Programming Control circuit PC can pass through the decoding of control address Device circuit 113 and page buffer circuit 115 control the programming operation of nonvolatile memory 110.For example, programming Control circuit PC can control address decoder circuit 113 and page buffer circuit 115 makes according to the exemplary implementation according to inventive concept The programmed method of example executes programming.

Fig. 2 is the circuit diagram for showing the memory block BLKa according to the exemplary embodiment of inventive concept.Referring to Fig. 2, deposit Reservoir block BLKa includes multiple unit string CS11-CS21 and CS12-CS22.Unit string CS11-CS21 and CS12-CS22 can edges Line direction and column direction arrangement are to form row and column.

For example, the first row can be formed along unit the string CS11 and CS12 of line direction arrangement, along the unit of line direction arrangement String CS21 and CS22 can form the second row.Unit string CS11 and CS21 along column direction arrangement can form first row, along column Unit the string CS12 and CS22 of direction arrangement can form secondary series.

Each unit string CS11-CS21 and CS12-CS22 may include multiple cell transistors.Cell transistor includes ground Selection transistor GSTa and GSTb, memory cell MC1-MC6 and string select transistor SSTa and SSTb.Each unit string Ground selection transistor GSTa and GSTb, memory cell MC1-MC6 and string select transistor SSTa and SSTb can with its On along row and column be disposed with the plane of unit string CS11-CS21 and CS12-CS22 (for example, the formation with substrate has memory block The corresponding plane in the surface of BLKa) it stacks on vertical direction.For example, the transistor of unit string can heap in the height direction It is folded.

Cell transistor can be the electricity of the threshold voltage changed with the quantity according to the charge by insulating layer capture Lotus captures transistor npn npn.

The source electrode of nethermost ground selection transistor GSTa can be commonly connected to common source line CSL.

The control grid of ground the selection transistor GSTa and GSTb of unit string CS11-CS21 and CS12-CS22 can be distinguished It is connected to the ground selection line GSLa and GSLb.The ground selection transistor of sustained height (or sequence), which can connect, to same to be selected The ground selection transistor of line, different height (or sequence) can connect to different ground selection lines.For example, the ground of the first height selects It selects transistor GSTa and is commonly connected to ground selection line GSLa, the ground selection transistor GSTb of the second height is selected with being commonly connected to Line GSLb.

Ground selection transistor with a line can connect to same selection line, and the ground selection transistor that do not go together can be with It is connected to different ground selection lines.For example, ground the selection transistor GSTa and GSTb of unit the string CS11 and CS12 of the first row connect It is connected to the first ground selection line, ground the selection transistor GSTa and GSTb of unit the string CS21 and CS22 of the second row are connected to the second ground Selection line.

Control grid positioned at the memory cell from substrate (or ground selection transistor GST) sustained height (or sequence) can To be commonly connected to same wordline, the control grid being located at from the memory cell of substrate different height (or sequence) can divide It is not connected to different wordline WL1-WL6.For example, memory cell MC1 is commonly connected to wordline WL1.Memory cell MC2 is total It is same to be connected to wordline WL2.Memory cell MC3 is commonly connected to wordline WL3.Memory cell MC4 is commonly connected to wordline WL4.Memory cell MC5 is commonly connected to wordline WL5.Memory cell MC6 is commonly connected to wordline WL6.

In the first string select transistor SSTa of the sustained height (or sequence) of unit string CS11-CS21 and CS12-CS22 Place, the control grid for the first string select transistor SSTa not gone together are respectively connected to different string selection line SSL1a-SSL2a. For example, the first string select transistor SSTa of unit string CS11 and CS12 are commonly connected to string selection line SSL1a.Unit string CS21 String selection line SSL2a is commonly connected to the first string select transistor SSTa of CS22.

In the second string select transistor SSTb of the sustained height (or sequence) of unit string CS11-CS21 and CS12-CS22 Place, the control grid for the second string select transistor SSTb not gone together are respectively connected to different string selection line SSL1b-SSL2b. For example, the second string select transistor SSTb of unit string CS11 and CS12 are commonly connected to string selection line SSL1b.Unit string CS21 String selection line SSL2b is commonly connected to the second string select transistor SSTb of CS22.

The unit that do not go together is connected in series to different string selection lines.With the sustained height (or sequence) of the unit string of a line String select transistor is connected to same string selection line.String with the different height (or sequence) of the unit string of a line selects crystal Pipe is connected to different string selection lines.

String select transistor with the unit string of a line can be commonly connected to a string selection line.For example, the first row The string select transistor SSTa and SSTb of unit string CS11 and CS12 can be commonly connected to a string selection line.For example, string choosing String selection line SSL1a can be commonly connected to by selecting transistor SSTa, and string select transistor SSTb can be commonly connected to string selection Line SSL1b.The string select transistor SSTa and SSTb of unit the string CS21 and CS22 of second row can be commonly connected to a string Selection line.For example, string select transistor SSTa can be commonly connected to string selection line SSL2a, string select transistor SSTb can be with It is commonly connected to string selection line SSL2b.

The column of unit string CS11-CS21 and CS12-CS22 are respectively connected to different bit line BL1 and BL2.For example, first The string select transistor SSTb of unit the string CS11 and CS21 of column are commonly connected to bit line BL1.The unit string CS12 of secondary series and The string select transistor SSTb of CS22 is commonly connected to bit line BL2.

Unit string CS11 and CS12 can form the first plane.Unit string CS21 and CS22 can form the second plane.

In memory block BLKa, the memory cell of each height of each plane can form Physical Page.Physical Page It can be the reading unit and writing unit of memory cell MC1-MC6.For example, can by string selection line SSL1a, SSL1b, A plane of SSL2a and SSL2b selection memory block BLKa.When conducting voltage be provided to string selection line SSL1a and SSL1b, and blanking voltage is provided to when going here and there selection line SSL2a and SSL2b, unit string CS11 and CS12 points of the first plane It is not connected to bit line BL1 and BL2.In other words, the first plane is selected.When conducting voltage be provided to string selection line SSL2a and SSL2b, and blanking voltage is provided to when going here and there selection line SSL1a and SSL1b, unit string CS21 and CS22 points of the second plane It is not connected to bit line BL1 and BL2.In other words, the second plane is selected.In the plane of selection, it can be selected by wordline WL1-WL6 Select a line of memory cell MC.In the row of selection, select voltage that can be applied to the second wordline WL2, non-selection voltage Remaining wordline WL1 and WL3-WL6 can be applied to.In other words, can by control string selection line SSL1a, SSL1b, SSL2a and SSL2b and wordline WL1-WL6 selects Physical Page corresponding with the second wordline WL2 of the second plane.It is being selected Physical Page memory cell MC2 in, write-in or read operation can be executed.

In memory block BLKa, memory cell MC1-MC6 can be executed according to memory block unit or sub-block unit Erasing operation.When executing erasing operation according to memory block unit, the memory cell MC of memory block BLKa can root According to erasing request (for example, the erasing from external memory controller is requested) by disposable all erasings.When according to sub-block list When member executes erasing operation, the part in the memory cell MC1-MC6 of memory block BLKa can request (example according to erasing Such as, the erasing request from external memory controller) by disposable all erasings, remaining part can be prohibited to wipe. Low-voltage (for example, ground voltage or with the voltage with ground voltage similar level) can be provided to the storage for being connected to and being just wiped free of The wordline of device unit is connected to and forbids the wordline of the memory cell of erasing can be floated.

Memory block BLKa shown in Figure 2 is exemplary.Inventive concept is not limited to memory block shown in Figure 2 BLKa.For example, the quantity of the row of unit string can increase or decrease.Quantity with the row of unit string changes, and is connected to unit The string selection line of the row of string or the quantity of ground selection line and the quantity of unit string for being connected to a bit line also can change.

The quantity of the column of unit string can increase or decrease.Quantity with the column of unit string changes, and is connected to unit string Column bit line quantity and be connected to the quantity of unit string of a string selection line and also can change.

The height of unit string can increase or reduce.For example, the ground selection transistor, the memory that include in each unit string The quantity of unit or string select transistor can increase or decrease.

The memory cell MC for belonging to a Physical Page can correspond at least three logical page (LPAGE)s.For example, (k is greater than 2 to k Integer) a bit can be programmed in a memory cell MC.In the memory cell MC for belonging to a Physical Page, quilt K bit being programmed in each memory cell MC can be respectively formed k logical page (LPAGE).

In the exemplary embodiment of inventive concept, three-dimensional (3D) memory array is provided.3D memory array is with one Or more the memory cell array of physical level be monolithically formed, memory cell has setting square active on a silicon substrate Area and the associated circuit of operation with the memory cell.Such associated circuit can be located above such substrate Or in such substrate.Term " monolithic " can refer to that the layer of every grade of array is deposited directly on the layer of each junior's array.

In the exemplary embodiment of inventive concept, 3D memory array includes vertical nand string, and vertical nand string is vertical Orientation is so that at least one processor unit is located above another memory cell.At least one processor unit can wrap Include electric charge capture layer.Each vertical nand string further includes at least one selection transistor above memory cell, described At least one selection transistor has structure identical with memory cell and is jointly monolithically formed with memory cell.

The following patent documents being all incorporated herein by quoting: U.S. Patent number US7,679,133, US8,553,466, US8,654,587, US8,559,235 and U.S. Patent Publication No. US2011/0233648 are described for according to inventive concept The construction of 3 D memory array that uses of exemplary embodiment.In aforementioned patent literature, 3 D memory array is by structure Make as multistage, it is at different levels between shared word line and/or bit line.

Fig. 3 is the process for showing the operating method of nonvolatile memory of the exemplary embodiment according to inventive concept Figure.Referring to figs. 1 to Fig. 3, in step s 110, the first programming operation is executed, so that the threshold voltage of cell transistor improves.Example Such as, the threshold voltage for being chosen as the cell transistor (for example, whole cell transistors) of programming target can be improved.Programming Control Circuit PC, which can be controlled, to be applied to the voltage of memory cell array 111 threshold voltage of cell transistor is improved.

In the step s 120, the second programming operation is executed, thus the list with the threshold voltage higher than verifying voltage VFYu The threshold voltage of first transistor can reduce.For example, can be in the cell transistor for performing the first programming operation to it Cell transistor with the threshold voltage higher than verifying voltage VFYu is programmed so that their threshold voltage by second Programming operation reduces.Verifying voltage VFYu can be the upper limit of the target threshold voltage range of cell transistor.Programming Control electricity Road PC, which can be controlled, is applied to what the voltage of memory cell array 111 made with the threshold voltage higher than verifying voltage VFYu The threshold voltage of cell transistor reduces.

Fig. 4 shows the threshold value electricity of cell transistor in the operating method of Fig. 3 of the exemplary embodiment according to inventive concept The change of pressure.In Fig. 4, horizontal axis indicates that the threshold voltage of cell transistor, the longitudinal axis indicate the quantity of cell transistor.Change speech It, Fig. 4 shows the threshold voltage distribution of cell transistor.

Referring to figs. 1 to Fig. 4, the initial threshold voltage distribution of cell transistor can be indicated by First Line L1.

If executing the first programming operation of step S110, the threshold voltage of cell transistor is improved.For example, unit is brilliant The threshold voltage distribution of body pipe can be changed from First Line L1 to the second line L2 by the first programming operation.

If executing the second programming operation of step S120, the threshold value electricity higher than verifying voltage VFYu of cell transistor Pressure drop is low.For example, the threshold voltage higher than verifying voltage VFYu of cell transistor can become lower than verifying voltage VFYu.It changes The threshold voltage distribution of Yan Zhi, cell transistor can be changed from the second line L2 to third line L3 by the second programming operation.

As described above, if executing the first programming operation and the second programming operation, the threshold voltage point of cell transistor The distribution of the threshold voltage of cloth constriction and cell transistor is only limitted to the level lower than verifying voltage VFYu.For example, being indicated by L3 Threshold voltage distribution width than indicated by L2 threshold voltage distribution width it is small.Due to the threshold voltage of cell transistor Control is in target zone, therefore the reliability of the nonvolatile memory including cell transistor improves.

Fig. 5 is the flow chart for showing the first programming operation of the exemplary embodiment according to inventive concept.Referring to Fig.1, Fig. 2 And low-voltage is supplied to the channel of cell transistor in step S210 by Fig. 5.For example, can by ground voltage or with have with The low-voltage of the similar level of ground voltage is supplied to the channel for being selected as programming the cell transistor of target.

In step S220, high voltage is supplied to the control grid of cell transistor.For example, can will have can draw The high voltage for playing the level of Fowler-Nordheim (F-N) tunnelling is supplied to the cell transistor for being selected as programming target Control grid.

The height electricity of low-voltage due to the channel supplied to cell transistor and the control grid supplied to cell transistor F-N tunnelling occurs in cell transistor for the voltage difference between pressure.Therefore, electronics is trapped in cell transistor, and unit is brilliant The threshold voltage of body pipe can be improved.

In the first programming operation, cell transistor can pass through word line program.For example, belonging in the first programming operation It can be improved in the threshold voltage of the memory cell for the Physical Page for being connected to same wordline.

Fig. 6 is to show to be supplied to memory block BLKa in the first programming operation according to the exemplary embodiment of inventive concept Voltage table.The example of the voltage when memory cell MC is selected as programming target is shown in Fig. 6.

Bit line BL1 and BL2 are applied to referring to Fig. 2 and Fig. 6, the first bit-line voltage VBL1.First bit-line voltage VBL1 can To be ground voltage or low-voltage with level similar with ground voltage.

First string selection line voltage VSSL1 is applied to string selection line SSL1a, SSL1b, SSL2a and SSL2b.First string Selection line voltage VSSL1 can be the voltage of conducting string select transistor SST1a, SST1b, SST2a and SST2b.SST1a and SST1b corresponds to the string select transistor for being connected to string selection line SSL1a and SSL1b, and SST2a and SST2b, which correspond to, to be connected to The string select transistor of string selection line SSL2a and SSL2b.First string selection line voltage VSSL1 can be supply voltage or have The high voltage of level similar with supply voltage or higher than supply voltage.

First is applied to non-selected wordline by voltage VPASS1.First can be by voltage VPASS1 and will connect The voltage be connected to the memory cell of non-selected wordline.First by voltage VPASS1 can be supply voltage or have with The high voltage of similar or higher than the supply voltage level of supply voltage.

First program voltage VPGM1 is applied to the wordline of selection.First program voltage VPGM1 can be to be passed through than first The high voltage of voltage VPASS1 high.

First ground selection line voltage VGSL1 is applied to ground selection line GSLa and GSLb.First ground selects line voltage VGSL1 It can be the voltage of conductively selection transistor GSTa and GSTb.First ground selection line voltage VGSL1 can be supply voltage or High voltage with level similar with supply voltage or higher than supply voltage.

First common source line voltage VCSL1 is applied to common source line CSL.First common source line voltage VCSL1 can be ground voltage Or the low-voltage with level similar with ground voltage.

In the case, the memory cell MC3 for being connected to third wordline WL3 is selected as the programming of the first programming operation Target.First wordline WL1, the second wordline WL2 and the 4th to the 6th wordline are applied to by voltage VPASS1 due to first WL4-WL6, therefore first memory unit MC1, second memory unit MC2 and the 4th to the 6th memory cell MC4- MC6 conducting.Since the first string selection line voltage VSSL1 is applied to string selection line SSL1a, SSL1b, SSL2a and SSL2b, because This string select transistor SST1a, SST1b, SST2a and SST2b conducting.Line voltage VGSL1 is selected to be applied to due to the first Ground selection line GSLa and GSLb, because this place selection transistor GSTa and GSTb are connected.Since the first program voltage VPGM1 is applied To third wordline WL3, therefore memory cell MC3 is connected.

Since the first bit-line voltage VBL1 is provided to bit line BL1 and BL2, low-voltage passes through string select transistor SST1a, SST1b, SST2a and SST2b and the 4th to the 6th memory cell MC4-MC6 are provided to third memory cell The drain electrode of MC3.In addition, the first common source line voltage VCSL1 supplied to common source line CSL passes through ground selection transistor GSTa and GSTb And first memory unit MC1 and second memory unit MC2 is supplied to the source electrode of third memory cell MC3.

As referring to described in Fig. 5, low-voltage is provided to the third memory for the target for being selected as the first programming operation The channel of unit MC3, high voltage are provided to the control grid of third memory cell MC3.Therefore, third memory cell The threshold voltage of MC3 increases.

Fig. 7 is to show to be supplied to memory block BLKa in the first programming operation according to the exemplary embodiment of inventive concept Voltage table.The example of voltage when local selection transistor GSTa is selected as programming target is shown in Fig. 7.

Bit line BL1 and BL2 are applied to referring to Fig. 2 and Fig. 7, the second bit-line voltage VBL2.Second bit-line voltage VBL2 can To be ground voltage or low-voltage with level similar with ground voltage.

Second string selection line voltage VSSL2 is supplied to string selection line SSL1a, SSL1b, SSL2a and SSL2b.Second string Selection line voltage VSSL2 can be the voltage of conducting string select transistor SST1a, SST1b, SST2a and SST2b.Second string choosing Selecting line voltage VSSL2 can be supply voltage or the high electricity with level similar with supply voltage or higher than supply voltage Pressure.

Second is applied to wordline WL1-WL6 by voltage VPASS2.Second, which can be conducting by voltage VPASS2, connects It is connected to the voltage of the memory cell of wordline WL1-WL6.Second can be supply voltage by voltage VPASS2 or have and confession The high voltage of similar or higher than the supply voltage level of piezoelectric voltage.

Second ground selection line voltage VGSL2 is applied to non-selected ground selection line.Second ground selects line voltage VGSL2 can To be the voltage of conductively selection transistor GST.Second ground selection line voltage VGSL2 can be supply voltage or have and power supply The high voltage of similar or higher than the supply voltage level of voltage.

Second program voltage VPGM2 is applied to the ground selection line selected.Second program voltage VPGM2 can be than The high voltage of two-way overvoltage VPASS2 high.

Second common source line voltage VCSL2 is applied to common source line CSL.Second common source line voltage VCSL2 can be ground voltage Or the low-voltage with level similar with ground voltage.

In the case, the ground selection transistor GSTa for being connected to the ground selection line GSLa is selected as the first programming operation Program target.Since second is applied to the first to the 6th wordline WL1-WL6 by voltage VPASS2, first to the 6th is deposited Storage unit MC1-MC6 conducting.Line voltage VGSL2 is selected to be applied to ground selection line GSLb due to the second, because this place selects Transistor GSTb conducting.Since the second program voltage VPGM2 is applied to ground selection line GSLa, because of this place selection transistor GSTa Conducting.

Since the second bit-line voltage VBL2 is provided to bit line BL1 and BL2, low-voltage passes through string select transistor SST1a, SST1b, SST2a and SST2b and the first to the 6th memory cell MC1-MC6 are provided to ground selection transistor The drain electrode of GSTb, and it is provided to by ground selection transistor GSTb the drain electrode of ground selection transistor GSTa.In addition, supplied to altogether The second common source line voltage VCSL2 of source line CSL is supplied directly into the source electrode of ground selection transistor GSTa.

As referring to described in Fig. 5, low-voltage is provided to the ground selection crystal for the target for being selected as the first programming operation The channel of pipe GSTa, high voltage are provided to the control grid of ground selection transistor GSTa.Therefore, in ground selection transistor GSTa In there is F-N tunnelling, the threshold voltage of ground selection transistor GSTa increases.

Ground selection transistor GSTb is programmed in a similar manner.For example, the low-voltage supplied to bit line BL1 and BL2 is logical Cross the drain side of ground selection transistor GSTb cell transistor (in other words, string select transistor SST1a, SST1b, SST2a and SST2b and memory cell MC1-MC6) it is transmitted to the drain electrode of ground selection transistor GSTb.Supplied to the low electricity of common source line CSL Pressure is supplied to ground choosing by the cell transistor (in other words, ground selection transistor GSTa) of the source side of ground selection transistor GSTb Select the source electrode of transistor GSTb.If high voltage is provided to the control grid of ground selection transistor GSTb, select crystal The threshold voltage of pipe GSTb increases.

Fig. 8 is the flow chart for showing the second programming operation of the exemplary embodiment according to inventive concept.Referring to figs. 1 to figure 3 and Fig. 8 executes verification operation using verifying voltage VFYu in step s310.For example, first can be performed to it The cell transistor of programming operation executes verification operation.It can be according to the cell transistor for performing the first programming operation to it Physical Page executes verification operation.If executing verification operation, in the cell transistor for performing the first programming operation to it, First unit transistor with the threshold voltage lower than verifying voltage VFYu and with the threshold value electricity higher than verifying voltage VFYu The second unit transistor of pressure can be distinguished from each other.

In step s 320, it is determined whether have been verified by operation.For example, there is no have than verifying voltage VFYu The second unit transistor of high threshold voltage or the quantity of second unit transistor can be determined less than in the case where predetermined value Have been verified by operation.

If the second programming operation can be completed by verification operation.If executing step not over verification operation Rapid S330.

In step S330, forbid the volume of the first unit transistor with the threshold voltage lower than verifying voltage VFYu Journey.In step S340, allow to program the second transistor with the threshold voltage higher than verifying voltage VFYu.For example, can To forbid or allow by discriminatively controlling to be supplied to the voltage of the first transistor and be supplied to the voltage of second transistor Programming.After that, in step S350, program voltage is supplied to the control of first unit transistor and second unit transistor Grid processed.For example, program voltage can be the voltage for causing hot hole to inject in second unit transistor.

Step S310 and S320 can form verification step.Step S330 to S350 can form programming step.It can weigh Verification step and programming step are executed again until the result of the verification operation of step S310 is determined as having passed through.In other words, may be used To repeat verification step and programming step until the threshold voltage of cell transistor is equal to or less than verifying voltage VFYu.

When repeating verification step and programming step, thus it is possible to vary be applied to the unit string of memory block BLKa The level of the voltage of CS11, CS12, CS21 and CS22.

Fig. 9 is to show the electricity for being supplied to memory block in the second programming operation according to the exemplary embodiment of inventive concept The table of pressure.The example when executing the second programming to memory cell MC is shown in Fig. 9.

The bit line of selection is applied to referring to Fig. 2 and Fig. 9, third bit-line voltage VBL3.Third bit-line voltage VBL3 can be with It is supply voltage or the high voltage with level similar to supply voltage or higher than supply voltage.4th bit-line voltage VBL4 quilt It is applied to non-selected bit line.4th bit-line voltage VBL4 can be ground voltage or the low electricity with level similar with ground voltage Pressure.

Third string selection line voltage VSSL3 is applied to the string selection line of selection.Third string selects line voltage VSSL3 can be with It is the voltage that string select transistor is connected.Third string selection line voltage VSSL3 can be supply voltage or have and supply voltage The high voltage of similar or higher than supply voltage level.Third string selection line voltage VSSL3 can have and third bit-line voltage VBL3 essentially identical level.4th string selection line voltage VSSL4 is applied to non-selected string selection line.4th string selection line Voltage VSSL4 can be supply voltage or the high voltage than third string selection line voltage VSSL3 high.4th string selection line voltage VSSL4 can be high voltage.These high voltages can prevent boosting (boosting).

Third program voltage VPGM3 is applied to the wordline of selection.Third program voltage VPGM3 can have in memory The level for causing hot hole to inject in unit, the memory cell is in the memory cell for the wordline for being connected to selection Allow the memory cell programmed to it.Third program voltage VPGM3 can have the electricity lower than third common source line voltage VCSL3 It is flat.Third program voltage VPGM3 can have the level for being enough to make third memory cell MC3 to end.

Third is applied to non-selected wordline by voltage VPASS3.Third can be by voltage VPASS3 to be made to store The voltage of device unit conducting.Third can be supply voltage by voltage VPASS3 or select line voltage VSSL3 to than third string High high voltage.

Line voltage VGSL3 is selected to third to be applied to ground selection line GSLa and GSLb.Select to third line voltage VGSL3 It can be the voltage for making ground selection transistor GSTa and GSTb conducting.Line voltage VGSL3 is selected to third to can be supply voltage Or the high voltage with level similar with supply voltage or higher than supply voltage.

Third common source line voltage VCSL3 is applied to common source line CSL.Third common source line voltage VCSL3 can be ground voltage Or the low-voltage with level similar with ground voltage.

As referring to described in Fig. 6, the first programming operation is executed to the memory cell MC3 for being connected to third wordline WL3.This Outside, in third memory cell MC3, belong to the threshold voltage of the third memory cell MC3 of unit string CS11 than verifying electricity VFYu high is pressed, belongs to the threshold voltage of the third memory cell MC3 of remaining unit string CS12, CS21 and CS22 than verifying electricity Press VFYu low.In other words, string selection line SSL1a and SSL1b corresponding with unit string CS11 and bit line BL1 has been selected, it is unselected Select string selection line SSL2a and SSL2b and bit line BL2 not corresponding with unit string CS11.

Figure 10 shows the unit string for being applied to selection in the second programming operation according to the exemplary embodiment of inventive concept The voltage of CS11.In Figure 10, unit string CS11 is shown on right side, the ditch of the cell transistor of unit string CS11 is shown in left side The curve graph of the voltage (or potential) in road.In voltage (or potential) curve graph, horizontal axis indicates that channel voltage Vch, the longitudinal axis are indicated The positioning (position) of cell transistor.

Referring to Fig. 2, Fig. 9 and Figure 10, third program voltage VPGM3 is applied to the third wordline WL3 of selection.Therefore, Three memory cell MC3 cut-off.For example, the channel of third memory cell MC3 has the first type (for example, p-type).Due to third Coupling between the control grid and channel of memory cell MC3, the voltage (or potential) of the channel of third memory cell MC3 It can reduce.

Third string selection line voltage VSSL3 is applied to string the selection line SSL1a and SSL1b of selection.Applying third string Under the original state for selecting line voltage VSSL3, string the selection line SSL1a and SSL1b of selection can be connected.

Third bit-line voltage VBL3 is supplied to the first bit line BL1 of selection.Third bit-line voltage VBL3 can be by leading Drain electrode of the channel pass of the logical string select transistor SST1a and SST1b that are selected to memory cell MC6.

If third is applied to the 4th to the 6th wordline WL4-WL6, the 4th to the 6th storage by voltage VPASS3 Device unit MC4-MC6 conducting.For example, the channel of the 4th to the 6th memory cell MC4-MC6 has second type (for example, N-shaped). Since third memory cell MC3 ends, the drain electrode of the 6th memory cell MC6 is transmitted to from the bit line BL1 of selection Voltage is transferred to the channel of the 4th to the 6th memory cell MC4-MC6.

After the 4th to the 6th memory cell MC4-MC6 conducting, with the 4th to the 6th memory cell MC4-MC6 The voltage of control grid be increased to third and pass through the target level of voltage VPASS3, the 4th to the 6th memory cell MC4- It is coupled between the control grid and channel of MC6.Due to the coupling, the channel of the 4th to the 6th memory cell MC4-MC6 Voltage (or potential) can than from the first bit line BL1 of selection supplied to the 6th memory cell MC6 drain electrode voltage it is high. At this point, string select transistor SST1a and SST1b end.In other words, the channel of the 4th to the 6th memory cell MC4-MC6 with First bit line BL1 is isolated and between the memory cell MC3 of cut-off and the string select transistor SST1a and SST1b of cut-off It is floating.

For example, third string selection line voltage VSSL3 and third bit-line voltage VBL3 can have essentially identical level.This When, the voltage for being transferred to the drain electrode of memory cell MC6, which can have from third string, selects line voltage VSSL3 or third bit line electricity The level pressed VBL3 to subtract the threshold voltage of string select transistor SST1a and SST1b and obtained.In the case, if the 6th The drain voltage of memory cell MC6 increases, then the turn-on condition of string select transistor SST1a and SST1b is unsatisfactory for, to go here and there Selection transistor SST1a and SST1b cut-off.

After string select transistor SST1a and SST1b cut-off, the channel of the 4th to the 6th memory cell MC4-MC6 Voltage is further increased due to coupling effect.In other words, the channel of the 4th to the 6th memory cell MC4-MC6 is floated, floats The voltage (or potential) for the channel set is elevated.For example, the voltage of the channel of the 4th to the 6th memory cell MC4-MC6 can be with Rise to boost voltage VBOOST.In other words, boost voltage VBOOST is provided to the leakage of the third memory cell MC3 of selection Pole.

Since third is provided to the first wordline WL1 and the second wordline WL2 by voltage VPASS3, third ground selection line electricity Pressure VGSL3 is provided to ground selection line GSLa and GSLb, because of this place selection transistor GSTa and GSTb and first memory list First MC1 and second memory unit MC2 conducting.Therefore, it is selected with passing through supplied to the third common source line voltage VCSL of common source line CSL It selects transistor GSTa and GSTb and first memory unit MC1 and second memory unit MC2 is transferred to the third of selection The source electrode of memory cell MC3.

Due to being supplied to the boost voltage VBOOST of the drain electrode of third memory cell MC3 and being supplied to third memory list Voltage difference between the third common source line voltage VCSL3 of the source electrode of first MC3, around third memory cell MC3/middle appearance heat Hole.In embodiment, third program voltage VPGM3 can have the electricity for causing hot hole in third memory cell MC3 It is flat.For example, third program voltage VPGM3 can have the electricity lower with third common source line voltage VCSL3 than boost voltage VBOOST It is flat.Third program voltage VPGM3 can be negative voltage.Since third program voltage VPGM3 is applied to third memory cell The control grid of MC3, therefore hot hole is injected into third memory cell MC3.In other words, third memory cell MC3 Threshold voltage reduce.

When repeating the verification step and programming step of Fig. 8, the level of third program voltage VPGM3 can be mentioned gradually High or reduction.When repeating the verification step and programming step of Fig. 8, third is gradually increased by the level of voltage VPASS3 Or reduce, so that the level of boost voltage VBOOST can be gradually increased or reduce.

Figure 11 to Figure 13 show be applied in the second programming operation according to the exemplary embodiment of inventive concept it is non-selected Unit string CS12, CS21 and CS22 voltage.In Figure 11 into Figure 13, unit string CS12, CS21 and CS22 are shown on right side, Voltage (or potential) curve graph of the channel of the cell transistor of unit string CS12, CS21 and CS22 is shown in left side.Each In voltage (or potential) curve graph, horizontal axis indicates that the voltage Vch of channel, the longitudinal axis indicate the positioning (position) of cell transistor.

Referring to Fig. 2, Fig. 9 and Figure 11, in non-selected unit string CS12, third program voltage VPGM3 is applied to choosing The third wordline WL3 selected.Therefore, third memory cell MC3 ends.

Third string selection line voltage VSSL3 is applied to string the selection line SSL1a and SSL1b of selection.Therefore, string selection is brilliant Body pipe SST1a and SST1b conducting.Third is provided to the 4th to the 6th wordline WL4-WL6 by voltage VPASS3.Therefore, Four to the 6th memory cell MC4-MC6 conducting.

4th bit-line voltage VBL4 is provided to the second non-selected bit line BL2.4th bit-line voltage VBL4 passes through string choosing Select the channel that transistor SSTa and SSTb are provided to the 4th to the 6th memory cell MC4-MC6.Due to the 4th bit-line voltage VBL4 is low-voltage, so if coupled in the control grid of the 4th to the 6th memory cell MC4-MC6, then the 4th to The voltage of the channel of 6th memory cell MC4-MC6, which does not rise to, ends string select transistor SSTa and SSTb.Therefore, no The boosting of 0 description referring to Fig.1 occurs, and the voltage of the channel of the 4th to the 6th memory cell MC4-MC6 becomes the 4th Line voltage VBL4.

Since third is selected with being provided to the first wordline WL1 and the second wordline WL2 and third by voltage VPASS3 Line voltage VGSL3 is applied to ground selection line GSLa and GSLb, because this place selection transistor GSTa and GSTb and first is stored Device unit MC1 and second memory unit MC2 conducting.Therefore, logical supplied to the third common source line voltage VCSL3 of common source line CSL It crosses ground selection transistor GSTa and GSTb and first memory unit MC1 and second memory unit MC2 and is transferred to selection Third memory cell MC3 source electrode.

Supplied to the drain electrode of third memory cell MC3 the 4th bit-line voltage VBL4 and be supplied to third memory cell Voltage difference between the third common source line voltage VCSL3 of the source electrode of MC3 does not cause hot hole.In other words, in non-selected unit It goes here and there in CS12, forbids the volume of third memory cell MC3 and preventing the boosting of drain voltage of third memory cell MC3 Journey.

Referring to Fig. 2, Fig. 9 and Figure 12, in non-selected unit string CS21, third program voltage VPGM3 is applied to The third wordline WL3 of selection.Therefore, third memory cell MC3 ends.

4th string selection line voltage VSSL4 is applied to non-selected string selection line SSL2a and SSL2b.Therefore, string selection Transistor SSTa and SSTb conducting.Third is provided to the 4th to the 6th wordline WL4-WL6 by voltage VPASS3.Therefore, Four to the 6th memory cell MC4-MC6 conducting.

Third bit-line voltage VBL3 is provided to the first bit line BL1 of selection.Third bit-line voltage VBL3 passes through string selection Transistor SSTa and SSTb are provided to the channel of the 4th to the 6th memory cell MC4-MC6.4th string selection line voltage VSSL4 is than the high voltage of third string selection line voltage VSSL3 high.For example, the 4th string selection line voltage VSSL4 can be set For it is sufficiently high make when the 4th to the 6th memory cell MC4-MC6 channel voltage due to from control grid coupling and When raising, string select transistor SSTa and SSTb do not end.Therefore, do not occur referring to Fig.1 0 description boosting, the 4th to the 6th The voltage of the channel of memory cell MC4-MC6 becomes third bit-line voltage VBL3.

Since third is provided to the first wordline WL1 and the second wordline WL2 by voltage VPASS3, third ground selection line electricity Pressure VGSL3 is applied to ground selection line GSLa and GSLb, because of this place selection transistor GSTa and GSTb and first memory list First MC1 and second memory unit MC2 conducting.Therefore, pass through ground supplied to the third common source line voltage VCSL3 of common source line CSL Selection transistor GSTa and GSTb and first memory unit MC1 and second memory unit MC2 is transferred to the of selection The source electrode of three memory cell MC3.

Supplied to the drain electrode of third memory cell MC3 third bit-line voltage VBL3 and be supplied to third memory cell Voltage difference between the third common source line voltage VCSL3 of the source electrode of MC3 is not enough to cause hot hole.In other words, non-selected In unit string CS21, forbid third memory cell MC3 and preventing the boosting of drain voltage of third memory cell MC3 Programming.

Referring to Fig. 2, Fig. 9 and Figure 13, in non-selected unit string CS22, third program voltage VPGM3 is applied to choosing The third wordline WL3 selected.Therefore, third memory cell MC3 ends.

4th string selection line voltage VSSL4 is applied to non-selected string selection line SSL2a and SSL2b.Therefore, string selection Transistor SSTa and SSTb conducting.Third is provided to the 4th to the 6th wordline WL4-WL6 by voltage VPASS3.Therefore, Four to the 6th memory cell MC4-MC6 conducting.

4th bit-line voltage VBL4 is provided to the second non-selected bit line BL2.4th bit-line voltage VBL4 passes through string choosing Select the channel that transistor SSTa and SSTb are provided to the 4th to the 6th memory cell MC4-MC6.4th string selection line voltage VSSL4 is than the high voltage of third string selection line voltage VSSL3 high, and the 4th bit-line voltage VBL4 is than third bit-line voltage VBL3 Low low-voltage.Therefore, when the voltage of the channel of the 4th to the 6th memory cell MC4-MC6 is due to the control gate from them The coupling of pole and when improving, string select transistor SSTa and SSTb do not end.Therefore, the boosting of 0 description referring to Fig.1 does not occur, The voltage of the channel of 4th to the 6th memory cell MC4-MC6 becomes the 4th bit-line voltage VBL4.

Since third is provided to the first wordline WL1 and the second wordline WL2 by voltage VPASS3, third ground selection line electricity Pressure VGSL3 is applied to ground selection line GSLa and GSLb, because of this place selection transistor GSTa and GSTb and first memory list First MC1 and second memory unit MC2 conducting.Therefore, pass through ground supplied to the third common source line voltage VCSL3 of common source line CSL Selection transistor GSTa and GSTb and first memory unit MC1 and second memory unit MC2 is transferred to the of selection The source electrode of three memory cell MC3.

Supplied to the drain electrode of third memory cell MC3 the 4th bit-line voltage VBL4 and be supplied to third memory cell Voltage difference between the third common source line voltage VCSL3 of the source electrode of MC3 does not cause hot hole.In other words, in non-selected unit It goes here and there in CS22, forbids the volume of third memory cell MC3 and preventing the boosting of drain voltage of third memory cell MC3 Journey.

Figure 14 is to show to be supplied to memory block in the second programming operation according to the exemplary embodiment of inventive concept The table of voltage.Figure 14 shows the example of the voltage when executing the second programming in ground selection transistor GSTa and GSTb.

The bit line of selection is applied to referring to Fig. 2 and Figure 14, the 5th bit-line voltage VBL5.5th bit-line voltage VBL5 can be with It is supply voltage or the high voltage with level similar with supply voltage or higher than supply voltage.6th bit-line voltage VBL6 It is applied to non-selected bit line.6th bit-line voltage VBL6 can be ground voltage or with the low of level similar with ground voltage Voltage.

5th string selection line voltage VSSL5 is applied to the string selection line of selection.5th string selection line voltage VSSL5 can be with It is the voltage that string select transistor is connected.5th string selection line voltage VSSL5 can be supply voltage or have and power supply electricity Press the high voltage of similar or higher than supply voltage level.5th string selection line voltage VSSL5 can have and the 5th bit line electricity The level for pressing VBL5 essentially identical.6th string selection line voltage VSSL6 is applied to non-selected string selection line.6th string selection Line voltage VSSL6 can be the voltage that string select transistor is connected.6th string selection line voltage VSSL6 can be supply voltage Or the high voltage with the level than the 5th string selection line voltage VSSL5 high.6th string selection line voltage VSSL6 can be and prevent The high voltage of boosting.

Four-way overvoltage VPASS4 is applied to wordline WL1-WL6.Four-way overvoltage VPASS4, which can be, makes first The voltage be connected to the 6th memory cell MC1-MC6.Four-way overvoltage VPASS4 can be supply voltage or to than the 5 The high voltage of string selection line voltage VSSL5 high.

4th program voltage VPGM4 is applied to the ground selection line of selection.4th program voltage VPGM4 can have on ground The level for causing hot hole to inject in selection transistor, described ground selection transistor are attached to the ground choosing of the ground selection line of selection Select the ground selection transistor for allowing to program it in transistor GSTa.4th program voltage VPGM4 can have more total than third Source line voltage VCSL3 low level.4th program voltage VPGM4 can have the electricity for being enough to make ground selection transistor GSTa cut-off It is flat.

4th ground selection line voltage VGSL4 is applied to non-selected ground selection line.4th ground selects line voltage VGSL4 can To be the voltage for making ground selection transistor conducting.4th ground selection line voltage VGSL4 can be supply voltage or have and power supply The high voltage of similar or higher than the supply voltage level of voltage.

Common source line voltage VCSL4 is applied to common source line CSL.Common source line voltage VCSL4 can be ground voltage or have with The low-voltage of the similar level of ground voltage.

As referring to described in Fig. 7, the first programming is executed in the ground selection transistor GSTa for being connected to ground selection line GSLa Operation.In addition, the threshold voltage ratio for belonging to the ground selection transistor GSTa of unit string CS11 is tested in ground selection transistor GSTa Voltage VFYu high is demonstrate,proved, the threshold voltage ratio for belonging to the ground selection transistor GSTa of remaining unit string CS12, CS21 and CS22 is tested It is low to demonstrate,prove voltage VFYu.In other words, string selection line SSL1a and SSL1b and bit line BL1 corresponding with unit string CS11 has been selected, Non-selected string selection line SSL2a and SSL2b and bit line BL2 not corresponding with unit string CS11.

Figure 15 shows the unit string for being applied to selection in the second programming operation according to the exemplary embodiment of inventive concept Voltage.In Figure 15, unit string CS11 is shown on right side, the channel of the cell transistor of unit string CS11 is shown in left side Voltage (or potential) curve graph.In voltage (or potential) curve graph, horizontal axis indicates that the voltage Vch of channel, the longitudinal axis indicate unit The positioning (position) of transistor.

Referring to Fig. 2, Figure 14 and Figure 15, the 4th program voltage VPGM4 as negative voltage is applied to the ground selection of selection Line GSLa.Therefore, selection transistor GSTa in ground ends.For example, the channel of ground selection transistor GSTa has the first type (for example, p Type).Due to the coupling between the control grid and channel of ground selection transistor GSTa, the electricity of the channel of ground selection transistor GSTa Pressure can reduce.

5th string selection line voltage VSSL5 is applied to string the selection line SSL1a and SSL1b of selection.Applying the 5th string Under the original state for selecting line voltage VSSL5, string select transistor SST1a and SST1b can be connected.

5th bit-line voltage VBL5 is provided to the first bit line BL1 of selection.5th bit-line voltage VBL5 can be by leading The channel pass of logical string select transistor SSTa and SSTb are to memory cell MC6.

If four-way overvoltage VPASS4 is applied to the first to the 6th wordline WL1-WL6, the first to the 6th storage Device unit MC1-MC6 conducting.For example, the channel of the first to the 6th memory cell MC1-MC6 has second type (for example, N-shaped). If the 4th ground selection line voltage VGSL4 be applied to ground selection line GSLb, selection transistor GSTb conducting.For example, ground The channel of selection transistor GSTb has second type.Since ground selection transistor GSTa ends, passed from the bit line BL1 of selection The voltage for transporting to the drain electrode of the 6th memory cell MC6 is transferred to the first to the 6th memory cell MC1-MC6 and ground choosing Select the channel of transistor GSTb.

After first to the 6th memory cell MC1-MC6 and ground selection transistor GSTb conducting, due to first to the 6th The voltage of the control grid of memory cell MC1-MC6 is increased to the target level and ground selection line of four-way overvoltage VPASS4 The voltage of the control grid of GSLb is increased to the target level of the 4th ground selection line voltage VGSL4, therefore the first to the 6th storage It is coupled between device unit MC1-MC6 and the control grid and channel of ground selection transistor GSTb.Due to the coupling, first Voltage to the channel of the 6th memory cell MC1-MC6 and ground selection transistor GSTb can be than supplying from the first bit line VBL1 Voltage to the drain electrode of the 6th memory cell MC6 is high.At this point, string select transistor SST1a and SST1b end.In other words, The channel of one to the 6th memory cell MC1-MC6 and ground selection transistor GSTb is isolated with the first bit line BL1, and is being ended Ground selection transistor GSTa and string select transistor SST1a and SST1b between it is floating.

5th string selection line voltage VSSL5 and the 5th bit-line voltage VBL5 can have essentially identical level.It is transferred to The voltage of the drain electrode of memory cell MC6 can have by selecting line voltage VSSL5 or the 5th bit-line voltage from the 5th string VBL5 subtracts the level that the threshold voltage of string select transistor SST1a and SST1b obtain.In the case, if memory list The drain voltage of first MC6 is improved due to coupling, then is unsatisfactory for the turn-on condition of string select transistor SST1a and SST1b, thus String select transistor SST1a and SST1b cut-off.

After string select transistor SST1a and SST1b cut-off, the first to the 6th memory cell MC1-MC6 and ground selection The voltage of the channel of transistor GSTb is further increased due to coupling effect.In other words, the first to the 6th memory cell MC1- The channel of MC6 and ground selection transistor GSTb are floated, and the voltage of floating channel is elevated.For example, the first to the 6th storage The voltage of the channel of device unit MC1-MC6 and ground selection transistor GSTb can increase as boost voltage VBOOST.In other words, it rises Piezoelectricity pressure VBOOST is provided to the drain electrode of the ground selection transistor GSTa of selection.

The ground selection transistor GSTa of selection is transferred to supplied to the 4th common source line voltage VCSL4 of common source line CSL Source electrode.

Due to being supplied to the boost voltage VBOOST of the drain electrode of ground selection transistor GSTa and being supplied to ground selection transistor Voltage difference between 4th common source line voltage VCSL4 of the source electrode of GSTa, around ground selection transistor GSTa/middle appearance heat is empty Cave.Since the 4th program voltage VPGM4 is applied to the control grid of ground selection transistor GSTa, hot hole is injected into In ground selection transistor GSTa.In other words, the threshold voltage of ground selection transistor GSTa reduces.

It, can be by preventing as described in referring to Fig.1 1 to Figure 13 in non-selected unit string CS12, CS21 and CS22 The boost in voltage of the drain electrode of ground selection transistor GSTa and forbid ground selection transistor GSTa programming.

Ground selection transistor GSTb is programmed in a similar manner.For example, in the unit string of selection, ground selection transistor The drain voltage of GSTb is boosted.The source electrode of ground selection transistor GSTb is transferred to supplied to the low-voltage of common source line CSL.Such as The 4th program voltage VPGM4 of fruit is provided to ground selection transistor GSTb, then the ground selection transistor GSTb of the unit string selected Threshold voltage reduce.

In non-selected unit string, the voltage of the drain electrode of ground selection transistor GSTb is prevented from boosting.Supplied to common source The low-voltage of line CSL is transferred to the source electrode of ground selection transistor GSTb.When the 4th program voltage VPGM4 is selected with being provided to When line GSLb, the threshold voltage of the ground selection transistor GSTb of non-selected unit string is not reduced.

When repeating the verification step and programming step of Fig. 8, the level of the 4th program voltage VPGM4 can be mentioned gradually High or reduction.When repeating the verification step and programming step of Fig. 8, the level of four-way overvoltage VPASS4 is gradually increased Or reduce, so that the level of boost voltage VBOOST can be gradually increased or reduce.

Figure 16 is the flow chart for showing the second programming operation of the exemplary embodiment according to inventive concept.Referring to figs. 1 to Fig. 3 and Figure 16 executes verification operation using verifying voltage VFYu in step S410.If verification operation is executed, right In its cell transistor for performing the first programming operation, the first unit with the threshold voltage lower than verifying voltage VFYu is brilliant Body pipe and second unit transistor with the threshold voltage higher than verifying voltage VFYu are distinguished from each other.

In the step s 420, it is determined whether have been verified by operation.It, then can be with if it is determined that have been verified by operation Complete the second programming operation.If the result of verification operation is not determined as having passed through, S430 is thened follow the steps.Step S410 and S420 can be verification step.

In step S430, forbid compiling the first unit transistor with the threshold voltage lower than verifying voltage VFYu Journey.In step S440, allow to program the second transistor with the threshold voltage higher than verifying voltage VFYu.At it Afterwards, in step S450, program voltage is supplied to the control grid of first unit transistor and second unit transistor.Example Such as, program voltage can be the voltage for causing hot hole to inject in second unit transistor.

In step S460, it is determined whether execute maximum programming step.For example, it may be determined whether will include step S430 Programming step to S450 executes pre-determined number.

As described in referring to Fig.1 0 to Figure 15, in the second programming operation, the selection of the unit string by promoting selection The drain voltage of cell transistor reduces the threshold voltage of the cell transistor of the selection of the unit string of selection.Boost voltage meeting Due to such as leakage current peripheral effect (peripheral effect) and gradually decrease.If boost voltage gradually decreases, The programming efficiency of the cell transistor of selection can reduce.In order to prevent programming efficiency due to boost voltage reduction and reduce, can It is executed for several times with the programming step that will include step S430 to S450.

For example, the unit string of selection can be restored after executing kth time programming step.For example, can be to memory block The channel voltage of the cell transistor of the unit string of BLKa is discharged.Later, after verification step, apply again referring to Fig. 9 or figure The voltage of 14 descriptions, so as to execute+1 programming step of kth.

When repeating programming step, it can control voltage conditions.Selection is applied to for example, can be improved or reduce The level of the program voltage of the control grid of cell transistor.It is applied to the level by voltage VPASS of non-selected wordline It increases or decreases, so that the level of boost voltage VBOOST can be improved or reduce.It is applied to the electricity of the low-voltage of common source line CSL It is flat to can be improved or reduce.

Figure 17 is to show the level for passing through voltage in the second programming operation according to the exemplary embodiment of inventive concept The timing diagram of control.In Figure 17, horizontal axis indicates that time T, the longitudinal axis indicate to pass through the level of voltage VPASS.Figure is shown in Figure 17 The example that control passes through the level of voltage VPASS in 16 programming step.

Referring to Fig.1 7, wordline WL is applied in the first moment T1 by voltage VPASS.After that, at the second moment T2, third moment T3, the 4th moment T4 and the 5th moment T5 are improved by the level of voltage VPASS.After that, the 6th Moment T6 is discharged by voltage VPASS.

As described in referring to Fig.1 6, the level of boost voltage VBOOST can pass at any time and gradually decrease.Such as Figure 17 institute Show, if be gradually increased by the level of voltage VPASS, due to coupling, the level of boost voltage VBOOST is gradually risen.It changes The reduction and raising of Yan Zhi, boost voltage VBOOST offset each other, so that the level of boost voltage VBOOST is compiled in execution second It is maintained when the programming step of journey operation.

It, can be as referring to figure although repeating the programming step of the second programming operation as described in referring to Fig.1 6 17 description ground control the level by voltage VPASS in each programming step.

Figure 18 is the process for showing the operating method of nonvolatile memory of the exemplary embodiment according to inventive concept Figure.Referring to Fig.1, Fig. 2 and Figure 18 executes the first programming operation in step S510 to improve the threshold voltage of cell transistor. For example, being selected as the threshold voltage of the cell transistor of program object can be improved.

In step S520, the second programming operation is executed to reduce in cell transistor with higher than verifying voltage VFYu The threshold voltage of the cell transistor of threshold voltage.The first volume is performed to it for example, can reduce by the second programming operation The threshold voltage of the cell transistor with the threshold voltage higher than verifying voltage VFYu in the cell transistor of journey operation.Example Such as, verifying voltage VFYu can be the upper limit of the target threshold voltage range of cell transistor.

In step S530, the maximum times for having reached iteration are determined.For example, it is determined whether having been carried out predetermined time Several the first programming operations and the second programming operation.If being also not carried out the first programming operation and the second programming behaviour of pre-determined number Make, then repeatedly therefore step S510 and S520 executes the first programming operation and the second programming operation again.If executed The first programming operation and the second programming operation of pre-determined number, then complete the programming of cell transistor.

If repeat by the first programming operation improve cell transistor threshold voltage operation and by the Two programming operations reduce the operation with the threshold voltage of cell transistor of the threshold voltage higher than verifying voltage VFYu, then may be used To reduce the threshold voltage distribution of cell transistor.

When repeating the first programming operation, thus it is possible to vary be applied to the electricity of unit string CS11, CS12, CS21 and CS22 Pressure.For example, the level of program voltage VPGM can be gradually increased.

When the second programming operation starts, the voltage that can be applied to unit string CS11, CS12, CS21 and CS22 is initial Turn to initial value.

Figure 19 is the stream for showing the operating method of the nonvolatile memory 110 according to the exemplary embodiment of inventive concept Cheng Tu.Referring to Fig.1, Fig. 2 and Figure 19 executes the first programming operation in step S610 to improve the threshold value electricity of cell transistor Pressure.For example, the whole threshold voltages for being selected as programming the cell transistor of target can be improved.

In step S620, the second programming operation is executed to reduce in cell transistor with higher than verifying voltage VFYu The threshold voltage of the cell transistor of threshold voltage.The first volume is performed to it for example, can reduce by the second programming operation The threshold voltage of the cell transistor with the threshold voltage higher than verifying voltage VFYu in the cell transistor of journey operation.Example Such as, verifying voltage VFYu can be the upper limit of the target threshold voltage range of cell transistor.

In step S630, verification operation is executed to cell transistor using verifying voltage VFYl.For example, if in unit There is the cell transistor with the threshold voltage lower than verifying voltage VFYl in transistor or has lower than verifying voltage VFYl Threshold voltage cell transistor quantity be greater than predetermined value, then can determine verification operation be failed.If in list There is no the cell transistor with the threshold voltage lower than verifying voltage VFYl or with than verifying voltage in first transistor The quantity of the cell transistor of VFYl low threshold voltage is not more than predetermined value, then can determine that the result of verification operation has been led to It crosses.

In step S640, if verification operation is determined as having passed through, the programming of cell transistor is completed.If tested Card operation is determined as having failed, then executes step S610 to S630 again.

It, can be with the volume of determination unit transistor if the number for repeating step S610 to S630 reaches predetermined threshold Journey is completed and mistake occurs.

When repeating the first programming operation, thus it is possible to vary be applied to the electricity of unit string CS11, CS12, CS21 and CS22 Pressure.For example, the level of program voltage VPGM can be gradually increased.

When the second programming operation starts, the voltage that can be applied to unit string CS11, CS12, CS21 and CS22 is initial Turn to initial value.

Figure 20 shows the threshold value of cell transistor in the operating method of Figure 19 of the exemplary embodiment according to inventive concept The change of voltage.In Figure 20, horizontal axis indicates that the threshold voltage vt h of cell transistor, the longitudinal axis indicate the quantity of cell transistor. In other words, Figure 20 shows the threshold voltage distribution of cell transistor.

Referring to Fig.1, the initial threshold voltage distribution of Fig. 2, Figure 19 and Figure 20, cell transistor can be by First Line L1 tables Show.

If executing the first programming operation of step S610, the threshold voltage of cell transistor is improved.For example, unit is brilliant The threshold voltage distribution of body pipe can change from First Line L1 to the second line L2.

If executing the second programming operation of step S620, reducing has the threshold voltage higher than verifying voltage VFYu The threshold voltage of cell transistor.For example, the threshold voltage higher than verifying voltage VFYu can become lower than verifying voltage VFYu. The first programming operation and the second programming operation are executed until the threshold voltage of cell transistor is equal to or higher than verifying voltage VFY1. In other words, the threshold voltage distribution of cell transistor can change from the second line L2 to third line L3.

As described above, if executing the first programming operation and the second programming operation, the threshold voltage point of cell transistor Cloth constriction, specifically, the threshold voltage of cell transistor are limited to the range between verifying voltage VFYu and verifying voltage VFY1.By It is controlled in target zone in the threshold voltage of cell transistor, therefore the nonvolatile memory 110 including cell transistor Reliability improve.

Figure 21 is the block diagram for showing the storage device of the exemplary embodiment according to inventive concept.Referring to Figure 21, storage dress Setting 100 includes nonvolatile memory 110, Memory Controller 120 and random access memory (RAM) 130.

Nonvolatile memory 110 can execute under the control of Memory Controller 120 and write, read and erase behaviour Make.Nonvolatile memory 110 can exchange the first data DATA1 with Memory Controller 120.For example, non-volatile memories Device 110 can receive the first data DATA1 from Memory Controller 120 and the first data DATA1 is written.Nonvolatile memory 110 are able to carry out read operation and export the first data DATA1 of reading to Memory Controller 120.

Nonvolatile memory 110 can receive the first order CMD1 and the first address from Memory Controller 120 ADDR1.Nonvolatile memory 110 can exchange control signal CTRL with Memory Controller 120.For example, non-volatile deposit Reservoir 110 can receive at least one of following signals: selection constitutes multiple semiconductor chips of nonvolatile memory 110 In at least one semiconductor chip chip select signal/CE, indicate from 120 received signal of Memory Controller be first It orders the order of CMD1 to latch enable signal CLE, indicate that from 120 received signal of Memory Controller be the first address AD DR1 Address latch enable signal ALE, generated in read operation by Memory Controller 120 and triggered periodically with for adjusting Reading enable signal/RE of whole timing, when transmission first order CMD1 or the first address AD DR1 when by Memory Controller 120 Write-in enable signal/WE of activation, by Memory Controller 120 activate with when power change when prevent it is undesired erasing or not Anti- stop signal/the WP of the write-in of desired write-in and in write operation by Memory Controller 120 generate and trigger periodically With the synchronous data strobe signal DQS of the input for adjusting the first data DATA1 from Memory Controller 120.For example, Nonvolatile memory 110 can export whether instruction nonvolatile memory 110 executes programming, erasing or read operation just Thread & busy signal R/nB and by nonvolatile memory 110 from read it is that enable signal/RE generates and periodically trigger with In synchronous at least one of the data strobe signal DQS of the output for adjusting the first data DATA1 to Memory Controller 120.

First data DATA1, the first address AD DR1 and the first order CMD1 can pass through the first channel CH1 and memory Controller 120 communicates.First channel CH1 can be input/output channel.Control signal CTRL can by second channel with deposit Memory controller 120 communicates.Second channel CH2 can be control channel.

Nonvolatile memory 110 has referring to figs. 1 to Figure 20 structure described and can retouch according to referring to figs. 1 to Figure 20 The method operation stated.For example, nonvolatile memory 110 is able to carry out the first programming of the threshold voltage of lift unit transistor Operation and the threshold value for reducing the cell transistor with the threshold voltage higher than verifying voltage in the cell transistor programmed Second programming operation of voltage.

Nonvolatile memory 110 may include flash memory.However, nonvolatile memory 110 is not limited to include flash memory.It is non- Volatile memory 110 may include such as phase transformation RAM (PRAM), magnetic RAM (MRAM), resistance RAM (RRAM), ferroelectric RAM (FeRAM) at least one of the various nonvolatile memories such as.

Memory Controller 120 is configured to control nonvolatile memory 110.For example, Memory Controller 120 can Control nonvolatile memory 110 is to execute write-in, reading or erasing operation.Memory Controller 120 can with it is non-volatile Memory 110 exchange the first data DATA1 and control signal CTRL and by first order CMD1 and the first address AD DR1 export to Nonvolatile memory 110.

Memory Controller 120 can control nonvolatile memory 110 under the control of external host device.Memory Controller 120 can exchange the second data DATA2 with external host device, and receive the second order CMD2 from external host device With the second address AD DR2.

Memory Controller 120 can be deposited by first unit (for example, time quantum or data cell) with non-volatile Reservoir 110 exchanges the first data DATA1 and by the second unit different from first unit (for example, time quantum or data sheet Member) the second data DATA2 is exchanged with external host device.

Memory Controller 120 can exchange the first data DATA1 simultaneously with nonvolatile memory 110 according to the first format First order CMD1 and the first address AD DR1 is transmitted to nonvolatile memory 110.Memory Controller 120 being capable of basis Second format different from the first format exchanges the second data DATA2 with external host device and receives the from external host device Two order CMD2 and the second address AD DR2.

RAM 130 can be used as buffer storage, cache (cache) memory or behaviour by Memory Controller 120 Make memory.For example, Memory Controller 120 can receive the second data DATA2 from external host device, in RAM 130 It stores received second data DATA2 and the second data DATA2 being stored in RAM130 is written as the first data DATA1 In nonvolatile memory 110.Memory Controller 120 can read the first data DATA1 from nonvolatile memory 110, The first data DATA1 of reading is stored in RAM130 and using the first data DATA1 being stored in RAM 130 as the second number It exports according to DATA2 to external host device.Memory Controller 120 can store in RAM 130 from nonvolatile memory Simultaneously the data being stored in RAM 130 are written again in nonvolatile memory 110 for 110 data read.

Memory Controller 120 can store data or generation for managing non-volatile memory 110 in RAM 130 Code.For example, Memory Controller 120 can be read from nonvolatile memory 110 for managing non-volatile memory 110 Code or data are simultaneously loaded into RAM 130 to drive nonvolatile memory 110.

Memory Controller 120 may include error-correcting code (ECC) block 124.ECC Block 124 can be non-based on being written to The first data DATA1 in volatile memory 110 generates even-odd check.The even-odd check of generation can be with the first data Nonvolatile memory 110 is written in DATA1 jointly.The operation for generating even-odd check can be error correction encoding operation.ECC Block 124 can receive the first data DATA1 and even-odd check from nonvolatile memory 110.ECC Block 124 is able to use received The mistake of the first data of parity-corrected DATA1.The operation of correction mistake can be error correcting/decoding operation.

In error correcting/decoding operation, ECC Block 124 is able to carry out simplified error correction or complete error correction. Simplified error correction can be the error correction of the error correction time with reduction.Complete error correction, which can be, to be had The error correction of higher reliability.ECC Block 124 can be by selectively executing simplified error correction or complete wrong school Service speed and reliability just to improve storage device 100.

RAM 130 may include such as dynamic ram (DRAM), static state RAM (SRAM), synchronous dram (SDRAM), PRAM, At least one of various random access memory of MRAM, RRAM, FeRAM etc..

In order to reduce the expense that erasing operation produces in nonvolatile memory 110, storage device 100 can execute ground Location mapping.For example, storage device 100 can be in idle memory space when external host device requested write operation Write request data were stored in memory cell, rather than wiped the memory cell of storage available data with depositing in erasing Write request data were stored in storage unit.Memory Controller 120 can drive according to the above method and be mapped in external master Flash translation layer (FTL) (the flash of logical address used in machine device and the physical address used in nonvolatile memory 110 Translationlayer, FTL).For example, the second address AD DR2 can be logical address, the first address AD DR1 can be object Manage address.

Storage device 100 can execute write-in, reading or the erasing operation of data according to the request of external host device.It deposits Storage device 100 may include solid state drive (SSD) or hard disk drive (HDD).Storage device 100 may include such as personal Computer memory card international federation (PCMCIA) card, compact flash (CF) card, smart media card (SM, SMC), memory stick, Multimedia card (MMC, minification (RS)-MMC, MMCmicro), secure digital (SD) block (SD, miniSD, microSD, safety Digital high capacity (SDHC)), the storage card of Common Flash Memory device (UFS) etc..Storage device 100 may include such as embedded more The installation memory of media card (eMMC), UFS, perfect page new (perfectpage new, PPN) etc..

Figure 22 is the block diagram for showing the Memory Controller of the exemplary embodiment according to inventive concept.Referring to Figure 22, deposit Memory controller 120 includes bus 121, processor 122, RAM 123, ECC Block 124, host interface 125, buffer control electricity Road 126 and memory interface 127.

Bus 121 is configured to provide channel between the composition element of Memory Controller 120.

Processor 122 can control the integrated operation of Memory Controller 120 and execute logical operation.122 energy of processor Enough communicated by host interface 125 with external host device.Processor 122 can store in RAM 123 passes through host interface 125 received second order CMD2 and the second address AD DR2.Processor 122 can be according to the second life being stored in RAM 123 It enables CMD2 and the second address AD DR2 generate the first order CMD1 and the first address AD DR1, and is exported by memory interface 127 The the first order CMD1 and the first address AD DR1 generated.

Processor 122 can be exported by Buffer control circuit 126 passes through received second data of host interface 125 DATA2 stores the second data DATA2 in RAM 123.Processor 122 can will be stored in RAM by memory interface 127 Data in 123 are exported by the received data of Buffer control circuit 126 as the first data DATA1.122 energy of processor Enough storages in RAM 123 are by the received first data DATA1 of memory interface 127 or pass through Buffer control circuit 126 Export the first data DATA1.Processor 122 can will be stored in the data in RAM 123 by host interface 125 or by slow It rushes the received data of device control circuit 126 to export as the second data DATA2, or RAM will be stored in by memory interface 127 Data in 123 are exported by the received data of Buffer control circuit 126 as the first data DATA1.

RAM 123 may be used as operation memory, cache memory or the buffer storage of processor 122.RAM 123 can store the code executed by processor 122 and order.RAM 123 can store the data handled by processor 122. RAM 123 may include SRAM.

ECC Block 124 is able to carry out error correction operations.ECC Block 124 can be based on that memory interface 127 will be output to The first data DATA1 or generate the mistake for executing error correction from the received second data DATA2 of host interface 125 Correcting code (for example, even-odd check).First data DATA1 and even-odd check can be exported by memory interface 127.ECC Block 124 are able to use through the received first data DATA1 of memory interface 127 and received first data of even-odd check execution The error correction of DATA1.The composition element that ECC Block 124 can be used as memory interface 127 is included in memory interface 127 In.

Host interface 125 is configured to communicate under the control of processor 122 with external host device.Host interface 125 The second order CMD2 and the second address AD DR2 can be received from external host device, and the second number is exchanged with external host device According to DATA2.

Host interface 125 may be structured to using such as universal serial bus (USB), Serial Advanced Technology Attachment (SATA), Serial Attachment small computer system interface (SAS), high-speed chip interconnect (HSIC), small computer system interface (SCSI), firewire, peripheral component interconnection (PCI), quick PCI (PCIe), flash non-volatile memory (NVMe), UFS, SD, At least one of a variety of different communication methods such as MMC, eMMC execute communication.

Buffer control circuit 126 is configured to control RAM 130 under the control of processor 122 (referring to Figure 21).It is slow Rushing device control circuit 126, data can be written in RAM 130 and read data from RAM 130.

Memory interface 127 is configured to communicate (reference with nonvolatile memory 110 under the control of processor 122 Fig. 1).First order CMD1 and the first address AD DR1 can be transmitted to nonvolatile memory 110 simultaneously by memory interface 127 The first data DATA1 and control signal CTRL are exchanged with nonvolatile memory 110.

RAM 130 can be not provided with storage device 100.In other words, storage device 100, which can not have, is located at memory Individual memory outside controller 120 and nonvolatile memory 110.In the case, Buffer control circuit 126 can To be not provided with Memory Controller 120.The function of RAM 130 can be held by the internal RAM 123 of Memory Controller 120 Row.

As an example, processor 122 is able to use code control Memory Controller 120.Processor 122 can be from setting Nonvolatile memory (for example, read-only memory) loading code inside Memory Controller 120.As another example, Processor 122 can be loaded from the received code of memory interface 127.

The bus 121 of Memory Controller 120 is divided into control bus and data/address bus.Data/address bus can be by structure Make to transmit data in Memory Controller 120, control bus may be constructed such that transmitted in Memory Controller 120 it is all Such as control information of order, address.Data/address bus and control bus can be separated from each other and can not interfere or influence. Data/address bus can connect to host interface 125, Buffer control circuit 126, ECC Block 124 and memory interface 127.Control Bus can connect to host interface 125, processor 122, Buffer control circuit 126, RAM 123 and memory interface 127.

Figure 23 is the block diagram for showing the computing device 1000 according to the exemplary embodiment of inventive concept.Referring to Figure 23, meter Calculating device 1000 includes processor 1100, RAM 1200, storage device 1300, modem 1400 and user interface 1500.

Processor 1100 can control the integrated operation of computing device 1000 and execute logical operation.For example, processor 1100 can be built into system-on-chip (SoC).Processor 1100 can be general processor, application specific processor or application Processor.

RAM 1200 can be communicated with processor 1100.RAM 1200 can be processor 1100 or computing device 1000 Main memory.Processor 1100 can in RAM 1200 interim store code or data.Processor 1100 is able to use RAM 1200 execute code and processing data.Processor 1100 be able to use RAM 1200 execute operating system, using etc. it is each Kind software.Processor 1100 is able to use the integrated operation that RAM 1200 controls computing device 1000.RAM 1200 may include The non-volatile memories of the volatile memory of SRAM, DRAM, SDRAM etc. or PRAM, MRAM, RRAM, FeRAM etc. Device.

Storage device 1300 can be communicated with processor 1100.Storage device 1300 can store the number for retaining long-time According to.In other words, processor 1100 can store the data for retaining long-time in storage device 1300.1300 energy of storage device Enough store the boot image for driving computing device 1000.Storage device 1300 can store operating system, using etc. Various softwares source code.Storage device 1300 can store by operating system, using etc. the processing of various softwares number According to.

Processor 1100 can be by the way that the source code being stored in storage device 1300 to be loaded into RAM1200 and then hold The source code that is loaded into RAM 1200 of row come drive operating system, using etc. various softwares.Processor 1100 can The data being stored in storage device 1300 are loaded into RAM1200 and handle the data being loaded into RAM 1200.Processing The data for retaining long-time being stored in the data in RAM1200 can be loaded into storage device 1300 by device 1100.

Storage device 1300 may include the nonvolatile memory of flash memory, PRAM, MRAM, RRAM, FeRAM etc..

Modem 1400 can under the control of processor 1100 with communication with external apparatus.For example, modem 1400 can execute wired or wireless communication with external device (ED).Modem 1400 can based on such as long term evolution (LTE), Global intercommunication microwave accesses (WiMax), global system for mobile communications (GSM), CDMA (CDMA), bluetooth, near-field communication (NFC), at least one of various wireless communications methods of Wireless Fidelity (WiFi), radio frequency identification (RFID) or such as USB, SATA, SCSI, firewire, PCI, PCIe, NVMe, UFS, SD, secure digital input and output (SDIO), universal asynchronous receiver transmitter (UART), Serial Peripheral Interface (SPI) (SPI), high speed SPI (HS-SPI), RS232, internal integrated circuit (I2C), high speed (HS)- The various cable modems of I2C, integrated audio interface chip (I2S), Sony/Philips Digital interface (S/PDIF), MMC, eMMC etc. At least one of letter method executes communication.

User interface 1500 can communicate under the control of processor 1100 with user.For example, user interface 1500 can be with Including such as keyboard, keypad, key, touch panel, touch screen, touch tablet, touch ball, camera, microphone, gyro sensors The user input interface of device, vibrating sensor etc..User interface 1500 may include such as liquid crystal display (LCD), You Jifa Optical diode (OLED) display, Activematric OLED (AMOLED) display, light emitting diode (LED), loudspeaker, motor (motor) user's output interface such as.

Storage device 1300 may include the storage device 100 according to the exemplary embodiment of inventive concept.Processor 1100, RAM 1200, modem 1400 and user interface 1500 are capable of forming the host dress communicated with storage device 1300 It sets.

Figure 24 shows the perspective for showing the structure of the memory block BLKa (referring to Fig. 2) according to the embodiment of inventive concept Figure.Figure 25 is the cross-sectional view for showing the structure of the memory block BLKa according to the embodiment of inventive concept.Reference Figure 24 and Figure 25, Substrate 111 is set.In embodiment, substrate 111 can be the trap with the first conduction type.For example, substrate 111 can be it is logical Cross 3 race's elements that such as boron is injected in substrate 111 and the p-well formed.For example, substrate 111 can be the bag being arranged in N trap Shape p-well.Hereinafter it is assumed that substrate 111 is p-well (or pouch-shaped p-well).However, substrate 111 is not limited to p-type.

Extend in a first direction and multiple common source area CSR separated from one another are arranged in substrate 111 in a second direction On.Multiple common source area CSR can be commonly connected to each other to form common source line.Multiple common source area CSR can have and substrate 111 Different the second conduction type of conduction type.For example, multiple common source area CSR can have N-type.Hereinafter it is assumed that multiple common sources Area CSR has N-type.In the following, multiple common source area CSR are not limited to N-type.

Multiple insulating materials 112 and 112a are between Liang Ge common source area adjacent to each other in multiple common source area CSR along third Direction (that is, direction vertical with substrate 111) is sequentially positioned in substrate 111.Multiple insulating materials 112 and 112a can be It is separated from one another on third direction.Multiple insulating materials 112 and 112a extend in a first direction.In embodiment, multiple exhausted Edge material 112 and 112a may include the insulating materials of such as conductor oxidate.In embodiment, multiple insulating materials 112 Thickness with the insulating materials 112a contacted with substrate 111 in 112a can be smaller than the thickness of other insulating materials 112.

Sequence is arranged and upwardly penetrates through multiple insulating materials 112 and multiple column PL of 112a in third party in a first direction It is arranged between two adjacent common source areas.In embodiment, multiple column PL can pass through insulating materials 112 and 112a and substrate 111 contacts.In embodiment, column can be separated from one another between two adjacent common source areas in a first direction.Column can be with It is arranged to line in a first direction.

Each of multiple column PL include lower prop PLa and upper prop PLb.The width of lower prop PLa can with substrate 111 Distance increases and increases.Lower prop PLa may include multiple material.For example, lower prop PLa may include the second information storage layer 116b, channel layer 114 and the internal material 115 inside channel layer 114.Second information storage layer 116b may include insulation Material, such as silica, silicon nitride.

The top of lower prop PLa can be filled with silicon pad SP.Silicon pad SP can have conduction identical with channel layer 114 Type.Silicon pad SP can have p-type or can be intrinsic silicon.Silicon pad SP can be set to make lower prop PLa and upper prop PLb It is easy connection.

Upper prop PLb can connect on lower prop PLa, specifically, be connected on silicon pad SP.The width of upper prop PLb can be with Increase with increasing at a distance from substrate.Upper prop PLb may include multiple material.For example, upper prop PLb may include the second letter Cease accumulation layer 116b, channel layer 114 and the internal material 115 inside channel layer 114.Second information storage layer 116b can be with Including insulating materials, such as silica, silicon nitride.

Channel layer 114 may include the semiconductor material (for example, silicon) with the first conduction type.Channel layer 114 can be with Including having the semiconductor material (for example, silicon) with 111 same conductivity type of substrate.Channel layer 114 may include not having to lead The intrinsic semiconductor of electric type.Channel layer 114 may include the first channel layer 114a and the second channel layer 114b.

Internal material 115 may include insulating materials.For example, internal material 115 may include the insulation of such as silica Material.For example, internal material 115 may include air gap.First information accumulation layer 116a setting insulating materials 112 and 112a with And on the surface of the exposure of the column PL between two adjacent common source areas.First information accumulation layer 116a may include insulation material Material, such as silica, silicon nitride.Internal material 115 may include the first internal material 115a and the second internal material 115b.

The between two adjacent common source areas and exhausted of first information accumulation layer 116a is arranged in conductive material CM1 to CM10 On the surface of exposure between edge material 112 and 112a.Conductive material CM1 to CM10 can extend in a first direction.It is conductive Material C M1 to CM10 can be separated by the wordline notch WL Cut on common source area CSR.Wordline notch WL Cut can expose common source Area CSR.Wordline notch WL Cut can extend in a first direction.

In embodiment, conductive material CM1 to CM10 may include conductive metal material.Conductive material CM1 to CM10 can To include the non-metallic conducting material of such as polysilicon.In embodiment, it can remove and be arranged in insulating materials 112 and 112a Uppermost insulating materials upper surface on first information accumulation layer 116a.In embodiment, it can remove and be arranged exhausted First information accumulation layer 116a in the side surface of edge material 112 and 112a on the side surface of column PL.

Multiple drain electrodes 320 are arranged on multiple column PL.In embodiment, drain electrode 320 may include having the second conductive-type The semiconductor material (for example, silicon) of type.For example, drain electrode 320 may include the semiconductor material (for example, silicon) with N-type.Under Face, it is assumed that drain electrode 320 includes N-type silicon.However, drain electrode 320 is not limited to include N-type silicon.In embodiment, drain electrode 320 can expand It opens up on the channel layer 114 of column PL.

Extend in a second direction and multiple bit lines BL separated from one another is arranged in drain electrode 320 in a first direction.Position Line BL is connect with drain electrode 320.In embodiment, 320 and bit line BL of drain electrode can be connected to each other by contact plug (not shown).? In embodiment, bit line BL1 to BL2 may include conductive metal material.In embodiment, bit line BL1 may include having to BL2 The non-metallic conducting material of such as polysilicon.

Conductive material CM1 to CM10 can have the first to the tenth height according to from the sequence of substrate 111.Multiple column PL with Multiple unit strings are collectively formed in first information accumulation layer 116a and multiple conductive material CM1 to CM10.Each of multiple column PL A unit string is formed with first information accumulation layer 116a and adjacent conductive material CM1 to CM10.

Column PL is arranged in substrate 111 along line direction and column direction.Tenth conductive material CM10 can form row.It is connected to The column of same tenth conductive material can form a line.Bit line BL can form column.The column for being connected to same bit line can be formed One column.Column PL and first information accumulation layer 116a and multiple conductive material CM1 to CM10 formation is arranged more along row and column direction A unit string.

First information accumulation layer 116a and the second information storage layer 116b can form tunnel insulation layer, charge-trapping Layer and barrier insulating layer.At least one of tunnel insulation layer, electric charge capture layer and barrier insulating layer may include in the first letter It ceases in accumulation layer 116a.At least another in tunnel insulation layer, electric charge capture layer and barrier insulating layer may include second In information storage layer 116b.

Compared with Fig. 2, the first conductive material CM1 of the first height can form ground selection line GSLa and can select with being formed Select the control grid of transistor GSTa.Second conductive material CM2 of the second height can form ground selection line GSLb and can be with shape At the control grid of ground selection transistor GSTb.Third conductive material can be respectively formed to the 8th conductive material CM3 to CM8 One to the 6th wordline WL1 to WL6 and the control grid that the first to the 6th memory cell MC1 to MC6 can be formed.

9th conductive material CM9 of the 9th height can form string selection line SSL1a and SSL2a and can form string selection The control grid of transistor SSTa.Tenth conductive material CM10 of the tenth height can form string selection line SSL1b and SSL2b simultaneously The control grid of string select transistor SSTb can be formed.

As shown in figures 24 and 25, the structure for the interconnecting piece that lower prop PLa and upper prop PLb are connected to each other and lower prop PLa and upper The structure of any other part of column PLb is different.For example, the channel layer 114 of lower prop PLa can not the direct ditch with upper prop PLb Channel layer 114 connects, but the channel layer 114 of lower prop PLa can be connect by silicon pad SP with the channel layer 114 of upper prop PLb.Silicon Pad SP can cause and effect as the extension class of channel layer 114.

Since the structure of interconnecting piece is different from the structure of any other part, correspond to the cell transistor of interconnecting piece Characteristic may from correspond to the characteristic of cell transistor of other parts it is different.Even if apply it is identical programming, read or Erasing voltage, the change of the threshold voltage of the cell transistor corresponding to coupling part and the unit crystal corresponding to other parts The change of the threshold voltage of pipe may also can be different.That is, corresponding to the cell transistor of interconnecting piece may not normally be compiled Journey, reading or method for deleting programming are read or are wiped.

To prevent the above problem, the cell transistor corresponding to interconnecting piece may be used as illusory memory cell.It is illusory to deposit Storage unit can be not used in programming, reading or erasing data.Illusory memory cell can only provide on or off function The channel layer 114 of lower prop PLa to be electrically connected or electrically disconnected with the channel layer 114 of upper prop PLb.

Figure 26 shows the example for being used as illusory memory cell corresponding to the cell transistor of interconnecting piece.Referring to Figure 24 to figure 26, the first conductive material CM1 can form ground selection line GSL and can form the control grid of ground selection transistor GST.Second First can be respectively formed to third wordline WL1 to WL3 to the 4th conductive material CM2 to CM4 and can form first to third The control grid of memory cell MC1 to MC3.

5th conductive material CM5 can form dummy word line DWL and can form the control gate of illusory memory cell DMC Pole.6th to the 8th conductive material CM6 to CM8 can be respectively formed the 4th to the 6th wordline WL4 to WL6 and can form the 4th To the control grid of the 6th memory cell MC4 to MC6.9th and the tenth conductive material is same as described above, therefore omits them Description.

5th conductive material CM5 is shown in FIG. 26 to form dummy word line DWL.However, the embodiment of inventive concept can With without being limited thereto.For example, the 4th conductive material CM4 or the 4th and the 5th conductive material CM4 and CM5 can form one article of illusory word Line or a plurality of dummy word line.One conductive material CM1 is shown in FIG. 26 to form ground selection line.However, this shows unlimited It include the modified example in the scope and spirit of inventive concept in the case where the embodiment of inventive concept processed.

The threshold voltage of memory cell MC1 to MC6 is changed by programming operation and erasing operation.Data are by adjusting depositing The threshold voltage of storage unit MC1 to MC6 and be written into memory cell MC1 to MC6.Memory cell MC1 is written to MC6's Data are read by determining the threshold voltage of memory cell MC1 to MC6.The data that memory cell MC1 to MC6 is written are logical Crossing makes the threshold voltage of memory cell MC1 to MC6 that there is similar level to wipe.

Figure 27 is shown when executing programming operation to memory cell MC1 to MC6 and memory cell MC1 is extremely when erasing operation The change of the threshold voltage of MC6.In Figure 27, horizontal axis represents the threshold voltage of memory cell, and the longitudinal axis represents memory cell Quantity.That is, Figure 27 shows the distribution of the threshold voltage of memory cell MC1 to MC6.

Referring to Figure 26 and Figure 27, the threshold voltage of erasing operation adjustment memory cell MC1 to MC6 makes memory cell The threshold voltage of MC1 to MC6 is included in erase status " E ".Programming operation adjusts the threshold value electricity of memory cell MC1 to MC6 Pressure is so that the threshold voltage of memory cell MC1 to MC6 is included in erase status " E " and the first to the 7th programming state P1 extremely In P7.If executing programming operation, each memory cell, which can have, is included in erase status " E " and first to the 7th Threshold voltage of the programming state P1 in a state into P7.

In embodiment, when a memory cell is written in 3 bit datas, memory cell may include wiping State " E " and the first to the 7th programming state P1 are in a state into P7.It is write when by N-bit data (N is positive integer) When entering a memory cell, each memory cell can be included according to programming operation erase status " E " and first to (the 2nd^N- 1) in a state in programming state.

Figure 28 is the flow chart for showing the method that programming operation is executed to memory cell MC1 to MC6.Referring to Fig.1, Figure 26 And Figure 28, in step S710, nonvolatile memory 110 can be from external device (ED) (for example, the Memory Controller of Figure 21 120) writing commands CMD1, address AD DR1 and data DATA1 are received.In step S720, nonvolatile memory 110 can be with Received data DATA1 is loaded on page buffer circuit 115.

In step S730, nonvolatile memory 110 can execute programming operation to improve and be selected by address AD DR1 The threshold voltage of memory cell.As programming operation executes, including the storage in the first to the 7th programming state P1 into P7 The threshold voltage of device unit can be improved according to write-in data DATA1.Even if executing programming on the basis of data DATA1 is written Operation, being included in erase status E value voltage and can also keep in memory cell.

In step S740, nonvolatile memory 110 can execute verifying read operation.For example, non-volatile memories Device 110 can by using respectively with the first to the 7th programming state P1 to P7 corresponding first to M verifying voltage (M be 1 or Bigger integer) execute verifying read operation.Nonvolatile memory 110, which can determine, to be included in kth programming state (k is 1 Positive integer between M) in the threshold voltage of memory cell whether be equal to or more than kth verifying voltage.

In step S750, nonvolatile memory 110 may determine whether to pass through programming operation.If being programmed for kth The threshold voltage of the memory cell of programming state is not less than kth verifying voltage, then can pass through kth programming state.If logical The first to the 7th programming state is crossed, then can pass through programming operation (S770).If by programming operation, programming operation knot Beam.Nonvolatile memory 110 can be by the completion report of programming operation to Memory Controller 120.If not over volume Journey operation can then determine that programming operation fails.In step S760, nonvolatile memory 110 can determine programming operation The number (or circulation execute counting) that executes of circulation it is whether corresponding with largest loop.For example, the execution (S730) of programming operation, The determination (S750) that the execution (S740) and programming operation for verifying read operation pass through may be constructed a circulation.

If circulation executes, counting is not corresponding with largest loop, and nonvolatile memory 110 can execute subsequent cycle S730, S740 and S750.If it is corresponding with largest loop that circulation executes counting, in step S780, nonvolatile memory 110 can determine misprogrammed occur.Nonvolatile memory 110 can notify Memory Controller 120 in the programming operation phase Between there is mistake.

Figure 29 is the flow chart for showing the method that erasing operation is executed to memory cell MC1 to MC6.Referring to Fig.1, scheme 26, Figure 27 and Figure 29, in step S810, nonvolatile memory 110 can be from external device (ED) (for example, the memory of Figure 21 Controller 120) receive erasing order CMD1 and address AD DR1.

In step S820, nonvolatile memory 110 can execute erasing operation to reduce and be selected by address AD DR1 The threshold voltage of memory cell.In step S830, nonvolatile memory 110 can execute verifying read operation.For example, Nonvolatile memory 110 can execute verifying read operation by using verifying voltage corresponding with erase status " E ".It is non-easy The property lost memory 110 can determine whether the threshold voltage of memory cell is equal to or less than verifying voltage.

In step S840, nonvolatile memory 110 may determine whether to pass through erasing operation.If memory cell Threshold voltage be less than verifying voltage, then can pass through erasing operation (S860).If by erasing operation, erasing operation knot Beam.Nonvolatile memory 110 can be by the completion notice Memory Controller 120 of erase status.

If not over erasing operation, it is determined that erasing operation failure.In step S850, nonvolatile memory 110 can determine whether the number (or circulation executes counting) of the circulation execution of erasing operation is corresponding with largest loop.For example, wiping Except the determination (S840) that the execution (S820) of operation, the execution (S830) of verifying read operation and erasing operation pass through can be with structure It is recycled at one.

If circulation executes, counting is not corresponding with largest loop, and nonvolatile memory 110 can execute subsequent cycle S820, S830 and S840.If it is corresponding with largest loop that circulation executes counting, in step S870, nonvolatile memory 110 can determine erasure error occur.Nonvolatile memory 110 can notify Memory Controller 120 in the erasing operation phase Between there is mistake.

Return to Figure 26, illusory memory cell DMC, selection transistor GST or string select transistor SSTa and SSTb Threshold voltage it is adjustable as referring to described in Fig. 4 or Figure 20 in particular range.Later, with to memory cell MC1 Execute programming operation, erasing operation or read operation to MC6, illusory memory cell DMC, selection transistor GST or string choosing The threshold voltage for selecting transistor SSTa and SSTb can change due to interfere or coupling.

If illusory memory cell DMC, selection transistor GST or string select transistor SSTa and SSTb threshold value electricity Except pressure is beyond the range limited by verifying voltage VFYl and VFYu, then illusory memory cell DMC, selection transistor GST Or string select transistor SSTa and SSTb may not be normally connected during programming operation, read operation or erasing operation or Cut-off.

If illusory memory cell DMC, selection transistor GST or string select transistor SSTa and SSTb threshold value electricity Except pressure is beyond the range limited by verifying voltage VFYl and VFYu, then illusory memory cell DMC, selection transistor GST Or the threshold voltage of string select transistor SSTa and SSTb can be adjusted again by the first programming operation and the second programming operation In the range of being included in and limited by verifying voltage VFYl and VFYu.

Figure 30 is shown when executing the first programming operation, illusory memory cell DMC, selection transistor GST or string choosing Select the change of the threshold voltage of transistor SST.For example, string select transistor SST may include string select transistor SSTa and SSTb.In Figure 30, horizontal axis represents threshold voltage, and the longitudinal axis represents the quantity of memory cell.That is, Figure 30 shows threshold voltage Distribution.

Referring to Figure 26 and Figure 30, illusory memory cell DMC, in selection transistor GST or string select transistor SST Some threshold voltages can be less than verifying voltage VFYl.If executing the first programming operation, less than verifying voltage VFYl's Illusory memory cell DMC, selection transistor GST or string select transistor SST threshold voltage can be improved to verifying electricity Press VFYl or higher.

Figure 31 be show nonvolatile memory 110 check illusory memory cell DMC, selection transistor GST or string The flow chart of the threshold voltage and the method for the first programming operation of execution of selection transistor SST.Reference Figure 26, Figure 30 and Figure 31, In step S910, nonvolatile memory 110 may determine whether to meet inspection condition.

Inspection condition can refer to nonvolatile memory 110 check illusory memory cell DMC, selection transistor GST Or the condition that the threshold voltage of string select transistor SST must satisfy.Inspection condition may include nonvolatile memory 110 Internal environment variable or external environment variable.The example of inspection condition will be more fully described referring to Figure 36.

If being unsatisfactory for inspection condition, nonvolatile memory 110 will not check illusory memory cell DMC, select Select the threshold voltage of transistor GST or string select transistor SST.If being unsatisfactory for inspection condition, nonvolatile memory 110 Will not to illusory memory cell DMC, selection transistor GST or string select transistor SST execute the first programming operation.

If meeting inspection condition, process is carried out to step S915.In step S915, nonvolatile memory 110 Can by using verifying voltage VFYl to illusory memory cell DMC, selection transistor GST or string select transistor SST Execute verifying read operation.Nonvolatile memory 110 can determine illusory memory cell DMC, selection transistor GST or The threshold voltage of string select transistor SST is less than verifying voltage VFYl and is also equal to or greater than verifying voltage VFYl.

In step S920, nonvolatile memory 110 may determine whether to operate by checking.If memory cell DMC, selection transistor GST or string select transistor SST threshold voltage be not less than verifying voltage VFYl, then can pass through inspection Look into operation.If in step S960, nonvolatile memory 110 can not execute the first programming by checking operation Terminate process in the case where operation or can determine in the case where not executing the first programming operation to pass through the first programming operation.It Afterwards, process relevant to the first programming operation terminates.

If illusory memory cell DMC, the threshold voltage of selection transistor GST or string select transistor SST be less than Verifying voltage VFYl then checks that operation will fail.If checking operation failure, process is carried out to step S925.In step In S925, nonvolatile memory 110 can forbid the illusory memory for being equal to or more than verifying voltage VFYl to threshold voltage Cells D MC, selection transistor GST or string select transistor SST programming.

For example, can forbid depositing to being connected to the illusory of the bit line by the way that supply voltage or positive voltage are applied to bit line Storage unit DMC, selection transistor GST or string select transistor SST programming, the level of positive voltage and the level of supply voltage It is similar.

In step S930, nonvolatile memory 110 be can permit to the threshold value electricity having less than verifying voltage VFYl Press Vth illusory memory cell DMC, selection transistor GST or string select transistor SST programming.For example, can pass through by Ground voltage or low-voltage be applied to bit line allow to be connected to the bit line illusory memory cell DMC, selection transistor GST or string select transistor SST programming, the level of low-voltage and the level of ground voltage are similar.

In step S935, nonvolatile memory 110 can supply voltage according to Figure 32.Figure 32, which is shown, is applied to storage The example of the voltage of device block BLKb.Referring to Figure 26 and Figure 32, the 7th bit-line voltage VBL7 is applied to and is allowed the unit of programming The corresponding bit line BL of transistor (for example, illusory memory cell, selection transistor or string select transistor).7th bit line electricity Pressure VBL7 can be ground voltage or low-voltage, and the level of low-voltage and the level of ground voltage are similar.

8th bit-line voltage VBL8 is applied to and forbid programming cell transistor (for example, illusory memory cell, Selection transistor or string select transistor) corresponding bit line BL.8th bit-line voltage VBL8 can be supply voltage or positive voltage, The level of positive voltage and the level of supply voltage are similar.

5th program voltage VPGM5 is applied to and allow program cell transistor (for example, illusory memory cell, Ground selection transistor or string select transistor) corresponding dummy word line DWL, string selection line SSL or ground selection line GSL.5th compiles Journey voltage can be the high voltage for allowing cell transistor to undergo tunnelling.

By the 5th be applied to by voltage VPASS5 and forbid programming cell transistor (for example, illusory memory cell, Ground selection transistor or string select transistor) corresponding dummy word line DWL, string selection line SSL or ground selection line GSL.5th is logical Overvoltage VPASS5 can be smaller than the 5th program voltage VPGM5 but allow cell transistor (for example, illusory memory list Member, selection transistor or string select transistor) conducting high voltage.

Whether dummy word line DWL, string selection line SSL and ground selection line are applied to by voltage VPASS5 according to the 5th Any of GSL, the 5th can have different level or identical level by voltage VPASS5.Electricity can be passed through by the 6th Pressure VPASS6 is applied to wordline WL1 to WL6.6th can be by voltage VPASS6 it is smaller still than the 5th program voltage VPGM5 The high voltage for allowing memory cell MC1 to MC6 to be connected.Whether wordline WL1 is applied to by voltage VPASS6 according to the 6th Any of to WL6, the 6th can have different level or identical level by voltage VPASS6.

5th common source line voltage VCSL5 is applied to common source line CSL.5th common source line voltage VCSL5 can be ground voltage Or low-voltage, the level of low-voltage and the level of ground voltage are similar.

Figure 26, Figure 30 and Figure 31 are returned to, in step S940, nonvolatile memory 110 can be by using verifying electricity Press VFYl to illusory memory cell DMC, selection transistor GST or string select transistor SST execute verifying read operation.It is non- Volatile memory 110 can determine illusory memory cell DMC, selection transistor GST or string select transistor SST threshold Threshold voltage is less than verifying voltage VFYl and is also equal to or greater than verifying voltage VFYl.

In step S945, nonvolatile memory 110 be may determine whether through the first programming operation.If illusory deposit Storage unit DMC, selection transistor GST or string select transistor SST threshold voltage be not less than verifying voltage VFYl, then exist In step S960, the first programming operation can be passed through.Nonvolatile memory 110 can terminate the first programming operation.

If illusory memory cell DMC, the threshold voltage of selection transistor GST or string select transistor SST be less than Verifying voltage VFYl, then the first programming operation will fail, and process proceeds to step S950.It is non-volatile to deposit in step S950 Whether the number (or circulation executes counting) that reservoir 110 can determine that the circulation of programming operation executes is corresponding with largest loop.Example Such as, step S925 to step S945 can form a circulation of the first programming operation.

If circulation executes, counting is not corresponding with largest loop, and nonvolatile memory 110 can execute subsequent cycle. If circulation executes, counting is corresponding with largest loop, and in step S955, nonvolatile memory 110 can be determined and be compiled Journey mistake.Nonvolatile memory 110 can notify Memory Controller 120 mistake occur during the first programming operation.

Figure 33 show when executing the second programming operation illusory memory cell DMC, selection transistor GST or string selection The variation of the threshold voltage of transistor SST.In Figure 33, horizontal axis represents threshold voltage, and the longitudinal axis represents the quantity of memory cell. That is, Figure 33 shows the distribution of threshold voltage.

Referring to Figure 26 and Figure 33, illusory memory cell DMC, in selection transistor GST or string select transistor SST Some threshold voltages may be greater than verifying voltage VFYu.It is bigger than verifying voltage VFYu if executing the second programming operation Illusory memory cell DMC, the threshold voltage of selection transistor GST or string select transistor SST can be reduced to verifying Voltage VFYu or smaller.

Figure 34 be show nonvolatile memory 110 check illusory memory cell DMC, selection transistor GST or string The flow chart of the threshold voltage and the method for the second programming operation of execution of selection transistor SST.Reference Figure 26, Figure 33 and Figure 34, In step S1010, nonvolatile memory 110 may determine whether to meet inspection condition.

If being unsatisfactory for inspection condition, nonvolatile memory 110 can not check illusory memory cell DMC, The threshold voltage of selection transistor GST or string select transistor SST.In addition, if being unsatisfactory for inspection condition, it is non-volatile to deposit Reservoir 110 can not to illusory memory cell DMC, selection transistor GST or string select transistor SST execute the second programming Operation.

If meeting inspection condition, process is carried out to step S1015.In step S1015, nonvolatile memory 110 can by using verifying voltage VFYu to illusory memory cell DMC, selection transistor GST or string select transistor SST executes verifying read operation.Nonvolatile memory 110 can determine illusory memory cell DMC, selection transistor The threshold voltage of GST or string select transistor SST are greater than verifying voltage VFYu and are still equal to or less than verifying voltage VFYu.

In step S1020, nonvolatile memory 110 may determine whether to operate by checking.If illusory storage Device cells D MC, the threshold voltage of selection transistor GST or string select transistor SST be not more than verifying voltage VFYu, then can be with It is operated by checking.If in step S1060, nonvolatile memory 110 can not execute the by checking operation Terminate process in the case where two programming operations, or can determine in the case where not executing the second programming operation and be compiled by second Journey operation.Later, process relevant to the second programming operation terminates.

If illusory memory cell DMC, the threshold voltage of selection transistor GST or string select transistor SST be greater than Verifying voltage VFYu then checks that operation will fail.If checking operation failure, process is carried out to step S1025.In step In S1025, nonvolatile memory 110 can be forbidden illusory equal to or less than the threshold voltage of verifying voltage VFYu to having Memory cell DMC, selection transistor GST or string select transistor SST programming.

For example, can forbid depositing to being connected to the illusory of the bit line by the way that supply voltage or positive voltage are applied to bit line Storage unit DMC, selection transistor GST or string select transistor SST programming, the level of positive voltage and the level of supply voltage It is similar.

In step S1030, nonvolatile memory 110 be can permit to the threshold value electricity bigger than verifying voltage VFYu Press Vth illusory memory cell DMC, selection transistor GST or string select transistor SST programming.For example, can pass through by Ground voltage or low-voltage be applied to bit line allow to be connected to the bit line illusory memory cell DMC, selection transistor GST or string select transistor SST programming, the level of low-voltage and the level of ground voltage are similar.

In step S1035, nonvolatile memory 110 can supply voltage according to Figure 35.Figure 35, which is shown, to be applied to The example of the voltage of memory block BLKb.Referring to Figure 26, Figure 34 and Figure 35, the 9th bit-line voltage VBL9 is applied to and allows to compile The bit line BL of cell transistor (for example, illusory memory cell, the selection transistor or string select transistor) comparison of journey.The Nine bit-line voltage VBL9 can be supply voltage or positive voltage, and the level of positive voltage and the level of supply voltage are similar.

Tenth bit-line voltage VBL10 is applied to and forbid programming cell transistor (for example, illusory memory cell, Ground selection transistor or string select transistor) corresponding bit line BL.Tenth bit-line voltage VBL10 can be ground voltage or low electricity Pressure, the level of low-voltage and the level of ground voltage are similar.

6th program voltage VPGM6 is applied to and allow program cell transistor (for example, illusory memory cell, Ground selection transistor or string select transistor) corresponding dummy word line DWL, string selection line SSL or ground selection line GSL.6th compiles Journey voltage VPGM6 can have the level for causing hot hole to inject in memory transistor.6th program voltage VPGM6 can be with With the level lower than third common source line voltage VCSL3.6th program voltage VPGM6, which can have, is enough to make illusory memory list Member, selection transistor or string select transistor cut-off level.

By the 7th be applied to by voltage VPASS7 and forbid programming cell transistor (for example, illusory memory cell, Ground selection transistor or string select transistor) corresponding dummy word line DWL, string selection line SSL or ground selection line GSL.7th compiles Can be by voltage VPASS7 allow cell transistor (for example, illusory memory cell, selection transistor or string selection it is brilliant Body pipe) conducting high voltage.

Whether dummy word line DWL, string selection line SSL and ground selection line are applied to by voltage VPASS7 according to the 7th Any of GSL, the 7th can have different level or identical level by voltage VPASS7.Electricity can be passed through by the 8th Pressure VPASS8 can be applied to wordline WL1 to WL6.8th can be by voltage VPASS8 and be enough to be connected memory cell MC1 extremely The high voltage of MC6.Whether any of wordline WL1 to WL6 is applied by voltage VPASS8 according to the 8th, the 8th passes through electricity Pressure VPASS8 can have different level or identical level.

6th common source line voltage VCSL6 is applied to common source line CSL.6th common source line voltage VCSL6 can be ground voltage Or low-voltage, the level of low-voltage and the level of ground voltage are similar.

Figure 26, Figure 33 and Figure 34 are returned to, in step S1040, nonvolatile memory 110 can be by using verifying electricity Press VFYu to illusory memory cell DMC, selection transistor GST or string select transistor SST execute verifying read operation.It is non- Volatile memory 110 can determine illusory memory cell DMC, selection transistor GST or string select transistor SST threshold Threshold voltage is greater than verifying voltage VFYu and is still equal to or less than verifying voltage VFYu.

In step S1045, nonvolatile memory 110 be may determine whether through the second programming operation.If illusory Memory cell DMC, selection transistor GST or string select transistor SST threshold voltage be not more than verifying voltage VFYu, then The second programming operation (S1060) can be passed through.Nonvolatile memory 110 can terminate the second programming operation.

If illusory memory cell DMC, the threshold voltage of selection transistor GST or string select transistor SST be greater than Verifying voltage VFYu, then the second programming operation will fail.If the second programming operation fails, process is carried out to step S1050. In step S1050, nonvolatile memory 110 can determine programming operation circulation execute number (or circulation execute meter Number) it is whether corresponding with largest loop.For example, step S1025 to step S1045 can form the second programming operation one follows Ring.

If circulation executes, counting is not corresponding with largest loop, and nonvolatile memory 110 can execute subsequent cycle. If circulation executes, counting is corresponding with largest loop, and in step S1055, nonvolatile memory 110 can determine appearance Misprogrammed.Nonvolatile memory 110 can notify Memory Controller 120 mistake occur during the second programming operation.

It, can be with according to the nonvolatile memory 110 of the embodiment of inventive concept as described above, when meeting inspection condition Check threshold voltage less than verifying voltage VFYl illusory memory cell DMC, selection transistor GST or string select transistor SST.Nonvolatile memory 110 can to threshold voltage less than verifying voltage VFYl illusory memory cell DMC, select Transistor GST or string select transistor SST executes the first programming operation to allow its threshold voltage to improve.

When meeting inspection condition, threshold value electricity can be checked according to the nonvolatile memory 110 of the embodiment of inventive concept Pressure greater than verifying voltage VFYu illusory memory cell DMC, selection transistor GST or string select transistor SST.It is non-volatile Property memory 110 can to threshold voltage greater than verifying voltage VFYu illusory memory cell DMC, selection transistor GST Or string select transistor SST executes the second programming operation to allow the reduction of its threshold voltage.

Therefore, though illusory memory cell DMC, selection transistor GST or string select transistor SST threshold voltage Change due to interfere or coupling, illusory memory cell DMC, selection transistor GST or string select transistor SST threshold value Voltage can also be adjusted to belong to the range limited by verifying voltage VFYl and VFYu.It is non-volatile this may imply improving The reliability of memory 110.

In embodiment, inspection condition (hereinafter referred to as " first checks condition ") relevant to verifying voltage VFYl It can be different from inspection condition (hereinafter referred to as " second checks condition ") relevant to verifying voltage VFYu.When meeting the When one inspection condition, the first programming operation can be executed, when satisfaction second checks condition, the second programming operation can be executed.

As another example, first check that condition can check that condition is identical with second.When meeting mutually the same first When inspection condition and the second inspection condition, nonvolatile memory 110 can execute the first programming operation and the second programming operation The two.Check that operation and second checks that nonvolatile memory 110 can choose simultaneously when operating when meeting mutually the same first Execute one of the first programming operation and the second programming operation.

Figure 36 shows the example of the inspection condition according to the embodiment of inventive concept.Referring to Figure 1 and Figure 36, the condition of inspection can To be the temperature of nonvolatile memory 110 or the storage device 100 including nonvolatile memory 110.Be equal to when temperature or When greater than the first temperature T1, inspection condition can satisfy.

When meeting inspection condition, nonvolatile memory 110 can execute the first programming operation or the second programming operation. If temperature than the first temperature T1 high, nonvolatile memory 110 can execute periodically at any time the first programming operation or Second programming operation.

When temperature is equal to or less than second temperature T2, inspection condition can satisfy.Nonvolatile memory 110 can be held The first programming operation of row or the second programming operation.If temperature is less than second temperature T2, nonvolatile memory 110 can be with Execute the first programming operation or the second programming operation periodically at any time.

First temperature T1 and second temperature T2 can be collectively included in inspection condition.As another example, the first temperature One in T1 and second temperature T2 can be included in inspection condition, another can be not included in inspection condition In.

Inspection condition can also include the number of programming operation or erasing operation.Memory block BLK1 to BLKz can be directed to Each of manage the number of programming operation or erasing operation.For example, can be managed by using multiple counting periods The number of programming operation or erasing operation.For example, counting 0 to 999 may belong to the period 1, counting 1000 to 1999 can belong to In second round.

When the programming operation of particular memory block or the number of erasing operation change from a cycle (for example, period 1) When to another period (for example, second round), inspection condition can satisfy.When meeting inspection condition, non-volatile memories Device 110 can execute the first programming operation or the second programming operation.In embodiment, count the period can be uniformly in magnitude 's.As another example, counting the period can be different from each other in magnitude.

For example, the counting period can reduce as programming operation or the number of erasing operation increase.That is, as programming is grasped Make or the number of erasing operation increases, nonvolatile memory 110 can increase the first programming operation or the second programming operation Execute frequency.

Inspection condition can also include the operation of nonvolatile memory 110.For example, if in inspection operation before Inspection condition after or before (for example, S1010 of the S910 or Figure 34 of Figure 31) executes the number of erasing operation after meeting Equal to the first reference count R1, then it can satisfy inspection condition.If the programming operation executed after inspection operation before Number be equal to the second reference count R2 when, then can satisfy inspection condition.First reference count R1 can have fixed value.Such as The number for the read operation that fruit executes after inspection operation before is equal to third reference count R3, then can satisfy inspection item Part.

First can have fixed value each of to third reference count R1 to R3.As another example, first to Three reference count R1 to R3 can have the value determined according to previously determined table or formula.As another example, first to Each of three reference count R1 to R3 can have the value generated at random after checking operation.

Inspection condition can also include the time.For example, if operating in inspection before (for example, the S910 or figure of Figure 31 34 S1010) after elapsed time be equal to or more than the first reference time T1, then can satisfy testing conditions.First reference Time can have fixed value.As another example, the first reference time T1 can have according to previously determined table or formula Determining value.As another example, the first reference time T1 can have the value generated at random after checking operation.

Figure 37 shows the application example of the memory block BLKb of Figure 26.Referring to Figure 37, memory block BLKc's selects with ground Line GSL adjacent wordline can be the first dummy word line DWL1.The memory cell for being connected to the first dummy word line DWL1 can be with It is the first illusory memory cell DMC1.The wordline adjacent with string selection line SSL1a and SSL2a of memory block BLKc can be Second dummy word line DWL2.Being connected to the second dummy word line DWL2 memory cell can be the second illusory memory cell DMC2。

Wordline between first dummy word line DWL1 and the second dummy word line DWL2 can be the first to the 5th wordline WL1 extremely WL5.First to the 5th wordline WL1 to WL5 can be respectively connected to the first to the 5th memory cell MC1 to MC5.Dummy word line Position can be not limited to interconnecting piece as shown in figure 26.Such as, if it is desired, dummy word line can be set in memory block The various positions of BLKc.

According to the exemplary embodiment of inventive concept, the threshold voltage of cell transistor especially selection transistor can be with It is programmed in target zone.It thus provides having the non-volatile memory device of the reliability improved non-volatile with this The operating method of memory device.

Although inventive concept is described referring to the exemplary embodiment of inventive concept, to those skilled in the art It will be apparent that in the case where not departing from the range for the inventive concept being defined by the claims various changes can be carried out to it And modification.

Claims (20)

1. a kind of method of operating nonvolatile memory device, the non-volatile memory device includes multiple unit strings, Each unit string includes at least one the string choosing stacked along the direction vertical with the surface for being provided with unit string of substrate Select transistor, multiple memory cells, at least one illusory memory cell and at least one ground selection transistor, the side Method includes:

First programming operation is executed to the first illusory memory cell in the multiple unit string, after the first programming operation, First illusory memory cell has first threshold voltage；

Verification operation is executed to the first illusory memory cell using verifying voltage, verifying voltage is the first illusory memory cell The upper limit of target threshold voltage after the first programming operation；

Determine whether first threshold voltage is higher than verifying voltage；

In the case where determining that first threshold voltage is higher than verifying voltage, the second programming is executed to the first illusory memory cell and is grasped Make to reduce the threshold voltage of the first illusory memory cell from first threshold voltage, after the second programming operation, first is empty If memory cell has second threshold voltage,

Wherein, second threshold voltage is lower than first threshold voltage.

2. according to the method described in claim 1, wherein, the first programming operation is for by the threshold of the first illusory memory cell Threshold voltage is increased to the operation of first threshold voltage from initial threshold voltage, and including the first programming operation voltage to be applied to The step of grid of first illusory memory cell and by low-voltage supplied to the first illusory memory cell channel step Suddenly, the first programming operation voltage is positive voltage.

3. according to the method described in claim 2, wherein, low-voltage is supplied by following steps: illusory by being coupled to first The bit line of memory cell is by the first low-voltage supplied to the drain electrode of the first illusory memory cell and by being coupled to first Second low-voltage is supplied to the source electrode of the first illusory memory cell by the common source line of illusory memory cell.

4. according to the method described in claim 3, wherein, the first low-voltage and the second low-voltage are ground voltage respectively.

5. according to the method described in claim 1, wherein, the second programming operation includes that the second programming operation voltage is applied to The step of grid of one illusory memory cell, the second programming operation voltage is negative voltage.

6. according to the method described in claim 5, wherein, the second programming operation further includes by being coupled to the first illusory memory Third low-voltage is supplied to the step of source electrode of the first illusory memory cell by the common source line of unit.

7. according to the method described in claim 6, wherein, by respectively by the first high voltage be provided to selection bit line and will Second high voltage is provided to the grid of corresponding string select transistor, and the drain electrode of the first illusory memory cell is electrically floating.

8. according to the method described in claim 7, wherein, the second programming operation further includes to the unit string of selection in addition to first The grid of memory cell and illusory memory cell except the grid of illusory memory cell is applied through voltage.

9. according to the method described in claim 1, wherein, the method also includes:

First programming operation is executed to the second illusory memory cell in the multiple unit string, to improve the second illusory storage The threshold voltage of device unit, after the first programming operation, the second illusory memory cell has third threshold voltage；

Verification operation is executed to the second illusory memory cell using verifying voltage；

Determine whether third threshold voltage is equal to or less than verifying voltage；

In the case where determining that third threshold voltage is equal to or less than verifying voltage, the is being executed to the first illusory memory cell While two programming operations, the second programming operation is forbidden to the second illusory memory cell.

10. a kind of method of operating nonvolatile memory device, the non-volatile memory device includes multiple unit strings, Each unit string includes at least one the string choosing stacked on the direction vertical with the surface for being provided with unit string of substrate Select transistor, multiple memory cells, at least one illusory memory cell and at least one ground selection transistor, the side Method includes:

Determine whether to meet inspection condition；

In the case where determination meets inspection condition, the first ground in the multiple unit string is selected using the first verifying voltage Transistor executes verifying read operation；

Determine whether the first threshold voltage of the first ground selection transistor is higher than the first verifying voltage；

In the case where determining that the first threshold voltage of the first ground selection transistor is higher than the first verifying voltage, select the first Transistor executes the first programming operation, to reduce the first threshold voltage of the first ground selection transistor.

11. according to the method described in claim 10, wherein, when temperature is greater than or equal to the first temperature or when temperature is less than Or meet inspection condition when equal to second temperature, wherein second temperature is less than the first temperature.

12. according to the method described in claim 10, wherein, when the volume of the relevant memory cell of selection transistor to the first Journey or the number of erasing meet inspection condition when increasing another numbers range to enter in multiple numbers ranges.

13. according to the method for claim 12, wherein the number with programming or the erasing of memory cell increases, often The size of a numbers range reduces.

14. brilliant when being selected after inspection condition before meets with the first according to the method described in claim 10, wherein The number of the programming operation of the relevant memory cell of body pipe, read operation or erasing operation is greater than or equal to full when reference number of times Foot checks condition.

15. according to the method described in claim 10, wherein, being held when to the relevant memory cell of the selection transistor to the first Gone erasing operation when meet inspection condition.

16. according to the method described in claim 10, the method also includes:

In the case where determination meets inspection condition, the second ground in the multiple unit string is selected using the first verifying voltage Transistor executes verifying read operation；

Determine whether the second threshold voltage of the second ground selection transistor is higher than the first verifying voltage；

In the case where determining the second threshold voltage of the second ground selection transistor not higher than the first verifying voltage, to the first While selection transistor executes the first programming operation, to the second, selection transistor forbids the first programming operation.

17. according to the method described in claim 10, the method also includes:

In the case where determination meets inspection condition, using the second verifying voltage to the illusory memory in the multiple unit string Unit executes the second verifying read operation；

Determine whether the threshold voltage of illusory memory cell is higher than the second verifying voltage；

In the case where determining that the threshold voltage of illusory memory cell is higher than the second verifying voltage, illusory memory cell is held The second programming operation of row, to reduce the threshold voltage of illusory memory cell.

18. according to the method described in claim 10, the method also includes:

In the case where determining the first threshold voltage of the first ground selection transistor not higher than the first verifying voltage, tested using third Demonstrate,proving voltage, selection transistor executes third verifying read operation to the first；

Determine whether the first threshold voltage of the first ground selection transistor is lower than third verifying voltage；

In the case where determining the first threshold voltage of the first ground selection transistor lower than third verifying voltage, select the first Transistor executes third programming operation, to improve the first threshold voltage of the first ground selection transistor.

19. according to the method described in claim 10, the method also includes:

In the case where determination meets inspection condition, using the 4th verifying voltage to the illusory memory in the multiple unit string Unit executes the 4th verifying read operation；

Determine whether the threshold voltage of illusory memory cell is lower than the 4th verifying voltage；

In the case where determining the threshold voltage of illusory memory cell lower than four verifying voltages, illusory memory cell is held The 4th programming operation of row, to improve the threshold voltage of illusory memory cell.

20. a kind of method of operating nonvolatile memory device, the non-volatile memory device includes multiple unit strings, Each unit string includes at least one the string choosing stacked on the direction vertical with the surface for being provided with unit string of substrate Select transistor, multiple memory cells, at least one illusory memory cell and at least one ground selection transistor, the side Method includes:

First programming operation is executed to the memory cell in the multiple unit string, to improve the first threshold of memory cell Voltage, according to the first threshold voltage programmed, programmed memory cell has in erase status and multiple programming states A kind of state；

When at least one of ground selection transistor, string select transistor and the illusory memory cell in the multiple unit string At least one second threshold voltage when being higher than the first verifying voltage, selection transistor, string select transistor and illusory deposit over the ground At least one described second programming operation of execution in storage unit, to reduce ground selection transistor, string select transistor and void If at least one described at least one described second threshold voltage in memory cell；

When at least one described second threshold voltage is lower than the second verifying voltage, selection transistor, string select transistor over the ground With in illusory memory cell described at least one execute third programming operation, to improve at least one second threshold electricity Pressure.