CN109658509B

CN109658509B - Long and narrow pattern spot partitioning method and device, computer equipment and storage medium

Info

Publication number: CN109658509B
Application number: CN201811507162.9A
Authority: CN
Inventors: 李成名; 殷勇; 武鹏达; 吴伟; 郭沛沛; 刘晓丽; 戴昭鑫
Original assignee: Chinese Academy of Surveying and Mapping
Current assignee: Chinese Academy of Surveying and Mapping
Priority date: 2018-12-11
Filing date: 2018-12-11
Publication date: 2020-12-01
Anticipated expiration: 2038-12-11
Also published as: CN109658509A

Abstract

The invention relates to the technical field of map making and map synthesis, in particular to a method and a device for partitioning a long and narrow pattern spot, computer equipment and a storage medium. The method comprises the following steps: acquiring the image spot data, and dividing a regular grid to decompose the image spot data into a plurality of subdata sets; identifying the long and narrow pattern spots in the sub data sets, and respectively calculating the area sum of the long and narrow pattern spots in each sub data set; and finely dividing the regular grid based on the area and balance to finish the blocking of the long and narrow pattern spots. The invention finely divides the grids according to the area and balance, ensures that the area sum of the long and narrow pattern spots in each grid falls within a set range, is suitable for parallel calculation, is favorable for load balance of a computer, can improve the calculation efficiency during calculation of large data volume, saves the calculation resources, prevents program collapse caused by insufficient memory of the computer during calculation, and ensures the stability of data calculation.

Description

Long and narrow pattern spot partitioning method and device, computer equipment and storage medium

Technical Field

The invention relates to the technical field of map making and map synthesis, in particular to a method and a device for partitioning a long and narrow pattern spot, computer equipment and a storage medium.

Background

With the increase of the application depth and the application range of the geographical national situation census data, the requirement of comprehensively reflecting the regional land utilization condition in a multilevel manner from large-scale ground coverage data (map spots) to various small-scale data is more and more urgent. A dissolving (resolving) operation of a long and narrow pattern spot is a common operation in the automatic land use data integration process, and when a map changes from a large scale to a small scale, the long and narrow pattern spot on the map cannot be continuously perceived visually, so that the long and narrow pattern spot on the map has to be split to an adjacent pattern spot through the dissolving operation. The main steps of the melting operation are as follows: (1) defining a width standard threshold, and identifying a long and narrow pattern spot in a piece of full-coverage pattern spot data; when the land utilization data space participating in the melting is large, a blocking strategy needs to be introduced, the core of the blocking strategy is to divide mass map data into data subsets with small areas, and then each data subset is processed in parallel, thereby improving the automatic comprehensive efficiency on the basis of fully utilizing the computing capability of a machine.

The chunky approach is a key step in implementing the chunky strategy, Chaudhry et al (2010) indicate that the chunky approach has a direct impact on the overall quality and efficiency. In the existing research, the blocking method can be divided into two types, namely a blocking method based on a regular grid and a blocking method based on a geographic unit, according to different blocking units. Generally, the regular grid blocking method is to divide an area based on a grid with a regular shape such as a square or a rectangle, Thiemann and the like (2011) performs aggregation operation of land utilization data by applying the blocking method, so that a good comprehensive effect is obtained; touya et al (2017) further apply the method to road route simplification and building face selection operation, and experiments show that the regular grid blocking method is simple, easy to use and high in efficiency, and is particularly suitable for comprehensive operators without considering context. However, when the region is divided based on the regular grids such as squares and rectangles, the situation that the internal elements to be processed are distributed too densely can occur in the partial grids, and the calculation efficiency is affected, therefore, Briat and the like (2011) provides a quadtree grid partitioning method to optimize the traditional regular grid partitioning method, and performs hierarchical division on the region with higher element density according to the quadtree.

For the thawing operation, the areas of the narrow and long pattern spots in different grids obtained according to the two blocking methods still have great difference, so that the data throughput of each computing node is different during parallel processing, load balance of machine computing is not facilitated, and the thawing efficiency is influenced.

Disclosure of Invention

Therefore, it is necessary to provide a method and an apparatus for partitioning a long and narrow pattern patch, a computer device and a storage medium, which solve the problems that in the prior art, the areas of the long and narrow pattern patches in a grid network are greatly different, so that the data throughput of each computing node is different during parallel processing, load balance of machine computing is not facilitated, and the fusion efficiency is affected.

The embodiment of the invention is realized in such a way that a long and narrow pattern spot blocking method comprises the following steps:

acquiring the image spot data, and dividing a regular grid to decompose the image spot data into a plurality of subdata sets;

identifying the long and narrow pattern spots in the sub data sets, and respectively calculating the area sum of the long and narrow pattern spots in each sub data set;

and finely dividing the regular grid based on the area and balance to finish the blocking of the long and narrow pattern spots.

In another embodiment of the present invention, there is provided an elongate patch sectioning device, the device including:

the data acquisition and decomposition module is used for acquiring the pattern spot data and dividing a regular grid to decompose the pattern spot data into a plurality of subdata sets;

a long and narrow pattern spot identification module, configured to identify a long and narrow pattern spot in the sub data set, and calculate an area sum of the long and narrow pattern spot in each sub data set respectively;

and the long and narrow pattern spot dividing module is used for finely dividing the regular grid based on the area sum balance to finish the block division of the long and narrow pattern spots.

In another embodiment of the present invention, a computer device is provided, the computer device comprising a memory and a processor, the memory having stored therein a computer program, which, when executed by the processor, causes the processor to perform the steps of one of the above-described elongated patch blocking methods.

In a further embodiment of the present invention, a computer-readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, causes the processor to perform the steps of a long and narrow spot segmentation method as described above.

The method, the device, the computer equipment and the storage medium for partitioning the long and narrow pattern spots have the advantages that the obtained pattern spot data are partitioned to obtain the sub data sets, the long and narrow pattern spots in the sub data sets are identified, each grid is finely partitioned based on the area and balance of the long and narrow pattern spots in each sub data set, and the long and narrow pattern spots and the partitioning are completed. The invention finely divides the grids according to the area and balance, ensures that the area sum of the long and narrow pattern spots in each grid falls within a set range, is suitable for parallel calculation, is favorable for load balance of a computer, can improve the calculation efficiency during calculation of large data volume, saves the calculation resources, prevents program collapse caused by insufficient memory of the computer during calculation, and ensures the stability of data calculation.

Drawings

FIG. 1 is a flow chart of a method for chunking a narrow pattern spot according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a skeleton line calculation method according to an embodiment of the present invention;

FIG. 3(a) is a schematic diagram of the area imbalance of the elements to be processed in the mesh, and FIG. 3(b) is a schematic diagram of the fine-grained pattern spots generated at the boundary of the mesh;

fig. 4(a) is a schematic diagram before buffer construction, fig. 4(b) is a schematic diagram of buffer construction with distance D using SL1 as a reference, and fig. 4(c) is a schematic diagram of modified grid boundaries;

FIG. 5 is a graph of raw experimental data for experiments conducted in accordance with the present invention;

FIG. 6 is a graph showing the results of a melting experiment performed on a multi-component grid according to the present invention;

fig. 7(a) is a schematic diagram of a blocking result of a regular grid in an area where the long and narrow pattern spots are uniformly distributed, fig. 7(b) is a schematic diagram of a blocking result of a quadtree grid in an area where the long and narrow pattern spots are uniformly distributed, and fig. 7(c) is a schematic diagram of a blocking result of a text method in an area where the long and narrow pattern spots are uniformly distributed;

fig. 8(a) is a schematic diagram of a blocking result of a regular grid in an unbalanced distribution region of a narrow and long pattern spot, fig. 8(b) is a schematic diagram of a blocking result of a quadtree grid in an unbalanced distribution region of a narrow and long pattern spot, and fig. 8(c) is a schematic diagram of a blocking result of a method herein in an unbalanced distribution region of a narrow and long pattern spot;

FIG. 9(a) is a diagram of a minimum spot at a boundary, FIG. 9(b) is a diagram of a grid boundary modification using the present invention, and FIG. 9(c) is a diagram of a fusion result after modification using the present invention;

fig. 10(a) is a schematic diagram of a fine small pattern spot at the boundary of a common pattern spot, fig. 10(b) is a schematic diagram of a melting result before the correction of the common pattern spot, fig. 10(c) is a schematic diagram of the correction of the boundary of a common pattern spot grid, and fig. 10(d) is a schematic diagram of a melting result after the correction of the common pattern spot;

FIG. 11 is a block diagram of an embodiment of an apparatus for partitioning an elongated pattern;

fig. 12 is a block diagram showing an internal configuration of a computer device according to an embodiment of the present invention.

In the figure, 1, a narrow spot boundary; 2. grid forming; 3. and (4) elements of the map class.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms unless otherwise specified. These terms are only used to distinguish one element from another. For example, a first xx script may be referred to as a second xx script, and similarly, a second xx script may be referred to as a first xx script, without departing from the scope of the present application.

As shown in fig. 1, in an embodiment, a method for partitioning a long and narrow pattern spot is provided, which may specifically include the following steps:

step S101, obtaining pattern spot data, and dividing a regular grid to decompose the pattern spot data into a plurality of subdata sets;

step S102, identifying the long and narrow pattern spots in the sub data sets, and respectively calculating the area sum of the long and narrow pattern spots in each sub data set;

and step S103, finely dividing the regular grid based on the area and balance to finish the blocking of the long and narrow pattern spots.

In the embodiment of the present invention, in step S101, to obtain the patch data, a regular grid is divided to decompose the patch data into a plurality of sub-data sets. The data is spot data input by a user, such as vector full-coverage spot data. The regular grid refers to grids with regular shapes such as rectangles and triangles (e.g., regular triangles), and the invention is described by taking a rectangle as an example. The invention introduces a blocking strategy, the core of the blocking strategy is to divide mass map data into data subsets with smaller areas, and then each data subset is processed in parallel, so that the comprehensive efficiency can be improved on the basis of fully utilizing the computing capacity of a machine.

In this embodiment of the present invention, in step S102, the area sum of the long and narrow patches in each sub-data set is calculated for identifying the long and narrow patches in the sub-data set. The narrow and long pattern spots refer to some long and narrow objects in the pattern spots, such as a narrow and long planar river, a low-level planar road, a highway, a field ridge, a ditch and the like, and the narrow and long pattern spots usually connect a plurality of different types of pattern spots of the ground objects, and have an important role in maintaining topological connectivity of the pattern spots of the ground objects. When the scale is small, the narrow and long pattern spot is reduced in dimension from a two-dimensional planar feature to a one-dimensional linear feature due to the small width.

In this embodiment of the present invention, in step S103, the regular grid is finely divided based on the area and balance, and the blocking of the long and narrow pattern spots is completed. In the present invention, the area sum balance means that the areas of the elongated patches included in different grids are substantially the same and are close to the average value of the areas of the elongated patches included in the grids. Therefore, the calculation amount of each grid is basically consistent when the computer performs parallel processing on the data in each grid.

The narrow and long pattern blocking method provided by the embodiment of the invention is characterized in that a sub-data set is obtained by dividing the obtained pattern data, narrow and long patterns in the sub-data set are identified, and each grid is finely divided based on the area and balance of the narrow and long patterns in each sub-data set, so that the narrow and long patterns and the blocking are completed. The invention finely divides the grids according to the area and balance, ensures that the area sum of the long and narrow pattern spots in each grid falls within a set range, is suitable for parallel calculation, is favorable for load balance of a computer, can improve the calculation efficiency during calculation of large data volume, saves the calculation resources, prevents program collapse caused by insufficient memory of the computer during calculation, and ensures the stability of data calculation.

In an embodiment, in step S101, the dividing rule grid decomposes the patch data into a plurality of sub-data sets, which may specifically include the following steps:

step S201, calculating the minimum circumscribed rectangle of the pattern spot area;

step S202, calculating equidistant segmentation points of the minimum circumscribed rectangle according to the set row number and column number of the regular grid;

step S203, generating the regular grid which is parallel to the coordinate axis of the partition point and is not coincident with the coordinate axis of the partition point according to the equal-interval partition points, and obtaining a plurality of subdata sets.

In the embodiment of the present invention, step S201 is to calculate the minimum bounding rectangle of the speckle region. The Minimum Bounding Rectangle (MBR) is a rectangle that surrounds a geometric body, has a boundary parallel to coordinate axes, and has a minimum area, and can be calculated by calculating coordinates of a lower left corner point and an upper right corner point of a spot region, or coordinates of a lower right corner point and an upper left corner point.

In the embodiment of the present invention, in step S202, the equidistant dividing points of the minimum bounding rectangle are calculated according to the set number of rows and columns of the regular grid. In the present invention, the number of rows and columns of the grid needs to be set in advance, and it should be noted that the number of rows and columns of the preset grid will affect the average value of the area of the narrow and long patches in the grid, but the present invention implements fine division based on the balance of the values, so the number of rows and columns should be appropriate, for example, considering the amount of parallel processing from the computer, considering the total area of the narrow and long patches, and the like.

The specific method comprises the following steps: calculating the minimum circumscribed rectangle according to the spatial distribution range of the pattern spots, and setting multiple groups of initial row and column numbers n₁、n₂、…、n_mThe length and width of the MBR are equally divided to form n₁×n₁、n₂×n₂、…、n_m×n_mThe multiple regular grids are divided into scales, the fusion calculation time under each grid scale is respectively counted, the grid size with the optimal fusion efficiency is used as the optimum grid size of the region, and the row and column number is determined. Of course, n can also be examined according to the specific distribution of the pattern spots₁×n₂、n₂×n₁And the like, and the above combinations are for illustration only.

In this embodiment of the present invention, in step S203, the regular grid parallel to and not overlapping with the coordinate axis of the partition point is generated according to the equidistant partition points, so as to obtain a plurality of the sub data sets. The coordinate axis in the invention is the coordinate axis in a Cartesian coordinate system, the horizontal axis is the east-west direction, and the vertical axis is the north-south direction. The division points determine the number of rows and columns of the grid boundary, and the coordinate axis determines the direction of the grid boundary.

In the invention, the speckle data is divided into a plurality of sub-data sets by the division rule grid, so that the parallel processing of massive speckle data can be realized, the computing resources are fully utilized, and the computing efficiency is improved.

In an embodiment, the identifying the long and narrow pattern spots in the sub data set in step S102 may specifically include the following steps:

step S301, calculating the width of the pattern spot;

step S302, setting a width threshold value, and comparing the width of the image spot with the width threshold value to identify a long and narrow image spot.

In the embodiment of the present invention, step S301 calculates the width of the pattern patch. The width of the elongated pattern spot can be calculated based on the following equation:

W＝S/BL (1)

wherein W is the approximate average width of the image spot, S is the area of the image spot, and BL is the longest skeleton line of the image spot. The calculation method of the skeleton line comprises the following steps:

(1) constructing a boundary constraint Delaunay triangulation (Delaunay triangulation) for the elongated patches;

(2) according to the number of adjacent triangles of the triangle inside the polygon, the triangle is subdivided into three categories:

class i triangle: there is one and only one adjacent triangle, the two sides of which form the boundaries of the polygon, of the class i triangle. As shown in FIG. 2, each of the vertices A, D, F is an end point of a skeleton line, such as Δ ABG, Δ CDE, and Δ EFG.

Class II triangles: there are two adjacent triangles, which are backbone structures of the skeleton lines, describing the extending directions of the skeleton lines. Like Δ BCE in fig. 2, the advancing direction of the skeleton line is unique in the triangle type ii.

Class III triangles: there are two adjacent triangles, which are the intersections of the branches of the skeleton lines, and which are the starting points for stretching in 3 directions. As in fig. 2, Δ berg, extends in three directions at point L.

Respectively extracting central axes of the three types of triangles according to the following method, and connecting the central axes to form a skeleton line, wherein the common side of two adjacent triangles is called as an adjacent side:

class i triangle: connecting the midpoints of only adjacent edges with their corresponding vertices, such as segments AH, DJ, FK in FIG. 2;

class II triangles: connecting the midpoints of two adjacent edges, such as line IJ in FIG. 2;

class III triangles: connecting the center of gravity to the midpoints of the three sides, such as line segments LI, LK, LH in fig. 2.

In this embodiment of the present invention, step S302 is to set a width threshold, and compare the width of the patch with the width threshold, so as to identify a long and narrow patch. Referring to the technical specification of the geographical national situation general survey result graph, for the threshold definition of the width standard of the narrow and long pattern spots, a proportion scale of the graph is larger than 50 thousands (see table 1), and other proportion scales can be finely adjusted by referring to the index.

TABLE 1 narrow pattern spot Width criterion

In the invention, a specific identification mode of the long and narrow pattern spots is given, and the long and narrow pattern spots meeting the requirements can be screened out in a targeted manner by setting a threshold value, so that the calculation is more targeted.

In an embodiment, the step S103 of performing fine division on the regular grid based on the area and balance may specifically include the following steps:

step S401, calculating the average value of the areas of the long and narrow pattern spots as the optimum processing area;

step S402, taking the optimum processing area as a standard to split or merge the regular grids, so that the area of the narrow and long pattern spots to be processed in each grid is in a set range.

In the embodiment of the present invention, step S401 calculates an average value of the area sum of the narrow and long patches as an optimum processing area. Identifying m grids covered by the long and narrow pattern spots (taking the number n multiplied by n of the grids as an example, m is more than or equal to 0 and less than or equal to n²) And the average of the areas of the elongated patches within these meshes is taken as the optimum treatment area.

In this embodiment of the present invention, in step S402, the regular grids are split or merged using the optimum processing area as a standard, so that the area of the long and narrow patches to be processed in each grid is within a set range. For the fusion operation of mass image spots, the area of the narrow and long image spots in the grid is an influence meterHowever, since the narrow and long patches have non-uniform distribution characteristics in space, there is still a large difference in the areas of the narrow and long patches in the mesh formed according to the conventional regular mesh partition method, as shown in the block result diagram of the regular mesh shown in fig. 3(a), the mesh PA30 has the smallest area of the narrow and long patches of 0m²The grid PA02 has the largest narrow and long spot area 3143.22m²The difference between the two area values is large. The difference in the areas of the narrow and long pattern spots to be processed in the grid unit is not favorable for balancing the computational resources of the machine in the parallel processing process, resulting in a reduction in the overall processing efficiency.

In the invention, the areas of the image spots in each grid are approximately the same through splitting or merging the grids based on area balance, thereby balancing the occupation of computing resources in the parallel computing process and improving the processing efficiency.

As an optimization scheme of the previous embodiment, splitting the regular grid using the optimum processing area as a standard in step S402 may specifically include the following steps:

step S501, defining a splitting coefficient, and calculating the splitting coefficient of each grid according to the definition;

step S502, selecting all grids with the splitting coefficients larger than a set value, and arranging according to the splitting coefficients to form a splitting queue;

step S503, selecting the grid with the maximum splitting coefficient, calculating the coordinates of the middle point of the long edge of the grid, generating a boundary line parallel to the short edge based on the coordinates of the point, and splitting the grid into two sub-grids;

step S504, calculating the splitting coefficient of the sub-grid, if the splitting coefficient of the sub-grid is larger than the set value, adding the sub-grid into the splitting queue, and updating the splitting queue;

and repeating the steps S503 and S504 until all the grid splitting coefficients are smaller than the set value.

In this embodiment of the present invention, in step S501, a splitting coefficient is defined, and the splitting coefficient of each grid is calculated according to the definition. Still take n × n grids as an example: by twoAn integer variable i, j (i ═ 0, 1., n-1, j ═ 0, 1., n-1) identifies the row and column numbers of the grids, and the area of the narrow and long pattern Patch (PA) to be processed in each grid is calculated_ij) (ii) a Identifying m grids covered by the pattern spots (m is more than or equal to 0 and less than or equal to n)²) And taking the average value of the areas of the long and narrow pattern spots in the grids as the optimum Processing Area (PA);

in the embodiment of the present invention, a splitting coefficient f is defined, and each grid is split using the most suitable processing area as a standard, so as to achieve that the areas of the to-be-processed long and narrow patches in each grid are substantially consistent, and a mathematical function for calculating f may be:

for example, when f is more than or equal to 0.5 and less than or equal to 1.5, the area of the narrow and long pattern spot in the grid is proper, and the splitting treatment is not carried out; if f is larger than 1.5, the area of the narrow and long pattern spot in the grid is larger, and the narrow and long pattern spot needs to be split. It should be noted that the present embodiment is not limited to a specific application, but only an exemplary application; the method for calculating the splitting coefficient provided by the invention can be replaced by other forms, and the basic principle is to measure the closeness degree between the area of the pattern spot in each grid and the optimum processing area.

In the invention, the proximity degree of the image spot area in each grid and the optimum processing area can be measured by calculating the splitting coefficient, and when certain difference exists between the image spot area in each grid and the optimum processing area, the grid can be split to reduce the image spot area in a single grid, so that the method is suitable for grids with larger image spot areas.

As another optimization scheme of the previous embodiment, the step S402 of merging the regular grids with the optimum processing area as a standard may specifically include the following steps:

step S601, defining a merging coefficient, and calculating the merging coefficient of each grid according to the definition;

step S602, selecting all grids with the merging coefficients smaller than a set value, and arranging according to the size of the merging coefficients to form a merging queue;

step S603, selecting a mesh with the minimum merging coefficient, and merging the mesh with the smallest area of the long and narrow pattern patches in the adjacent meshes;

step S604, calculating a merging coefficient of the merged mesh, and if the merging coefficient of the merged mesh is smaller than the set value, adding the merged mesh to the merge queue, and updating the merge queue;

and repeating the steps S603 and S604 until all the grid merging coefficients are greater than the set value.

In this embodiment of the present invention, in step S501, a merging coefficient is defined, and a merging coefficient of each mesh is calculated according to the definition. Still take n × n grids as an example: marking the row number and the column number of the grid by two integer variables i, j (i is 0, 1.. multidot., n-1, j is 0, 1.. multidot., n-1), and calculating the area of a narrow and long pattern spot (PA) to be processed in each grid_ij) (ii) a Identifying m grids covered by the pattern spots (m is more than or equal to 0 and less than or equal to n)²) And taking the average value of the areas of the long and narrow pattern spots in the grids as the optimum Processing Area (PA);

in the embodiment of the present invention, a merging coefficient f is defined, and the most suitable processing area is used as a standard to merge the grids, so as to achieve that the areas of the to-be-processed long and narrow patches in each grid are substantially consistent, and a mathematical function for calculating f may be:

for example, when f is more than or equal to 0.5 and less than or equal to 1.5, the area of the narrow and long pattern spots in the grid is proper and is not subjected to merging treatment; if f is more than or equal to 0 and less than 0.5, the area of the narrow and long pattern spots in the grid is small, and the narrow and long pattern spots need to be combined. It should be noted that the present embodiment is not limited to a specific application, but only an exemplary application; the method for calculating the merging coefficient provided by the invention can be replaced by other forms, and the basic principle is to measure the closeness degree between the area of the image spot in each grid and the optimum processing area. It should be noted that the definition of the splitting coefficient and the definition of the merging coefficient may be the same or different, and the present invention is not limited thereto.

In the invention, the degree of closeness between the area of the pattern spots in each grid and the optimum processing area can be measured by calculating the merging coefficient, and when the area of the pattern spots in each grid has a certain difference with the optimum processing area, the area of the pattern spots in a single grid can be increased by merging the grids, so that the method is suitable for the grids with smaller area of the pattern spots.

As another optimization of the previous embodiment, step S103 is to perform fine-partition on the mesh based on the area and balance, and then further includes: the method comprises the following steps of establishing topology and modifying the grid by combining boundary arc semantic information:

step S701, setting a buffer distance, and establishing a grid buffer area according to the buffer distance;

step S702, identifying a narrow and long pattern spot arc segment which is intersected with the grid and completely contained by the buffer area in the buffer area;

step S703, constructing a unified topological relation for the long and narrow pattern spots and the grid, and recording semantic information associated with each arc segment;

step S704, replacing the grid arc segment associated with the long and narrow pattern patch arc segment by the long and narrow pattern patch arc segment according to the topological relation and semantic information of the arc segment, and deleting the replaced grid arc segment;

step S705, updating the topological relation between the long and narrow pattern spot and the mesh.

In the embodiment of the invention, the fusion accuracy and stability are influenced by adding the fine-grained pattern spots at the boundary of the grid. In parallel computing, the influence of the partitioned grid on data is avoided as much as possible, and the computer is focused on the processing of the internal elements of the grid. However, when the region pattern spot set is segmented by adopting the regular grid segmentation method, some small fine-grained pattern spots are inevitably added around the segmented grid. As shown in fig. 3(b), the elongated pattern spots P are segmented at nodes O by mesh boundaries SL1, SL3, resulting in finely divided pattern spots P1, P2. The number of the newly added fine-crushing pattern spots is related to the grid division density, and the fine-crushing pattern spots are easier to generate when the grid division density is higher. These finely divided patches can cause the following two problems during the melting process: firstly, the pattern spots participate in the melting of the pattern spots because the widths of the pattern spots accord with the judgment condition of the long and narrow pattern spots, and for the fine and broken pattern spots generated by the long and narrow pattern spots, the melting result inevitably influences the shape and the ductility of a splitting line, so that the melting accuracy is reduced; and secondly, the newly added fine pattern spots have indefinite area, and in extreme cases, fine pattern spots with extremely small areas (almost 0) appear, and the extremely small pattern spots collapse in the melting process due to the fact that the splitting lines cannot be calculated, and the melting stability is damaged.

In the embodiment of the present invention, when the boundary of the block grid is modified, the value of the buffer width threshold D is very critical, and is usually based on the minimum visible length threshold of human eyes on the map (MULLER, 1987), and the value is generally 0.3 or 0.4mm on the target scale map.

In the embodiment of the invention, the topological relation is 'node-arc-polygon', that is, the relation information between polygons and arcs and between arcs and nodes is recorded and stored, and meanwhile, the boundary arc semantic information, including the information of arcs ID, the belonged land class, the land class number and the like, is recorded, so as to correct the boundary of the block grid.

The following description will be made by taking fig. 4(a) to 4(c) as an example. In fig. 4(a), a buffer of distance D is constructed with SL1 as a reference, and P1, P2 are within the buffer; in fig. 4(b), the arc segments a1 and a2 are two completely contained arc segments, and according to the semantic topology, the arc segments associated with the SL1 are replaced with a1 and a2, respectively, and the modified grid boundary is shown in fig. 4 (c).

In the invention, a grid correction method is further provided, and fine pattern spots generated at the intersection of the long and narrow pattern spots and the grid are eliminated, so that the problem that the melting process is influenced by grid division is solved, and the accuracy and stability of melting are improved

The process of the present invention and the advantages over the prior art are described below with reference to one embodiment.

In this embodiment, the general survey data of geographic national conditions of a certain place is taken as an example, and the raw data scale is 11 ten thousand, and the space range of the experimental area is 1825.594km²The total number of the pattern spots is 125779, the comprehensive target scale is 1:10 ten thousand, and the total number of the narrow pattern spots with the width smaller than 0.4mm is 395. The experimental environment is Microsoft Win 764-bit operating system, the CPU is Intel Core I7-3770, the single machine 8 Core 8 thread, the main frequency 3.2GHz, the memory 16GB and the solid state disk 1024 GB. FIG. 5 is a graph of raw experimental data for experiments performed in accordance with the present invention.

To verify the efficiency of the mesh refinement method proposed herein, the method herein is compared with the regular mesh blocking method, the quadtree hierarchical blocking method.

The method is characterized in that a regular grid dividing method is adopted, the size of a multi-component block grid of 5 multiplied by 5, 6 multiplied by 6 and the like is set for carrying out melting operation, the time used in the processes of grid blocking, image spot splitting and image spot reconstruction of each group of experiments is respectively counted, and the experiment result is shown in figure 6.

As can be seen from FIG. 6, the time spent in each set of experiments is distributed in an "inverted-clock" pattern. When the experimental area is treated as a whole (1 × 1), the melting operation cannot be completed due to the limitation of the memory capacity of a computer; when the block grid is 5 multiplied by 5, the time for melting the single grid is long, which results in long overall time for melting; when the number of grids is 16 × 16, the area of the narrow spot corresponding to the single grid with the least processing time is 141733.21m²(ii) a When the number of blocks is increased to 40 × 40, although the mode of the splitting time of a single grid is reduced to 1s, the time consumption of the blocks is obviously increased.

In fig. 5, the distribution of the narrow and long pattern spots in the rectangular frame a is relatively uniform, and the narrow and long pattern spots are respectively processed by adopting a regular grid blocking method, a quadtree hierarchical blocking method and a grid fine-dividing method herein, and the results are shown in fig. 7(a) to 7 (c).

The melting efficiency of the region of different blocking methods is counted, as shown in table 2.

TABLE 2 comparison of melting operation efficiency based on three different blocking methods

From fig. 7(a) to fig. 7(c) and table 2, it can be seen that the results of the three blocking methods are the same for the region where the distribution of the narrow and long spots is relatively uniform. In addition, the maximum interval of the melting time of a single grid is only 0.48s, and the blocking time required by the quad-tree grid blocking method and the method is slightly higher than that required by the regular grid blocking method, because the two methods judge the area value of the narrow and long pattern spot in the grid, and the three blocking methods are basically consistent when the three blocking methods are used for melting the region and are not enough for 15 s.

In fig. 5, the narrow and long pattern spots in the rectangular frame B are distributed in the band from top left to bottom right, and the narrow and long pattern spots around the narrow and long pattern spots are sparse and are in an unbalanced state as a whole. Fig. 8(a) to 8(c) show the results of the blocking process performed by the three methods: fig. 8(a) is a schematic diagram of the segmentation results of a regular grid, fig. 8(b) is a schematic diagram of the segmentation results of a quadtree grid, and fig. 8(c) is a schematic diagram of the segmentation results of the method herein.

The melting efficiency of the region in different blocking methods is counted, as shown in table 3.

TABLE 3 comparison of melting operation efficiency based on three different chunking methods

As can be seen from fig. 8(a) to 8(c) and table 3, for a narrow and long pattern spot distribution imbalance region, the difference of the results obtained by the three blocking methods is large, both the regular grid and the quad-tree grid blocking methods have blank grids without any pattern spots inside, both the text method and the quad-tree grid blocking method subdivide grids with large density, except that the text method can merge grids with small internal pattern spot areas, the number of the grids is only 26, and the number of the grids is the smallest among the three blocking methods. In addition, the maximum melting time of a single grid in the method is 3.36s, which is consistent with the maximum melting time of the single grid in the method of partitioning the quadtree grid, but the time is shortened by more than 1 time compared with the regular method of partitioning the grid. In terms of total time consumption, the time consumed by the method in all the melting process and the splicing process is lower than that of the other two methods, namely 40% of the total time consumed by the regular grid partitioning method and 83% of the total time consumed by the quadtree grid partitioning method.

Also taking the data of fig. 5 as an example, the rationality of the block boundary correction is verified. Setting the buffer width threshold value D to 0.4mm, 133 small fine-crushing patches newly added due to boundary segmentation are identified in total, and fig. 9(a) and 10(a) are two typical small fine-crushing patch examples. Among them, FIG. 9(a) shows a very small pattern spot formed by boundary division, and its area is only 0.01m²Fig. 10(a) shows a typical fine small pattern spot formed by boundary segmentation.

As can be seen from fig. 9(a), the boundary segmentation may locally form extremely small patches with a sufficiently small area, and if the fusion operation is directly performed without processing these extremely small patches, the splitting lines cannot be calculated, which may easily cause a comprehensive collapse, and affect the fusion process. Fig. 9(b) is a schematic diagram of the result of the boundary correction according to the method of the present disclosure, and it can be found that the corrected boundary better eliminates the extremely small speckle at the boundary and is beneficial to obtain the correct long and narrow speckle melting result, as shown in fig. 9 (c).

As can be seen from fig. 10(b), the finely divided small pattern spots formed by boundary segmentation will continue to participate in the melting of the pattern spots due to the matching of the determination condition of the long and narrow pattern spots, resulting in a significant change in the shape of the splitting line at the position, and the shape of the main body of the long and narrow pattern spots cannot be accurately reflected. Fig. 10(c) is a schematic diagram of the result of performing boundary correction according to the method in this document, and it can be found that the corrected boundary better eliminates the fine small image spots at the boundary, effectively avoids the influence of the image spots on the melting operation, and ensures the quality of the image spots melting, as shown in fig. 10 (d).

As shown in fig. 11, in an embodiment, an elongated patch blocking device is provided, which may specifically include:

the data acquisition and decomposition module 1101 is configured to acquire patch data, and divide a regular grid to decompose the patch data into a plurality of sub-data sets;

a long and narrow pattern spot identification module 1102, configured to identify a long and narrow pattern spot in the sub data set, and calculate an area sum of the long and narrow pattern spot in each sub data set respectively;

a narrow and long pattern spot dividing module 1103, configured to perform fine division on the regular grid based on the area and balance, so as to complete the blocking of the narrow and long pattern spots.

In this embodiment of the present invention, the module 1101 is configured to obtain the patch data, and divide the patch data into a plurality of sub-data sets by using a regular grid. The data is spot data input by a user, such as vector full-coverage spot data. The regular grid refers to grids having regular shapes such as rectangles and triangles, and the invention is described by taking a rectangle as an example. The invention introduces a blocking strategy, the core of the blocking strategy is to divide mass map data into data subsets with smaller areas, and then each data subset is processed in parallel, so that the comprehensive efficiency can be improved on the basis of fully utilizing the computing capacity of a machine.

In this embodiment of the present invention, the module 1102 is configured to identify a long and narrow pattern patch in the sub data set, and calculate an area sum of the long and narrow pattern patches in each sub data set respectively. The narrow and long pattern spots refer to some long and narrow objects in the pattern spots, such as a narrow and long planar river, a low-level planar road, a highway, a field ridge, a ditch and the like, and the narrow and long pattern spots usually connect a plurality of different types of pattern spots of the ground objects, and have an important role in maintaining topological connectivity of the pattern spots of the ground objects. When the scale is small, the narrow and long pattern spot is reduced in dimension from a two-dimensional planar feature to a one-dimensional linear feature due to the small width.

In this embodiment of the present invention, the module 1103 is configured to perform fine division on the regular grid based on the area and balance, and complete the blocking of the long and narrow patches. In the present invention, the area sum balance means that the areas of the elongated patches included in different grids are substantially the same and are close to the average value of the areas of the elongated patches included in the grids. Therefore, the calculation amount of each grid is basically consistent when the computer performs parallel processing on the data in each grid.

According to the narrow and long pattern blocking device provided by the embodiment of the invention, the obtained pattern data is divided to obtain the sub data sets, the narrow and long patterns in the sub data sets are identified, and each grid is finely divided based on the area and balance of the narrow and long patterns in each sub data set, so that the narrow and long patterns and the blocking are completed. The invention finely divides the grids according to the area and balance, ensures that the area sum of the long and narrow pattern spots in each grid falls within a set range, is suitable for parallel calculation, is favorable for load balance of a computer, can improve the calculation efficiency during calculation of large data volume, saves the calculation resources, prevents program collapse caused by insufficient memory of the computer during calculation, and ensures the stability of data calculation.

In an embodiment, the data obtaining and decomposing module 1101 is configured to divide a regular grid to decompose the blob data into a plurality of sub-data sets, and specifically includes:

calculating the minimum circumscribed rectangle of the pattern spot area;

calculating equidistant segmentation points of the minimum circumscribed rectangle according to the set row number and the set column number of the regular grid;

and generating the regular grid which is parallel to the coordinate axis of the partition point and is not overlapped with the coordinate axis of the partition point according to the equal-interval partition points to obtain a plurality of subdata sets.

In the embodiment of the present invention, a Minimum Bounding Rectangle (MBR) refers to a rectangle that surrounds a geometric body, has a boundary parallel to a coordinate axis, and has a minimum area, and the minimum bounding rectangle can be calculated by calculating coordinates of a lower left corner point and an upper right corner point of a region of a pattern spot, or coordinates of a lower right corner point and an upper left corner point.

In the embodiment of the present invention, the number of rows and columns of the grid needs to be set in advance, it should be noted that the number of rows and columns of the grid preset will affect the average value of the area of the narrow and long patches in the grid, and the present invention implements fine division based on the balance of the values, so the number of rows and columns should be suitable, for example, considering the amount of parallel processing from the computer, considering the total area of the narrow and long patches, and the like. The specific method comprises the following steps:

calculating the minimum circumscribed rectangle according to the spatial distribution range of the pattern spots, and setting multiple groups of initial row and column numbers n₁、n₂、…、n_mEquidistant partition of MBR length and widthForm n₁×n₁、n₂×n₂、…、n_m×n_mThe multiple regular grids are divided into scales, the fusion calculation time under each grid scale is respectively counted, the grid size with the optimal fusion efficiency is used as the optimum grid size of the region, and the row and column number is determined. Of course, n can also be examined according to the specific distribution of the pattern spots₁×n₂、n₂×n₁And the like, and the above combinations are for illustration only.

In the embodiment of the invention, the coordinate axis is a coordinate axis in a Cartesian coordinate system, the horizontal axis is in the east-west direction, and the vertical axis is in the north-south direction. The division points determine the number of rows and columns of the grid boundary, and the coordinate axis determines the direction of the grid boundary.

In an embodiment, the long and narrow spot identification module 1102 is configured to identify a long and narrow spot in the sub data set, and specifically includes:

calculating the width of the pattern spot;

setting a width threshold value, and comparing the width of the image spot with the width threshold value so as to identify the long and narrow image spot.

W＝S/BL (1)

wherein W is the approximate average width of the image spot, S is the area of the image spot, and BL is the longest skeleton line of the image spot.

In an embodiment of the present invention, the long and narrow spot identification module 1102 is configured to set a width threshold, and compare the width of the spot with the width threshold to identify the long and narrow spot. Referring to the technical specification of the geographical national situation general survey result graph, for the threshold definition of the width standard of the narrow and long pattern spots, a proportion scale of the graph is larger than 50 thousands (see table 1), and other proportion scales can be finely adjusted by referring to the index.

In an embodiment, the narrow and long pattern patch dividing module 1103 is specifically configured to:

calculating an average value of the area of the long and narrow pattern spots from the area sum as an optimum processing area;

and splitting or merging the regular grids by taking the optimal processing area as a standard, so that the area of the narrow and long pattern spots to be processed in each grid is in a set range.

In the embodiment of the present invention, the average value of the area of the slit pattern is calculated from the area sum as the optimum processing area. Identifying m grids covered by the long and narrow pattern spots (taking the number n multiplied by n of the grids as an example, m is more than or equal to 0 and less than or equal to n²) And the average of the areas of the elongated patches within these meshes is taken as the optimum treatment area.

In the embodiment of the invention, the regular grids are split or combined by taking the optimum processing area as a standard, so that the area of the narrow and long pattern spots to be processed in each grid is in a set range. For the fusion operation of massive image spots, the area of the elongated image spots in the grid is the main factor affecting the calculation efficiency, however, since the elongated image spots present non-uniform distribution characteristics in space, there is still a large difference in the area of the elongated image spots in the grid formed according to the existing regular grid dividing method, as shown in fig. 3(a), the regular grid blocking result shows that the area of the elongated image spots in the grid PA30 is 0m, which is the smallest, and the area of the elongated image spots is 0m²The grid PA02 has the largest narrow and long spot area 3143.22m²The difference between the two area values is large. The difference in the areas of the narrow and long pattern spots to be processed in the grid unit is not favorable for balancing the computational resources of the machine in the parallel processing process, resulting in a reduction in the overall processing efficiency.

As an optimization scheme of the previous embodiment, the splitting the regular grid using the optimum processing area as a standard specifically includes:

defining a splitting coefficient, and calculating the splitting coefficient of each grid according to the definition;

selecting all grids with the splitting coefficients larger than a set value, and arranging according to the splitting coefficients to form a splitting queue;

selecting the grid with the maximum splitting coefficient, calculating the coordinates of the middle points of the long edges of the grid, generating a boundary line parallel to the short edges based on the coordinates of the points, and splitting the grid into two sub-grids;

calculating the splitting coefficient of the sub-grid, if the splitting coefficient of the sub-grid is larger than the set value, adding the sub-grid into the splitting queue, and updating the splitting queue;

and (4) repeating the steps (3) and (4) until all the grid splitting coefficients are smaller than the set value.

In the embodiment of the invention, the splitting coefficient is defined, and the splitting coefficient of each grid is calculated according to the definition. Still take n × n grids as an example: marking the row number and the column number of the grid by two integer variables i, j (i is 0, 1.. multidot., n-1, j is 0, 1.. multidot., n-1), and calculating the area of the narrow and long pattern spot (Patch area, PA) to be processed in each grid_ij) (ii) a Identifying m grids covered by the pattern spots (m is more than or equal to 0 and less than or equal to n)²) And taking the average value of the areas of the long and narrow pattern spots in the grids as the optimum Processing Area (PA);

As another optimization scheme of the previous embodiment, the merging the regular grids with the optimum processing area as a standard specifically includes:

defining a merging coefficient, and calculating the merging coefficient of each grid according to the definition;

selecting all grids with the merging coefficients smaller than a set value, and arranging according to the size of the merging coefficients to form a merging queue;

selecting the grid with the minimum merging coefficient, and merging the grid with the narrow and long pattern spot area and the minimum grid in the adjacent grids;

calculating the merging coefficient of the merged grid, if the merging coefficient of the merged grid is smaller than the set value, adding the merged grid into the merging queue, and updating the merging queue;

and repeating the steps 3 and 4 until all grid combination coefficients are larger than the set value.

In the embodiment of the present invention, the merging coefficients are defined, and the merging coefficients of each mesh are calculated according to the definitions. Still take n × n grids as an example: marking the row number and the column number of the grid by two integer variables i, j (i is 0, 1.. multidot., n-1, j is 0, 1.. multidot., n-1), and calculating the area of the narrow and long pattern spot (Patch area, PA) to be processed in each grid_ij) (ii) a Identifying m grids covered by the pattern spots (m is more than or equal to 0 and less than or equal to n)²) And taking the average value of the areas of the long and narrow pattern spots in the grids as the optimum Processing Area (PA);

As a further optimization scheme of the previous embodiment, the apparatus further includes a grid optimization module, which is specifically configured to:

setting a buffer distance, and establishing a grid buffer area according to the buffer distance;

identifying an elongate patch arc segment within the buffer that intersects the grid and is completely contained by the buffer;

constructing a uniform topological relation for the long and narrow pattern spots and the grids, and recording semantic information associated with each arc segment;

replacing the grid arc segment associated with the long and narrow pattern spot arc segment by the long and narrow pattern spot arc segment according to the topological relation and semantic information of the arc segment, and deleting the replaced grid arc segment;

and updating the topological relation between the long and narrow pattern spots and the grid.

The following description will be made by taking fig. 4(a) to 4(b) as an example. In fig. 4(a), a buffer of distance D is constructed with SL1 as a reference, and P1, P2 are within the buffer; in fig. 4(b), the arc segments a1 and a2 are two completely contained arc segments, and according to the semantic topology, the arc segments associated with the SL1 are replaced with a1 and a2, respectively, and the modified grid boundary is shown in fig. 4 (c).

FIG. 12 is a diagram illustrating an internal structure of a computer device in one embodiment. As shown in fig. 12, the computer apparatus includes a processor, a memory, a network interface, an input device, and a display screen connected through a system bus. Wherein the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program that, when executed by a processor, causes the processor to implement the xx method. The internal memory may also have stored therein a computer program that, when executed by the processor, causes the processor to perform the xx method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.

Those skilled in the art will appreciate that the architecture shown in fig. 12 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a narrow pattern patch blocking apparatus provided herein may be implemented in the form of a computer program that is executable on a computer device such as that shown in fig. 12. The memory of the computer device may store various program modules constituting the one type of narrow-band patch dividing apparatus, such as the data acquisition and decomposition module 1101, the narrow-band patch identification module 1102 and the narrow-band patch dividing module 1103 shown in fig. 11. The program modules constitute computer programs that cause the processor to execute the steps of a method for partitioning a narrow stripe pattern according to the embodiments of the present application described in the present specification.

For example, the computer device shown in fig. 12 may execute step S101 through the data acquisition and decomposition module 1101 in a long and narrow patch blocking apparatus shown in fig. 11; the computer device may perform step S102 through the long and narrow pattern recognition module 1102; the computer device may perform step S103 by the slit pattern dividing module 1103.

In one embodiment, a computer device is proposed, the computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:

In one embodiment, a computer readable storage medium is provided, having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the steps of:

It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in various embodiments may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a non-volatile computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the program is executed. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method of elongate patch blocking, the method comprising:

finely dividing and combining the regular grids based on the area sum balance to complete the blocking of the long and narrow pattern spots, and specifically, calculating the average value of the area of the long and narrow pattern spots as the optimum processing area;

2. A method as claimed in claim 1, wherein said partitioning rule grid decomposes said patch data into subdata sets, comprising the steps of: calculating the minimum circumscribed rectangle of the pattern spot area; calculating equidistant segmentation points of the minimum circumscribed rectangle according to the set row number and the set column number of the regular grid; and generating the regular grid which is parallel to the coordinate axis of the partition point and is not overlapped with the coordinate axis of the partition point according to the equal-interval partition points to obtain a plurality of subdata sets.

3. A method as claimed in claim 1, wherein said identifying the elongated patches in said subset of data comprises the steps of:

step 1: calculating the width of the pattern spot;

step 2: setting a width threshold value, and comparing the width of the image spot with the width threshold value so as to identify the long and narrow image spot.

4. A method for segmentation of an elongated pattern patch according to claim 1, wherein said splitting of said regular grid using said optimum processing area as a criterion comprises the steps of:

step 1: defining a splitting coefficient, and calculating the splitting coefficient of each grid according to the definition;

step 2: selecting all grids with the splitting coefficients larger than a set value, and arranging according to the splitting coefficients to form a splitting queue;

and step 3: selecting the grid with the maximum splitting coefficient, calculating the coordinates of the middle points of the long edges of the grid, generating a boundary line parallel to the short edges based on the coordinates of the points, and splitting the grid into two sub-grids;

and 4, step 4: calculating the splitting coefficient of the sub-grid, if the splitting coefficient of the sub-grid is larger than the set value, adding the sub-grid into the splitting queue, and updating the splitting queue;

5. A method for segmentation of an elongated pattern patch as claimed in claim 1, wherein said merging of said regular grid using said optimum processing area as a criterion comprises the steps of:

step 1: defining a merging coefficient, and calculating the merging coefficient of each grid according to the definition;

step 2: selecting all grids with the merging coefficients smaller than a set value, and arranging according to the size of the merging coefficients to form a merging queue;

and step 3: selecting the grid with the minimum merging coefficient, and merging the grid with the narrow and long pattern spot area and the minimum grid in the adjacent grids;

and 4, step 4: calculating the merging coefficient of the merged grid, if the merging coefficient of the merged grid is smaller than the set value, adding the merged grid into the merging queue, and updating the merging queue;

6. A method for partitioning an elongated patch as recited in claim 1, wherein said fine partitioning of said mesh based on said balance of area sums further comprises:

the method comprises the following steps of establishing topology and modifying the grid by combining boundary arc semantic information:

7. An elongate spot tiling apparatus, said apparatus comprising:

a long and narrow pattern spot identification module, configured to identify a long and narrow pattern spot in the sub data set, and calculate an area sum of the long and narrow pattern spot in each sub data set respectively; finely dividing the regular grid based on the area sum balance to complete the blocking of the long and narrow pattern spots, and specifically, calculating the average value of the area sum of the long and narrow pattern spots as the optimum processing area;

and the narrow and long pattern spot dividing module is used for splitting or merging the regular grids by taking the optimal processing area as a standard, so that the area of the narrow and long pattern spots to be processed in each grid is in a set range.

8. A computer device comprising a memory and a processor, the memory having stored therein a computer program that, when executed by the processor, causes the processor to perform the steps of a method of elongate patch blocking as claimed in any one of claims 1 to 6.

9. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, causes the processor to carry out the steps of a method of elongate patch blocking according to any of claims 1 to 6.