CN109643289A

CN109643289A - Low-power data for memory sub-system is transmitted

Info

Publication number: CN109643289A
Application number: CN201780051079.2A
Authority: CN
Inventors: J·徐; D·全; H-J·洛
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2016-08-22
Filing date: 2017-06-28
Publication date: 2019-04-16
Anticipated expiration: 2037-06-28
Also published as: TW201807590A; US10394724B2; CN113886292A; CN109643289B; US20180052785A1; WO2018038805A1

Abstract

Each system and method are related to reducing the power consumption of the data transmitting between processor and memory.The data to transmit on the data/address bus between processor and memory are checked to attempt to obtain the first data pattern, and if the first data pattern exists, the transmitting of the first data pattern on the data bus is suppressed.It is passed in the second bus between processor and memory on the contrary, corresponding to the first address of the first data pattern.First address is less than the first data pattern.The processor includes processor side first in first out (FIFO), and the memory includes memory side FIFO, wherein the first data pattern is present at the first address at the first address in the FIFO of processor side and in memory side FIFO.

Description

Low-power data for memory sub-system is transmitted

Open field

Disclosed various aspects are related to processing system.More specifically, each illustrative aspect is related to reducing processing system and depositing The power consumption of data transmitting between reservoir subsystem.

Background

Processing system may include assisting storage location, such as including the memory sub-system of main memory.It is big for having The main memory of memory capacity is realized, for example, the double data rate (DDR) (DDR) using dynamic random access memory (DRAM) technology is real Existing, memory sub-system can be realized outside piece, handle for example, being integrated into the one or more of access memory sub-system Device is integrated into processor chips thereon or the different storage core on piece of system on chip (SoC).Correspondingly, primary storage is accessed Device is related to transmitting data between memory sub-system and SoC, this associated cost for power consumption.

Power consumption in storage system is well-known a challenge.Have as is generally known in the art for reducing in memory Power consumption several technologies, such as voltage adjust.For example, by considering the low-power DDR for several generations or several versions (LPDDR) specified supply voltage can see a trend of voltage adjusting.Supply voltage VDD for LPDDR1 is 1.8V；Supply voltage VDD for LPDDR2 and LPDDR3 is 1.2V；Supply voltage VDD for LPDDR4 is 1.1V.So And for each generation (for example, LPDDR5 and later) in future, the range adjusted for further progress voltage is limited, Because if supply voltage persistently reduces, can it is observed that due to the input/output of memory periphery (IO) circuit system refreshing Performance degradation caused by the limitation that operation and performance are applied.Thus, times reached can be adjusted by further progress voltage What power efficiency gain may be offset by performance and degrading quality.

Correspondingly, the power efficiency existed in the art for improving existing and each generation in the future memory sub-system is same When the shortcomings that avoid the need for conventional methods (such as voltage adjusting).

It summarizes

Illustrative aspect of the invention is related to System and method.The data to transmit on the data/address bus between processor and memory are checked to attempt to obtain the first data mould Formula, and if the first data pattern exists, inhibit the transmitting of the first data pattern on the data bus.But it is handling Transmitting corresponds to the first address of the first data pattern in the second bus between device and memory.First address is less than the first number According to mode.The processor includes processor side first in first out (FIFO), and the memory includes memory side FIFO, wherein the One data pattern is present at the first address at the first address in the FIFO of processor side and in memory side FIFO.

For example, an illustrative aspect is related to a kind of method communicated in the processing system, this method comprises: determination is wanted The data transmitted on data/address bus between processor and memory have the first data pattern, and the first data pattern is inhibited to exist Transmitting corresponds to the first data in transmitting on the data/address bus, and the second bus between the processor and the memory First address of mode.

It is related to a kind of equipment in terms of another exemplary, including processor, memory and in the processor and the memory Between data/address bus.Data pattern examiner, which is configured to determine the data to transmit on the data bus, has the first data Mode and transmitting and second bus of first data pattern on the data/address bus is inhibited to be configured in the processor Transmitting corresponds to the first address of the first data pattern between the memory.

Another illustrative aspect is related to a kind of equipment, including for determination will data between processor and memory it is total The data transmitted on line have the device of the first data pattern, for inhibiting the biography of first data pattern on the data/address bus The device passed, and transmitting corresponds to first data pattern in the second bus between the processor and the memory The first address device.

Another illustrative aspect is related to a kind of processing system, which includes the on piece comprising at least one processor System (SoC)；Storage memory package comprising at least one storage memory dice；Between SoC and storage memory package Storage memory link；Write data time pattern examiner, be configured to determine will SoC and storage memory package it Between storage memory link transmission link on the data transmitted there is the first data pattern and inhibit the first data mould Transmitting of the formula on the transmission link；And the first storage memory interface of SoC, it is configured to transmit on transmission link The first address corresponding to first data pattern.

Brief description

Attached drawing is provided to help that each aspect of the present invention is described, and provide attached drawing be only used for explain various aspects rather than It is defined.

Fig. 1 illustrates a conventional processing systems.

Fig. 2A-E illustrates the realization of an example processing system of the illustrative aspect according to the disclosure.

The timing diagram for the processing system that Fig. 3-4 illustrates each illustrative aspect according to the disclosure to configure.

The Memory Controller for the processing system that Fig. 5 illustrates each illustrative aspect according to the disclosure to configure.

Fig. 6, which is illustrated, is related to the flow chart of write operation according to each illustrative aspect of the disclosure.

Fig. 7, which is illustrated, is related to the flow chart of read operation according to each illustrative aspect of the disclosure.

Fig. 8, which is illustrated, is related to the flow chart of communication means according to each illustrative aspect of the disclosure.

Fig. 9 is that show wherein can be advantageously with the block diagram of the example wireless communications of the aspects of the disclosure.

Detailed description

Below for specific aspect of the invention description and related attached drawing in disclose each aspect of the present invention.It can structure Replaceability aspect is found out without departing from the scope of the present invention.In addition, well-known element will not be described in detail in the present invention Or it will be removed in order to avoid falling into oblivion correlative detail of the invention.

Wording " exemplary " is used herein to mean that " being used as example, example or explanation ".Here depicted as " example Any aspect of property " is not necessarily to be construed as preferred or advantageous over other aspects.Similarly, term " aspects of the present invention " and should not Seeking all aspects of the invention all includes discussed feature, advantage or operation mode.

The term as used herein is the purpose merely for description particular aspects, and is not intended to limitation aspects of the present invention. As it is used herein, " one " of singular, " certain " and "the" are intended to also include plural form, it is clear unless the context otherwise Instruction.It will also be understood that term " includes ", " having ", "comprising" and/or " containing " indicate stated spy as used herein Sign, integer, step, operation, the presence of element, and/or component, but one or more other features, integer, step are not precluded Suddenly, the presence or addition of operation, element, component and/or its group.

In addition, many aspects describe in the form of by the action sequence executed by the element for for example calculating equipment.It will recognize Know, various movements described herein can by special circuit (for example, specific integrated circuit (ASIC)), by just one or more The program instruction or executed by combination of the two that processor executes.In addition, these action sequences described herein can be recognized To be to be embodied in any type of computer readable storage medium completely, be stored with once execute will just make it is associated The corresponding computer instruction set of processor execution functionality described here.Various aspects of the invention can use number as a result, Different forms is planted to embody, all these forms have all been contemplated to fall in the range of subject content claimed.Separately Outside, for each aspect described herein, the corresponding form of any such aspect can be described herein as example " matching It is set to and executes the described logic acted ".

Each illustrative aspect of the disclosure is related to reducing the power consumption of memory in processing system.It recognizes, memory subsystem Power consumption in system to and from the data volume that memory sub-system is transmitted with increasing.Thus, in each illustrative aspect In, data traffic is lowered to reduce power consumption.For example, on data/address bus between SoC and memory sub-system there may be The repeated data mode transmitted back and forth.Such repeated data mode can be identified and be stored in SoC and memory In one or more buffers in subsystem.When the repeated data mode of storage in a buffer will be passed on the data bus When passing, address related with the data pattern can be only sent, and the transmitting of the data pattern itself can be inhibited.Each Illustrative aspect, compared with data pattern itself, address consumes less bandwidth, and therefore data traffic is reduced, thus Reduce power consumption.These and related aspect are further illustrated with reference to attached drawing below.

In Fig. 1, the conventional processing systems 100 with SoC 120 and memory sub-system 130 are illustrated.SoC120 can Including one or more processing elements, for the needs of exemplary explanation, processing element 104a-c therein is typically shown It is out digital signal processor (DSP) 104a, general processor (GPU) and media engine 104b, multicore central processing unit (CPU) 104c etc..Processing element 104a-c can be connected to Memory Controller by interface (such as system bus 106) 108.Processing element 104a-c can make the request to one or more memory groups 116 in access memory sub-system 130, And Memory Controller 108 controls these access requests.For example, queuing mechanism may be implemented in Memory Controller 108, arbitration Technology etc. is deposited with being selectively allowed for the one or more received from processing element 104a-c to request access to based on available bandwidth Reservoir subsystem 130.For purposes of brevity, it may be present in one between processing element 104a-c and Memory Controller 108 Grade or multilevel cache have been not shown, but model of each cache without influencing the disclosure can be realized according to routine techniques It encloses.

The memory access of memory sub-system 130 can be related to be integrated in from SoC 120 and be connected on SoC 120 respectively The memory interface 110 (for example, input/output pin or other relevant interfaces) of a bus.In one arrangement, bus 112a-b is shown as two-way or BDB Bi-directional Data Bus, and the order that bus 114 is shown as to carry address, clock etc. is total Line.

Data are write or stored with operation, to be written into the data of any memory group 116 by such as processing element 104a- One of c is provided, once and Memory Controller 108 grant write operation, then in the memory interface 110 from SoC 120 The upper data that carry of one or both of bus 112a-b are correspondingly in one or more I/O blocks of memory sub-system 130 It is received at 113a-b.The order (C) of data write operation, address (A) and clock (CLK) are supplied by CA in bus 114 It is received with CLK block 115.Data are passed to decoder and data latches 118 from I/O block 113a-b, data from decoder and Data latches 118 are passed to the address that the data will be written into just suitable memory group 116 (received from block 115).

Data are read or loaded with operation, is stored by controller in the read request from one of processing element 104a-c After 108 grant to the access of memory sub-system 130, read request, read address and clock can be supplied in bus 114 It answers, is received at the block 115 of memory sub-system 130, and by the use to block 118, the correspondence number from read address According to can be read from one of memory group 116, and it is supplied by block 118 and returns to one or more I/O block 113a-b.From I/O block 113a-b, read data can be provided to the memory interface 110 of SoC 120 on bus 112a-b, and Then it is ultimately transferred to requestor processes element 104a-c.

In both data write operation and read operation, as discussed above, bus 112a-b can be carried by block or n-bit Unit-sized meter data (for example, 8DQ number of 16 or 128 bit lengths is burst).It observes, at two of data transmitting In direction, i.e., for the write and read on bus 112a-b, the most data packets transmitted include repeat pattern.For example, without pressure The image data (for example, items 104a-c is used to carry out image procossing) of contracting may include the bulk weight comprising full 0 or complete 1 Multiple bit mode.However, in conventional processing systems 100, for example corresponding read/write command institute of the appearance each time of repetition bits mode It is passed like that regulation, which results in corresponding power consumptions.

In each illustrative aspect, it is understood that the transmitting of repeated data mode can be avoided by, and be transferred to repeated data Can replace is passed the indicator (it can be the size or bit width more much smaller than data pattern itself) of mode To save power consumption.The data that disclosing will transmit on the data/address bus between SoC and memory for determination include repeat number According to mode and inhibit the example technique of the transmitting of the repeated data mode on the data/address bus.It can be used one or more A buffer or first in first out (FIFO) structure and to transmit include on different bus between SoC and memory in FIFO The destination address of repeated data mode supplies the indicator of repeated data mode.All aspects of this disclosure are referring now to figure Processing system 200-280 shown in 2A-E illustrates.

Although it is appreciated that using being related to certain specific memory technologies in the description of the illustrative aspect in Fig. 2A-E Term, but this is intended merely to facilitate the purpose of explanation, and it is not intended as the exemplary side of any specific memory technology The limitation in face.For example, Fig. 2A-D illustrates the configuration of memory sub-system 230 comprising set according to any memory technology The memory group 216 of meter, memory technology include main memory technology, are such as marked by electronic component industry federation (JEDEC) The technology that standard is covered, DRAM, synchronous dram (SDRAM), DDR3, DDR4 etc. and each generation movement by JEDEC covering Memory technology, including low-power DDR (LPDDR) technology, such as LPDDR, LPDDR1, LPDDR2, LPDDR3, LPDDR4, LPDDR5 etc..In addition, as 2E is explained, illustrative aspect can also be equally applicable to be covered by JEDEC various existing and The flash memory technology in each generation in the future, for example, solid state drive (SSD) memory, Common Flash Memory (UFS), embedded multi-media card (eMMC) etc..

Correspondingly, A first refering to fig. 2, illustrates an example processing system 200.Processing system 200 has and processing system Certain similarities of system 100, and therefore will avoid for clarity to the detailed of the similar aspect of processing system 100 and 200 It repeats to the greatest extent.For example, processing element 204a-b, system bus 206 and the memory of SoC 220 connects in processing system 200 Mouth 210；Bus 212a-b and 214；And I/O block 213a-b, CA and CLK block 215 of memory sub-system 230, decoder sum number It can be similarly configured as the similar assembly of processing system 100 according to latch 218 and memory group 216.Although by It is referred to as SoC 220 and memory sub-system 230, but the two components can be any processor and memory respectively, regardless of They are integrated on the same chip still on different chips (for example, each illustrative aspect can be equally applicable to processing The inhibition of data transmitting on any data/address bus between device and memory).

The difference with processing system 100 is focused on, the Memory Controller 208 of processing system 200 has for dropping The supplementary features of the power consumption of data transmitting between low SoC 220 and memory sub-system 230, will be described now. As shown, Memory Controller 208 includes block 242a-c, is typically shown as writing data FIFO 242a, writes data Time mode detector 242b and write data FIFO policy management 242c.In addition, memory sub-system 230 further includes being shown It is out the extra block for writing data FIFO 252a-b, their example implementation will discuss in more detail with reference to Fig. 5.

If streaming is by any data traffic of Memory Controller 208 as the time is with data pattern repeatability Characteristic then writes data time pattern examiner 242b and is configured to whether pattern data detection is repeated, such as, if it is matched with Write the data pattern stored in data FIFO 242a.It fills and updates storage and writing the repeated data mould in data FIFO 242a Formula can be managed by writing data FIFO policy management 242c.It writes in data FIFO 242a if writing Data Matching in being stored in Data pattern at specific fifo address (also referred to as label) then writes matching (or hit) entry of data FIFO 242a Label is retrieved.Repeated data mode is also stored on the identical mark of memory sub-system 230 write in data FIFO 252a-b At label, they are shown as close to I/O block 213a-b or communicate with I/O block 213a-b.Two be separately depicted write data FIFO 252a-b is only an example implementation, and it is all to write data that two of them, which write each of data FIFO 252a-b, The half size of the word of FIFO 242b and saving write the word of data FIFO 242b half (e.g., including be stored in storage The top half of the word of the repeated data mode in the first address for writing data FIFO 242a in device controller 208 can be by It is stored at identical first address write in data FIFO 252b, and the lower half portion of word can be stored in and write data At the first address in FIFO 252b).In other implementations, the two write data FIFO 252a-b can by with write data FIFO 242a same word size individually writes data FIFO to replace.

Correspondingly, if include write data write data flow write data time pattern examiner 242b be detected as have That matches is stored in the write data mode write in data FIFO 242a, then Memory Controller 208 (or SoC 220 any other Logic or block) inhibit transmitting of the write data mode on bus 212a-b.It replaces, Memory Controller 208 is in bus The write data mode is sent on 214 be stored in write label locating for data FIFO 242a.As by with reference to Fig. 5 come discussing, should Label and write data mode (may be to want several big magnitudes, such as 128 bits) are much smaller compared to size (for example, being directed toward Save the several bits for writing the index of data FIFO 242a).

At memory sub-system 230, block 215 receives the label, together with relevant order to indicate that the label is to be directed to Be stored in the repeated data mode in data FIFO 252a-b of writing and the repeated data mode to be written into memory group Write address in 216.Write data mode is read from position pointed by the label in data FIFO 252b is write, and is passed through The use of decoder and data latches 218 is passed to the correspondence write address in memory group 216.In one example, number is write Internal signal or order can be used to execute from the transmitting for writing data FIFO 252b to memory group 216 according to mode, such as exist " the writing data duplication " from write address and label generated in memory sub-system 230.

Referring now to Fig. 2 B, in terms of a replacement is illustrated in example processing system 250, processing system 250 is in many Aspect is similar with processing system 200, as shown by the use of identical reference label.Focus on the area with processing system 200 Not, in processing system 250, data FIFO 252a-b is write with the replacement of data FIFO 254 is write, data FIFO 254 is write and is present in (as shown, each memory group 116 can have it in the decoder and 218 pieces of data latches of each memory group 116 Oneself associated decoder and data latches 218).If the power consumption of memory sub-system 230 is based on dry ingredients or factor, all If I/O interface power (for example, being consumed by I/O block 213), internal bus power are (for example, be used in I/O block 213a-b and storage Transmitted consumed by data between device group 216) and group operation power (for example, for read/writable memory device group 216).Pass through Repositioning writes data FIFO 254 (for example, the data FIFO 252a-b that writes from Fig. 2A close to I/O block 213a-b is deposited to each 218 pieces of the decoder and data latches of reservoir group 216), the internal bus power consumption of memory sub-system 230 can be lowered. With the figure writing data FIFO 252a-b be passed to memory group 216 of the wherein n-bit write data mode from I/O block 213a-b 2A is on the contrary, in fig. 2b, write data mould from the n-bit for writing data FIFO 252a-b to memory group 216 from I/O block 213a-b Formula transmitting can be avoided by.It replaces, internal storage signal is (such as according to raw by the received write order of block 215 and label At " write data duplication ") can be used for significantly reduced power consumption from being stored in decoder and data latches 218 Data FIFO 254 is write to retrieve write data mode and write direct corresponding memory group 216.

Referring now to Fig. 2 C, in terms of another replacement is illustrated in example processing system 250, processing system 250 is being permitted It is many-sided similar with processing system 200, as shown by the use of identical reference label.Focus on processing system 200 and 250 difference, processing system 260 include for inhibiting for example either on bus 212a-b to for read operation and writing behaviour Make the technology of the transmitting of the repeated data mode of the two.It is appreciated that although being solved in conjunction with various aspects related with write operation It says, but can also include place independently of the various aspects for the transmitting for inhibiting to repeat write data mode (for example, in processing system 200) Inhibit duplicate reading according to the various aspects of the transmitting of mode in reason system 260.Inhibit duplicate reading that can lead as follows according to the transmitting of mode It causes to save memory power.Correspondingly, in processing system 260, memory sub-system 230 includes each functional block, they are solved Say and be, for example, be disposed close to or close to I/O block 213a-b and be configured to detect any duplicate reading according to mode (such as It is corresponding to write the data pattern in data FIFO 252a-b with matching entry) read data pattern check 262a-b.If reading behaviour The data patterns match of work is in being stored in the data pattern write in data FIFO 252a-b, then for example on backward channel 264 only Only the transmitting direction matched data mode is present in the label for writing the entry of position in data FIFO 252a-b, the backward channel 264 can be a part of the independent bus or one of bus 212a-b from memory sub-system 230 to SoC 220.It is corresponding It reads data and is not passed to SoC 220 from memory sub-system 230 on such as bus 212a-b.It is connect on backward channel 264 When receiving the label, Memory Controller 208 in SoC 220 can write data FIFO 242a pointed by the label Entry read corresponding data mode data.As previously mentioned, remaining aspect for writing data path can be as example located Reason system 200 is similarly configured like that.

Referring now to Figure 2 D, processing system 270 is being permitted in terms of illustrating another replacement in example processing system 270 It is many-sided similar with the processing system 250 of Fig. 2 B, as shown by the use of identical reference label.It focuses on and processing system 200 and 250 difference, similar to the processing system 260 of Fig. 2 C, the processing system 270 of Fig. 2 D further includes for inhibiting for example to exist To the technology of the transmitting of the repeated data mode for both read and write operations either on bus 212a-b, although further It is secondary, it is noted that the various aspects of the transmitting of write data mode can be repeated independently of inhibition (for example, handling in some cases In system 250) and including inhibiting duplicate reading according to the various aspects of the transmitting of mode in processing system 270.Inhibit duplicate reading evidence The transmitting of mode for example can cause further to deposit and further decreasing the internal bus power of processing system 250 of Fig. 2 B Reservoir power is saved.In processing system 270, in the decoder and data latches 218 of each memory group 216, it will read Data pattern examiner 272 is placed together with data FIFO 254 is write.Although such as in the processing system 260 of Fig. 2 C, n-bit Reading data may be passed to from memory group 216 in inside and I/O block 213a-b and write data FIFO 252a-b immediately The read data pattern detector 262a-b of placement is matched with determining whether there is, and on the other hand in processing system 270, this Transmitting can be avoided by the internal bus power to save in memory sub-system 230 inside n-bit.On the contrary, read data pattern Detector 272 from data that memory group 216 is read and can will be stored in decoder and data latches 218 and write data Data pattern in FIFO 254 is made comparisons, and if there is matching, then can be for including writing in data FIFO 254 The tag entry of matched data mode generate internal signal bus (for example, " read fifo tag<0:i>(and read fifo label [3: 0])").The label can be sent via backward channel 264, the backward channel 264 can be from memory sub-system 230 to The bus of SoC 220.Corresponding reading data are not passed to SoC from memory sub-system 230 on such as bus 212a-b 220.When receiving the label on backward channel 264, the Memory Controller 208 in SoC 220 can be from the label institute The entry for writing data FIFO 242a being directed toward reads the data of corresponding data mode.As previously mentioned, data path is write Remaining aspect can be similarly configured as such as processing system 250.

With reference to Fig. 2 E, in terms of another replacement is illustrated in example processing system 280, processing system 280 is similar to upper The processing system 200,250,260 and 270 that text is discussed with reference to Fig. 2A-D, with some modifications to reflect that the possibility that can be made changes Example feature is extended to any memory technology.The similar aspect being retained in Fig. 2 E in Fig. 2A-D has been used identical Drawing reference numeral is shown, and will not be repeated again elaborate to similar characteristics for brevity.Focus on respectively with figure The difference of the processing system 200,250,260 and 270 of 2A-D, in Fig. 2 E, storage memory package 290 is shown to substitution figure Previously discussed memory sub-system 230 in 2A-D.In addition, the data/address bus 212a-b of Fig. 2A-D, command line 214 etc. are corresponding It is replaced by including the storage memory link of transmission (Tx) link 282 and reception (Rx) link 284 on ground.Also Fig. 2A-D is deposited Memory interface 210 make it is corresponding change to accommodate the above modification, and therefore memory interface 210 by the first storage interface Lai Substitution, is shown as storage memory interface 210 ', and from the angle of SoC 220, it is similar with the memory interface 210 of Fig. 2A-D Ground work, but manage in Tx link 282 up to the data of storage memory package 290 and control transmitting and in Rx link 284 The reception of upper data (and backward channel instruction under applicable circumstances).

Storage memory package 290 is considered in more detail, wherein various memory technologies can be supported, for example, being covered by JEDEC Existing and each generation in the future the flash memory technology of lid, for example, solid state drive (SSD) memory, Common Flash Memory (UFS), insertion Formula multimedia card (eMMC) etc..For example, the read/write interface to storage memory package 290 can be provided by physics (PHY) layer, Such as it is shown as the second storage memory interface of storage memory interface 292.The data that are received from Tx link 282 or Data to be delivered to Rx link 284 can correspondingly be provided to storage Memory Controller 294, may include reading data Pattern examiner 295 (similar to the read data pattern detector 272 of such as Fig. 2 D) and data FIFO is write (similar to for example scheming 2D's writes data FIFO 254).Storing memory dice 298 may include one or more memory arrays or memory group (class It is similar to the memory group 216 of such as Fig. 2 D).

Correspondingly, in the situation write, if writing data time mode by SoC 220 including the data flow of writing for writing data Detector 242b is detected as having the matching write data mode being stored in write in data FIFO 242a (for example, the first data mould Formula), then any other logic or block of storage the memory interface 210'(or SoC 220 of SoC 220) inhibit this to write data mould Transmitting of the formula on Tx link 282.It replaces, storage memory interface 210 ' sends this on Tx link 282 and writes data mould Formula stored label (for example, first address) in writing data FIFO 242a.At storage memory package 290, storage is deposited Memory interface 292 receives the label, together with relevant order to indicate that the label is to be directed to be stored in write in data FIFO 296 Repeated data mode and the repeated data mode to be written into storage memory dice 298 in write address.From writing number Write data mode is read according to position pointed by the label in FIFO 296, and passes it to storage memory dice 298 In correspondence write address.Correspondingly, the example adaptation at least based on the processing system 280 to above-mentioned Fig. 2 E, those skilled in the art Member will be understood that the modification that each illustrative aspect is fitted to any memory technology and can be made.

In the situation of reading, read data pattern detector 295 can by from the data that read of storage memory dice 298 with The data pattern write in data FIFO 296 is made comparisons, and if there is matching (for example, being directed to the second data pattern), then may be used Pass through storage memory with the tag entry (for example, second address) that will include the matched data mode in data FIFO 296 of writing Interface 292 and Rx link 284 are sent to the storage memory interface 210 ' of SoC 220.Corresponding reading data are not in such as bus SoC 220 is passed to from storage memory package 290 on Rx link 284.When receiving label on Rx link 284, SoC Storage memory interface 210 ' in 220 can be read from the entry pointed by the label in data FIFO 242a of writing of SoC 220 The data for taking corresponding data mode, as previously with reference to described in Fig. 2A-D.

Referring now to Fig. 3-4, by timing diagram related with the processing system 100 of Fig. 1 with the processing system with Fig. 2A-D The related timing diagram of 200-270 compare with explain according in the read operation and write operation of each illustrative aspect bus activity and Relevant power is saved.The true version of clock for each bus activity and mending are originally illustrated as CK_t and CK_c.

Consider Fig. 3 A-C, shows timing diagram related with write operation.In figure 3 a, the processing system 100 of Fig. 1 is shown Timing diagram, wherein writing data on data/address bus 112a-b for the write operation as indicated by the write order in bus 114 (in spite of there are repeated data modes) is sent (after the corresponding waiting time) from SoC 120 for example in the form of bursting To memory sub-system 130.On the contrary, considering Fig. 3 B, the processing system 250 with the processing system 200 of Fig. 2A or Fig. 2 B is shown Related timing diagram, it considers the situations for repeating write data mode.As can be seen, write address order and label Location (for example, writing the tag addresses of data FIFO 242a, although not explicitly shown) is sent in bus 214, and from No relevant data are sent on SoC 220 to the bus 212a-b of memory sub-system 230, that is, write data mode transmitting It is suppressed.Write from the correspondence in memory sub-system 230 retrieved in data FIFO it is corresponding write data, such as above with reference to Fig. 2A-B It is discussed.Fig. 3 C shows a kind of replacement of Fig. 3 B, and wherein backward channel (not showing in Fig. 2A-B) can also be used to pass Label is passed, rather than sends label in bus 214, while being sent on bus 212a-b again without related data.One Aspect, backward channel [a:0] can be typically be shown as include a+1 bit width, can be used for transmitting mark The independent bus of label.

Consider Fig. 4 A-C, shows timing diagram related with read operation.In Figure 4 A, the processing system 100 of Fig. 1 is shown Timing diagram read data on data/address bus 112a-b wherein for the read operation as indicated by the read command in bus 114 (in spite of there are repeated data modes) is for example in the form of bursting from memory sub-system (after the corresponding waiting time) 130 are sent to SoC 120.On the contrary, considering Fig. 4 B, the processing system 270 with the processing system 260 of Fig. 2 C or Fig. 2 D is shown Related timing diagram, it considers duplicate readings according to the situation of mode.As can be seen, read address order is in bus 214 On sent, and respective labels are sent on backward channel 264, and do not have related data to be sent out on bus 212a-b It send, that is, read data pattern transmitting is suppressed.It is write from the correspondence in Memory Controller 208 and retrieves corresponding reading in data FIFO Data, as discussed above with reference to Fig. 2 C-D.Fig. 4 C shows a kind of replacement of Fig. 4 B, wherein the benefit as backward channel 264 It fills or replaces, a part (for example, a part of bus 212a) of one of data/address bus 212a-b may be alternatively used for transmitting label, There is no relevant data to be sent on bus 212a-b again simultaneously.

Referring now to Figure 5, showing a kind of decomposition of each component of the Memory Controller 208 according to Fig. 2A-D realized View.Data FIFO 242a is write, data time pattern examiner 242b is write and writes data FIFO policy management 242c and is had Body it is shown in FIG. 5.

It writes data FIFO 242a and is shown as including multiple (x) entries, they are representatively shown as 504a-x. Each entry has data pattern, for example, the 2*n bit of the combined width (2*n bit) corresponding to data/address bus 212a-b Mode, wherein the data pattern can be respectively stored in the 2*n bit register for writing data FIFO 242a.Correspondingly, often The also associated label of one entry 504a-x, it can be m bit width.Generally, m, which can be, writes data FIFO 242a The function (for example, m=log2 (x)) of middle number of entries writes the ground that specific data pattern is stored in data FIFO 242a to be directed toward Location or index.(for example, from processing element when new 2*n bit writes data to up to (512) at the Memory Controller 208 One of 204a-c), new data of writing are temporarily stored in register 506.

Write data time pattern examiner 242b have by register 506 value be stored in it is every in entry 504a-x The logic that the value of data pattern in one is made comparisons.If there is the matching with one of entry 504a-x, then hit is generated 502.Correspondingly, if there is hit, then the m bit label for corresponding to matching entry 504a-x is also provided, it exists as label It is sent in bus 214, rather than the 2*n stored in register 506 is than feature data.Since m bit is much smaller than 2*n bit, because This realizes that corresponding power is saved.

It writes data FIFO policy management 242c and is used by following manner to fill with more new writen data FIFO 242a's Entry 504a-x.Data FIFO policy management 242c is write to be shown as including control logic 508 and write data for saving One or more field 510a-y of the mode score of the entry 504a-x of FIFO 242a.In order to illustrate consideration wherein has 16 The example of a mode score.After the arrival 512 of new data as discussed above, if new data generates hit 502, generate The label of the entry 504a-x of hit is shown as hit tag [3:0] (hit label [3:0]) 514.Control logic 508 is incremented by The score (can be saturation value) in corresponding field 510a-x indexed through hit tag [3:0] 514.On the other hand, if hit 502 are not asserted, that is, there is no be directed to be stored in post in writing any one of entry 504a-x of data FIFO 242a The matching of data in storage 506, then one of entry 504a-x can be replaced to add in register 506 and write data.

Least recently used strategy can be used by following manner replacement entry 504a-x: in tracking above example Preceding 16 best results and entry 504a-x is replaced with that minimum score.Thus, if hit 502 is vacation (that is, not having Matching), then it is the schema creation FIFO label [3:0] 518 among field 510a-y with minimum point.FIFO label [3:0] 518 Pointed entry 504a-x is substituted by the new writen data in register 506.In some respects, the data pattern of some pre-selections can With locked, they keep static and irreplaceable (for example, having 2*n full 0 and/or 2*n complete 1 in writing data FIFO 242a Predetermined data pattern can be the locking data mode that can not be substituted).

It will be appreciated that various aspects include for executing process disclosed herein, function and/or the various methods of algorithm.Fig. 6-8 Each illustrative methods of the disclosure are illustrated, as described in more detail below.

Consider Fig. 6, illustrates the method 600 for write operation.In frame 602, Memory Controller 208 is from processing element One of 204a-c receives 2*n bit data, and generates 2*n than feature data for being sent to memory sub-system 230, example Such as, it stores it in register 506.In decision block 604, determine whether new data creates the update such as reference Fig. 5 discussion The needs of data FIFO policy management 242c are write (for example, writing data FIFO using the mode score in field 510a-y to substitute The entry of 242a).(that is, the "No" path got off from decision block 604) if not, then data in frame 606, register 506 Entry 504a-x is compareed to be examined to attempt to be matched, for example, in writing data time pattern examiner 242b.In decision block 608, if there is matching, then hit 502 is generated, and additionally, if there is matching, then confirmed in decision block 610 full Foot writes any strategy in data FIFO policy management 242c.

It is assumed that both decision block 608 and 610 defers to "Yes" path, then in frame 622, Memory Controller 208 is capable of emitting " no data transmit write order " with FIFO label the label of entry 504a-x will be matched and nonmatched data mode is sent to Memory sub-system 230.In frame 624, memory sub-system 230 reads correspondence and writes in data FIFO 252a-b or 254 and to be write Enter the data of the corresponding address in memory group 216.

If one of decision block 608 or 610 obtain "No" path, frame 618 is reached, wherein Memory Controller 208 issue normal write (that is, without inhibiting), and in frame 620, memory sub-system 230 is with received from bus 212a- The data of b complete write operation.

If following "Yes" path from decision block 604, frame 612 is reached, wherein new writen data mode, which is pushed to, writes number According to one of the entry 504a-x of FIFO 242a, and (for example, such as the use pattern score for referring to Fig. 5 discussion in frame 614 510a-y), Memory Controller 208 issues corresponding " write order with FIFO tag update " with to memory sub-system 230 In correspondence write the notice of data FIFO 252a-b or 254 and to be pushed to and write in data FIFO 242a about new writen data mode Label.After this, in block 616, the write operation of new writen data mode executes in a usual manner, and new writen data mode exists It is sent on data/address bus 212a-b, and additionally, writes data FIFO 252a-b or 254 and be pushed to new writen data mode In frame 614 at position indicated by received label.

Referring now to Figure 7, illustrating the method 700 for read operation.In frame 702, Memory Controller 208 for example via Bus 214 issues read command and corresponding read address to memory sub-system 230.In frame 704, by from corresponding memory group Data are read at 216 read address to execute read operation.In frame 706, read data pattern detector 262a-b or 272 is respectively by institute Data are read to make comparisons with data FIFO 252a-b or 255 is write.In decision block 708, if read data pattern detector 262a-b Or 272 detect matching in corresponding write in data FIFO 252a-b or 255, then defer to "Yes" path and reach frame 710, wherein this The label matched at the position being detected is sub from memory by backward channel 264 (or part use to bus 212a-b) System 230 is sent to SoC 220, and does not have the corresponding transmitting of data streams read on bus 212a-b.In frame 712, storage Device controller 208 extracts data streams read from the position specified by label in data FIFO 242a is write.If from decision block 708 follow "No" path, that is, there is no matchings, then execute normal read operations, wherein transmitting is from storage on bus 212a-b The data streams read of device subsystem 230.

Referring now to soil 8, by discussion method 800.In all respects, method 800 can generally be related to processing system (for example, Processing system 200) in communication and can be related to mean discussed above 600 and/or method 700.Processing system may include collection At the processor on system on chip (SoC) and the memory including memory sub-system being integrated on the second chip.

For example, in frame 802, method 800 may include determination will between processor and memory data/address bus (for example, Bus 212a-b) on transmit data (for example, from SoC 220 to memory sub-system 230 write data or from memory System 230 arrive SoC 220 reading data) have the first data pattern (e.g., including full 0 or complete 1 predetermined data pattern).Frame 804 include inhibiting the transmitting of the first data pattern on the data bus, and frame 806 includes between processor and memory Transmitting corresponds to the first address (example of the first data pattern in second bus (for example, control bus 214 or backward channel 264) Such as, the label of the FIFO entry of processor side first in first out (FIFO) (writing data FIFO 242a on such as SoC 220), or The label of the FIFO entry of person's memory side FIFO (the writing data FIFO 252a-b/254 of such as memory sub-system 230)), Wherein the first address is less than the first data pattern.

In some respects, the transmitting of the first data pattern in frame 806 is from processor to memory, this includes from depositing The first data pattern is read in the first address in the FIFO of reservoir side, and the memory in memory is written in the first data pattern Group (for example, memory group 216), wherein memory side FIFO (for example, writing data FIFO 252a-b) is located at the defeated of memory Enter/output port (for example, IO frame 213a-b) at or memory side FIFO (for example, writing data FIFO 254) be located at memory In the decoder frame (for example, decoder and latch 218) of group；Its center 806 further comprise check memory side FIFO with Attempt to obtain the first data pattern for the read operation initiated by processor.

In some respects, the transmitting of the first data pattern in frame 806 is from memory to processor, this includes from It manages the first address in the FIFO of device side and reads the first data pattern, check processor side FIFO is to attempt to obtain for by processor First data pattern of the write operation of initiation, and if the first data pattern is not present in the FIFO of processor side, by One data pattern is added to the second address in the FIFO of processor side, transmit on the data bus first data pattern and Transmit second address in second bus, and by the first data pattern be added to memory side FIFO the second address (for example, As discussed in method 600,700).

Skilled artisans will appreciate that various any one of various different technologies and skill can be used for information and signal It indicates.For example, through the data, instruction, order, information, signal, bit, symbol and the code that illustrate to be addressed always above Piece can by voltage, electric current, electromagnetic wave, magnetic field or magnetic particle, light field or light particle, or any combination thereof indicate.

In addition, skilled artisans will appreciate that, the various illustrative logics described in conjunction with aspect disclosed herein Block, module, circuit and algorithm steps can be implemented as the combination of electronic hardware, computer software, or both.Clearly to solve Say that this interchangeability of hardware and software, various illustrative components, block, module, circuit and step are with its function above The form of energy property makees generalization description.Such functionality is implemented as hardware or software depends on concrete application and application In the design constraint of total system.Technical staff can realize in different method described function for every kind of specific application Property, but such realization decision is not to be read as causing a departure from the scope of the present invention.

It can be embodied directly in hardware, in conjunction with method, sequence and/or the algorithm that various aspects disclosed herein describes by handling It is embodied in the software module that device executes or in combination of the two.Software module can reside in RAM memory, flash memory, ROM Memory, eprom memory, eeprom memory, register, hard disk, removable disk, CD-ROM or known in the art In the storage medium of any other form.Exemplary storage medium is coupled to processor so that the processor can be deposited from/to this Storage media reading writing information.In alternative, storage medium can be integrated into processor.

Correspondingly, an aspect of of the present present invention may include a kind of computer-readable medium, be implemented with a kind of for accessing DRAM array and by by self-correction operation be integrated into self-refresh cycles the method for executing low-power self-correction.Therefore, The present invention is not limited to the example explained and any means for executing functionality described here are included in this In the various aspects of invention.

Fig. 9 is illustrated wherein can be advantageously with the example wireless communications 900 of all aspects of this disclosure.For solution Say purpose, Fig. 9 shows three remote units 920,930 and 950 and two base stations 940.In Fig. 9,920 quilt of remote unit It is shown as mobile phone, remote unit 930 is illustrated as portable computer, and remote unit 950 is illustrated as wireless local loop system The remote unit that position in system is fixed.For example, these remote units can be mobile phone, handheld personal communication systems (PCS) unit, portable data units (such as personal digital assistant), equipment, navigation equipment, set-top box, the music for enabling GPS The fixed data cell (such as meter reading equipment) in player, video player, amusement unit, position or storage or inspection Any other equipment of rope data or computer instruction, or any combination thereof.Although Fig. 9 illustrates the introduction according to the disclosure Remote unit, but the disclosure is not limited to these exemplary cells explained.All aspects of this disclosure may be adapted for use at packet In any equipment for including active integrated circuit system (the on-chip circuit system including memory and for testing and characterizing).

Device and method disclosed above are commonly designed and are configured in the GDSII that may be stored on the computer-readable medium In GERBER computer documents.These files are provided to manufacture processor in turn, these manufacture processors are based on these texts Part manufactures device.As a result the product obtained is semiconductor wafer, is then cut into semiconductor element and is packaged into half Conductor chip.These chips are subsequently used in devices described above.

Although in terms of aforementioned disclosure shows illustrative of the invention, it should be noted that can be to making various change herein Become and modifies without departing from the scope of the present invention as defined by the appended claims.According to described herein of the invention Function, step and/or movement in the claim to a method of various aspects are not necessarily intended to be performed in any particular order.In addition, to the greatest extent Pipe element of the invention may be described or claimed with odd number, but plural number be also it is contemplated, unless explicitly Ground states to be defined in odd number.

Claims

1. the method that one kind is communicated in the processing system, which comprises

The data that determination will transmit on the data/address bus between processor and memory have the first data pattern；

Inhibit transmitting of first data pattern on the data/address bus；And

Transmitting corresponds to the first of first data pattern in the second bus between the processor and the memory Address.

2. the method as described in claim 1, which is characterized in that the processor includes processor side first in first out (FIFO), And the memory includes memory side FIFO, wherein first data pattern is present in the processor side FIFO At first address at first address and in the memory side FIFO.

3. method according to claim 2, which is characterized in that for described first from the processor to the memory The transmitting of data pattern reads first data pattern from first address in the memory side FIFO and by institute State the memory group that the first data pattern is written in the memory.

4. method as claimed in claim 3, which is characterized in that the memory side FIFO be located at the input of the memory/ At output port.

5. method as claimed in claim 3, which is characterized in that the memory side FIFO is located at the decoding of the memory group In device block.

6. method as claimed in claim 3, which is characterized in that including checking the memory side FIFO to attempt to be directed to By first data pattern for the read operation that the processor is initiated.

7. method as claimed in claim 3, which is characterized in that second bus is from the memory to the processor Backward channel either the data/address bus a part.

8. method according to claim 2, which is characterized in that for described first from the memory to the processor The transmitting of data pattern reads first data pattern from first address in the processor side FIFO.

9. method according to claim 8, which is characterized in that including checking the processor side FIFO to attempt to be directed to By first data pattern for the write operation that the processor is initiated.

10. method according to claim 8, which is characterized in that if be not present in including first data pattern described In the FIFO of processor side, then first data pattern is added to the second address in the processor side FIFO, described First data pattern is transmitted on data/address bus and transmits second address in second bus, and will be described First data pattern is added to second address of the memory side FIFO.

11. method according to claim 8, which is characterized in that second bus is control bus.

12. the method as described in claim 1, which is characterized in that the processor is integrated on system on chip (SoC), and And the memory is integrated on the second chip including memory sub-system.

13. the method as described in claim 1, which is characterized in that first address is less than first data pattern.

14. the method as described in claim 1, which is characterized in that first data pattern be include full 0 or complete 1 it is predetermined Data pattern.

15. a kind of equipment, comprising:

Processor；

Memory；

Data/address bus between the processor and the memory；

Data pattern examiner, the data that being configured to determine will transmit on the data/address bus have the first data pattern simultaneously And inhibit transmitting of first data pattern on the data/address bus；And

Second bus is configured to transmit between the processor and the memory corresponding to first data pattern First address.

16. equipment as claimed in claim 15, which is characterized in that the processor includes the first in first out of processor side (FIFO), and the memory includes memory side FIFO, wherein first data pattern is present in the processor side At first address at first address in FIFO and in the memory side FIFO.

17. equipment as claimed in claim 16, which is characterized in that for described the from the processor to the memory The transmitting of one data pattern, the data pattern examiner are write data mode detectors, and first data pattern from First address in the memory side FIFO is read and is written into the memory group in the memory.

18. equipment as claimed in claim 17, which is characterized in that the memory side FIFO is located at the defeated of the memory Enter/output port at.

19. equipment as claimed in claim 17, which is characterized in that the memory side FIFO is located at the solution of the memory group In code device block.

20. equipment as claimed in claim 17, which is characterized in that the data pattern examiner is read data pattern inspection Device is configured to check for the memory side FIFO to attempt to obtain for described in the read operation initiated as the processor First data pattern.

21. equipment as claimed in claim 17, which is characterized in that second bus is from the memory to the processing A part of the backward channel of the device either data/address bus.

22. equipment as claimed in claim 17, which is characterized in that for described the from the memory to the processor The transmitting of one data pattern, first data pattern are read from first address in the processor side FIFO.

23. equipment as claimed in claim 22, which is characterized in that the data pattern examiner is write data mode inspection Device is configured to check for the processor side FIFO to attempt to obtain for described in the read operation initiated as the processor First data pattern.

24. equipment as claimed in claim 23, which is characterized in that further comprise writing data FIFO policy management block, quilt It is configured to first data pattern in the case where first data pattern is not present in the processor side FIFO It is added to the second address in the processor side FIFO, wherein first data pattern is passed on the data/address bus And second address is passed in second bus, and first data pattern is added to the memory At second address of side FIFO.

25. equipment as claimed in claim 23, which is characterized in that second bus is control bus.

26. equipment as claimed in claim 15, which is characterized in that the processor is integrated on system on chip (SoC), and And the memory is integrated on the second chip including memory sub-system.

27. equipment as claimed in claim 15, which is characterized in that first address is less than first data pattern.

28. equipment as claimed in claim 15, which is characterized in that first data pattern be include that full 0 or complete 1 make a reservation for Data pattern.

29. a kind of equipment, comprising:

The data that transmit on data/address bus between processor and memory for determination have the dress of the first data pattern It sets；

For inhibiting the device of transmitting of first data pattern on the data/address bus；And

Transmitting corresponds to first data pattern in the second bus between the processor and the memory The device of first address.

30. equipment as claimed in claim 29, which is characterized in that including for from the memory side being located in the memory It reads the device of first data pattern and is used for the first data mould in first address of first in first out (FIFO) Formula is written the device of the memory group in the memory, and for from the advanced elder generation in processor side being located in the processor The device of first data pattern is read in first address of (FIFO) out, wherein first data pattern is present in institute At first address for stating the memory side FIFO and processor side FIFO.

31. a kind of processing system, comprising:

System on chip (SoC), including at least one processor；

Store memory package, including at least one storage memory dice；

Storage memory link between the SoC and the storage memory package；

Data time pattern examiner is write, being configured to determine will be in the SoC and the storage stored between memory package Depositing the data transmitted on the transmission link of memory link has the first data pattern and first data pattern is inhibited to exist Transmitting on the transmission link；And

The first storage memory interface of the SoC, is configured to transmit on the transmission link corresponding to first number According to the first address of mode.

32. processing system as claimed in claim 31, which is characterized in that the Soc includes the first in first out of processor side (FIFO), and the storage memory package includes memory side FIFO, wherein first data pattern be present in it is described At first address at first address in the FIFO of processor side and in the memory side FIFO.

33. processing system as claimed in claim 32, which is characterized in that the storage memory package further comprises second Memory interface is stored, is configured to receive first address and provides first address including the storage The storage Memory Controller of device side FIFO, wherein the storage Memory Controller is configured to from the memory side FIFO First address search described in the first data pattern, and transmit first data pattern for being written into the storage The storage memory dice of memory package.

34. processing system as claimed in claim 32, which is characterized in that the storage memory package further comprises reading According to time mode detector, being configured to determine will be in the storage between the storage memory package and the SoC The data transmitted in the receives link of memory link have the second data pattern and inhibit second data pattern in institute State the transmitting in receives link；And

Second storage memory interface of the storage memory package, is configured to transmit correspondence on the transmission link In the second address of second data pattern, wherein second data pattern is present in the institute in the processor side FIFO It states at second address at the second address and in the memory side FIFO.