CN109637374B - Display panel and display device - Google Patents
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- CN109637374B CN109637374B CN201910087930.8A CN201910087930A CN109637374B CN 109637374 B CN109637374 B CN 109637374B CN 201910087930 A CN201910087930 A CN 201910087930A CN 109637374 B CN109637374 B CN 109637374B
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Abstract
The invention discloses a display panel and a display device. The display panel comprises a display area, a non-display area, a notch and a data line extending along a first direction, the edge of the display panel is sunken towards the inside of the display area along a second direction to form the notch, the first display area is positioned on one side of the notch, and the second display area is adjacent to the notch and the first display area; the scanning lines comprise first scanning lines positioned in the first display area and second scanning lines positioned in the second display area, and the number of sub-pixels electrically connected with the first scanning lines is less than that of the sub-pixels electrically connected with the second scanning lines; the scanning lines comprise a wire walking part and a grid part, the grid part is used as a grid of the switch tube, the line width of the grid part of the first scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the wire walking part of the first scanning line is different from the line width of the wire walking part of the second scanning line. The invention can improve the display uniformity.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the development of electronic technology and the increasing requirements of users on the performance and sensory experience of electronic products, manufacturers are also actively researching and developing electronic products capable of increasing selling points. Various special-shaped display screens, such as circular display screens or display screens with notches, appear in the market, and in the display area of the special-shaped display panels, pixels cannot be arranged in a regular rectangular array, so that the number of pixels in each row of pixels is not necessarily the same, and then the loads on the scanning lines driving different pixel rows are different, so that the brightness of the pixels determined by different scanning lines is different, and the display uniformity of the display panel is poor.
Therefore, it is an urgent technical problem to be solved in the art to provide a display panel and a display device with improved display uniformity.
Disclosure of Invention
In view of this, the present invention provides a display panel and a display device, which solve the technical problem of improving display uniformity.
In order to solve the above technical problem, in a first aspect, the present invention provides a display panel, including a display area, a non-display area surrounding the display area, and at least one notch, where the display area includes a plurality of data lines extending along a first direction, an edge of the display panel is recessed towards an inside of the display area along a second direction to form the notch, the second direction intersects with the first direction, the display area includes a first display area and a second display area, the first display area is located on one side of the notch in the second direction, and the second display area is adjacent to both the notch and the first display area in the first direction; the display area further includes:
the plurality of sub-pixels are arranged in an array and are arranged into pixel rows along a second direction;
the scanning lines extend along the second direction, one scanning line drives a plurality of sub-pixels positioned in the same pixel row, the scanning lines comprise a first scanning line positioned in the first display area and a second scanning line positioned in the second display area, and the number of the sub-pixels electrically connected with the first scanning line is less than that of the sub-pixels electrically connected with the second scanning line; wherein,
the scanning lines comprise a wire walking part and a grid part, wherein the grid part is used as a grid of the switch tube, the line width of the grid part of the first scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the wire walking part of the first scanning line is different from the line width of the wire walking part of the second scanning line.
In a second aspect, the present invention provides a display device comprising any one of the display panels provided by the present invention.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the invention realizes the adjustment of the load on the scanning line without changing the performance of the switching tube in the pixel circuit by performing differential design on the widths of line segments at different parts on the same scanning line. The integral load on the first scanning line and the integral load on the second scanning line can be approximately the same, so that the brightness of the sub-pixels driven by the first scanning line is consistent with that of the sub-pixels driven by the second scanning line, and the display uniformity is improved.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic view of a display panel according to an embodiment of the invention;
FIG. 2 is a first schematic diagram illustrating a comparison of pixel circuits in a first display area and a second display area of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an alternative implementation of a pixel circuit in a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a pixel circuit corresponding to FIG. 3;
FIG. 5 is a timing diagram of the pixel circuit corresponding to FIG. 4;
FIG. 6 is a schematic diagram of an alternative embodiment of a display panel according to an embodiment of the present invention;
FIG. 7 is a second schematic diagram illustrating a comparison of pixel circuits in the first display region and the second display region of the display panel shown in FIG. 6;
FIG. 8 is a third schematic diagram illustrating a comparison of pixel circuits in the first display region and the second display region of the display panel shown in FIG. 6;
FIG. 9 is a fourth schematic diagram illustrating a comparison of pixel circuits in the first display region and the second display region of the display panel shown in FIG. 6;
FIG. 10 is a schematic diagram of another alternative embodiment of a display panel according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of another alternative embodiment of a display panel according to an embodiment of the present invention;
fig. 12 is a fifth comparative diagram of pixel circuits of the first display area and the second display area in the display panel according to the embodiment of the invention;
fig. 13 is a sixth schematic diagram illustrating a comparison between pixel circuits of the first display area and the second display area in the display panel according to the embodiment of the invention;
fig. 14 is a seventh comparative diagram of pixel circuits of the first display area and the second display area in the display panel according to the embodiment of the present invention;
fig. 15 is a schematic diagram illustrating a comparison between pixel circuits in the first display area and the second display area in the display panel according to the embodiment of the invention;
fig. 16 is a schematic view of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a schematic view of a display panel according to an embodiment of the present invention. Fig. 2 is a first schematic diagram illustrating a comparison of pixel circuits in a first display area and a second display area of a display panel according to an embodiment of the present invention.
As shown in fig. 1, the display panel includes a display area AA, a non-display area BA disposed around the display area AA, and at least one notch K, where the display area AA includes a plurality of data lines D extending along a first direction a, and only one data line D is illustrated in the figure for clarity of illustrating other structures of the display panel. The edge of the display panel is recessed towards the inside of the display area AA along a second direction b to form a notch K, the second direction b is crossed with the first direction a, the display area AA comprises a first display area AA1 and a second display area AA2, the first display area AA1 is positioned on one side of the notch K in the second direction b, and the second display area AA2 is adjacent to both the notch K and the first display area AA1 in the first direction a; in the figure, two second display areas AA2 are disposed at both sides of the first display area AA1, and the two second display areas AA2 may have the same or different sizes. The display area AA further includes: and a plurality of sub-pixels sp arranged in an array, the plurality of sub-pixels sp being arranged in a pixel row spH along the second direction b.
A plurality of scan lines G extending along the second direction b, one scan line G driving a plurality of sub-pixels sp located in the same pixel row spH, the scan line G including a first scan line G1 located in the first display area AA1 and a second scan line G2 located in the second display area AA2, the number of sub-pixels sp electrically connected to the first scan line G1 being less than the number of sub-pixels sp electrically connected to the second scan line G2, the number of sub-pixels electrically connected to the scan line being only schematically shown in the figure; the scanning line G comprises a wiring part and a grid part, and the grid part is used as a grid of the switching tube. The display panel comprises pixel circuits, generally, one pixel circuit drives one sub-pixel, one scanning line is electrically connected with each pixel circuit driving the same pixel row to provide scanning signals for the pixel circuits, the pixel circuits comprise a plurality of switching tubes, one scanning line comprises a plurality of grid parts, the grid parts are overlapped with active layers in the display panel, and parts except the grid parts are wiring parts.
Fig. 2 illustrates only one alternative pixel circuit diagram and is not intended to limit the present invention. As shown in fig. 2, includes: the scanning line G (the first scanning line G1 and the second scanning line G2), the data line D, the positive power supply line PVDD, the reset trace Ref and the emission control line Emit, in the present invention, the line width of the gate portion of the first scanning line is equal to the line width of the gate portion of the second scanning line, the line width of the trace portion of the first scanning line is different from the line width of the trace portion of the second scanning line, and fig. 2 only shows that the line width of the trace portion of the first scanning line is greater than the line width of the trace portion of the second scanning line. The gate portion is a partial line segment on the scanning line G in the region circled by the dotted line in the figure, and the portions of the scanning line except the gate portion are all the routing portions. In the present invention, the gate portion and the trace portion corresponding to the first scan line and the second scan line can be understood by referring to the schematic diagram in fig. 2.
The line width of the grid part of the first scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the routing part of the first scanning line is different from the line width of the routing part of the second scanning line. The line width is the width of the routing in the extending direction perpendicular to the routing, the line width of the gate part is the width of the gate part in the extending direction perpendicular to the gate part, and the line width of the routing part is the width of the routing part in the extending direction perpendicular to the routing part. According to the law of resistance, R is rho L/S, R is resistance, rho is resistivity, L is resistance length, and S is resistance cross-sectional area. The size of the line width affects the size of the cross-sectional area of the resistor, and thus the size of the resistor. The line width of the grid part of the first scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the routing part of the first scanning line is different from the line width of the routing part of the second scanning line. The resistances of the routing part of the first scanning line and the routing part of the second scanning line are different, so that the overall resistance of the first scanning line is different from the overall resistance of the second scanning line. When the line width of the routing part of the first scanning line is larger than that of the routing part of the second scanning line, the integral resistance of the first scanning line is smaller than that of the second scanning line; when the line width of the routing portion of the first scanning line is smaller than the line width of the routing portion of the second scanning line, the overall resistance of the first scanning line is larger than the overall resistance of the second scanning line. The magnitude of the resistance of the scan line further affects the magnitude of the load of the scan line in driving the subpixels.
In the invention, the number of the sub-pixels electrically connected with the first scanning line is less than that of the sub-pixels electrically connected with the second scanning line, so that when the sub-pixels are driven to display, the load generated by the plurality of sub-pixels driven on the first scanning line is less than that generated by the plurality of sub-pixels driven on the second scanning line. The grid part is multiplexed as the grid of the switch tube, the overlapped part of the active layer and the grid in the switch tube is a channel region, the size of the grid affects the size of the channel region, namely the size of the grid can correspondingly affect the performance of the switch tube. According to the invention, the width of the routing part of the first scanning line is different from that of the routing part of the second scanning line, the resistance of the scanning line is adjusted by adjusting the width of the routing part on the scanning line, and then the load on the scanning line is adjusted, so that the overall load on the first scanning line is approximately the same as the overall load on the second scanning line, the brightness of the sub-pixels driven by the first scanning line is ensured to be consistent with that of the sub-pixels driven by the second scanning line, and the display uniformity is improved. The invention realizes the adjustment of the load on the scanning line without changing the performance of the switching tube in the pixel circuit by performing differential design on the widths of line segments at different parts on the same scanning line.
In an embodiment, fig. 3 is a schematic diagram of an alternative implementation of a pixel circuit in a display panel according to an embodiment of the present invention. Fig. 4 is a schematic diagram of a pixel circuit corresponding to fig. 3. Fig. 5 is a timing diagram of the pixel circuit corresponding to fig. 4.
As shown in fig. 3, the scan lines G include a first scan line JG and a second scan line YG, and one first scan line JG and one second scan line YG commonly drive a plurality of sub-pixels located in the same pixel row, and in the figure, one pixel circuit is illustrated, and the display panel includes a plurality of pixel circuits arranged in an array. In the pixel circuit, the first scan line JG supplies an active level signal in an initialization stage, and the second scan line YG supplies an active level signal in a data writing stage. The regions Z1 and Z2 shown by the dashed line in fig. 3 are regions where the gate portions of the first scanning line JG are located, and the regions Z3 and Z4 shown by the dashed line are regions where the gate portions of the second scanning line YG are located.
Fig. 4 only exemplifies that the pixel circuit includes 7 transistors (T1 to T7) and 1 capacitor C, and the pixel circuit includes signal terminals electrically connected to the first scan line JG, the second scan line YG, the data line D, the positive power supply line PVDD, the negative power supply line PVEE, the reset trace Ref, and the emission control line Emit, and a first node N1, a second node N2, a third node N3, and a fourth node N4. Along with the timing diagram shown in fig. 5. The working phases of the pixel circuit can be divided into: an initialization phase t1, a data writing phase t2 and a pixel light emission phase t 3. At initialization stage t 1: the first scan line JG provides an active level signal, and the reset signal provided by the reset trace Ref initializes the first node N1, while the reset signal resets the fourth node N4. At the data writing stage t 2: the b scan line YG provides an active level signal, and the data line D transmits a data signal to the first node N1, at which time the capacitor C is charged. In the pixel lighting period t 3: the emission control line Emit supplies an active level signal, the capacitor C discharges, and the positive power supply line PVDD transmits a positive power supply signal to the fourth node N4.
It should be noted that the schematic diagrams of fig. 3 and 4 are only for illustrating the operation principle of the first scanning line JG and the second scanning line YG, and the pixel circuit is not limited to the invention.
In the present invention, the first scan line in the first display area includes a first a scan line and a first b scan line, i.e. the schematic diagram of the pixel circuit in the first display area can refer to fig. 3. The second scan lines in the second display area include a second scan line and a second scan line, and the pixel circuit diagram in the second display area can also refer to the schematic diagram in fig. 3. The line width of the grid part of the first scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the routing part of the first scanning line is different from the line width of the routing part of the second scanning line, wherein the line width of the routing part of the first scanning line can be larger than the line width of the routing part of the second scanning line, so that the resistance load of the first scanning line is smaller than that of the second scanning line; or the line width of the routing part of the first scanning line is smaller than that of the routing part of the second scanning line, so that the resistance load of the first scanning line is larger than that of the second scanning line. The line width of the grid part of the first second scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the routing part of the first second scanning line is different from the line width of the routing part of the second scanning line; the line width of the routing part of the first scanning line B can be larger than that of the routing part of the second scanning line B, so that the resistance load of the first scanning line B is smaller than that of the second scanning line B; or the line width of the wire part of the first second scanning line is smaller than that of the wire part of the second scanning line, so that the resistance load of the first second scanning line is larger than that of the second scanning line.
In this embodiment, without changing the line widths of the gate portions on the first scanning line and the second scanning line, the performance of the switching tube in the pixel circuit electrically connected to the first scanning line is substantially the same as the performance of the switching tube in the pixel circuit electrically connected to the second scanning line, and in the initialization stage of the pixel circuit, when the first scanning line and the second scanning line supply the same voltage signal, the turn-on speed and the turn-on size of the switching tube multiplexing the gate portion of the first scanning line as the gate are substantially the same as the turn-on speed and the turn-on size of the switching tube multiplexing the gate portion of the second scanning line as the gate; in the same way, the on speed and the on size of the switching tube multiplexing the gate portion of the first second scanning line as the gate are substantially the same as those of the switching tube multiplexing the gate portion of the second scanning line as the gate. The resistance on the scanning line is adjusted by adjusting the line width of the wire walking part on the first scanning line and the second scanning line simultaneously, so that the integral load on the first scanning line is approximately the same as the integral load on the second scanning line, the brightness of the sub-pixel driven by the first scanning line and the first scanning line is ensured to be consistent with the brightness of the sub-pixel driven by the second scanning line and the second scanning line, and the display uniformity is improved.
In an embodiment, fig. 6 is a schematic diagram of an alternative implementation manner of a display panel according to an embodiment of the present invention. Fig. 7 is a second schematic diagram comparing pixel circuits of the first display region and the second display region in the display panel provided in fig. 6. As shown in fig. 6, the display panel further includes shift registers including a first shift register VSR1 and a second shift register VSR 2; the non-display area BA includes a first non-display area BA1 and a second non-display area BA2, in the second direction b, the first non-display area BA1 is located on a side of the first display area AA away from the notch K, the two second non-display areas BA2 are respectively located on two sides of the second display area AA2, the first shift register VSR1 is located in the first non-display area BA1, and the second shift register VSR2 is located in the second non-display area BA 2; a first scan line G1 is electrically connected to a first shift register VSR 1; both ends of one second scan line G2 are electrically connected to the two second shift registers VSR2 respectively located in the two second non-display areas BA 2. In this embodiment, the first scan line in the first display area is electrically connected to a first shift register for driving, the first shift register is located in the first non-display area, that is, the first scan line is driven in a single-side driving manner, and the corresponding shift register connected to the first scan line may not be disposed in the gap non-display area (gap non-display area BAK in the figure) located on the side of the first display area away from the first non-display area in the first direction, so that the space of the gap non-display area can be saved, and the narrowing of the gap non-display area is facilitated. In the display region of the display panel provided in this embodiment, since the first scan line is driven by one shift register, and the scan signal is transmitted from the right side to the left side on the first scan line as illustrated in fig. 6, the scan signal output from the first shift register to the first scan line drives a whole row of sub-pixels electrically connected to the first scan line; the second scanning line is driven by two shift registers, scanning signals on the second scanning line are respectively transmitted from two sides to the middle, and the scanning signals output to the second scanning line by one second shift register are equivalent to driving half rows of sub-pixels electrically connected with the second scanning line. In practice, the size of the gap of the display panel is relatively smaller than the size of the whole display panel, the number of the sub-pixels electrically connected with the first scanning line is smaller than that of the sub-pixels electrically connected with the second scanning line, and meanwhile, the number of the sub-pixels electrically connected with the first scanning line is larger than half of that of the sub-pixels electrically connected with the second scanning line. Therefore, in this embodiment, when the display panel is driven to display, the loads generated by the driving sub-pixels on the left and right sides of the second scan line are substantially the same, but the load generated by the driving sub-pixels on the first scan line is relatively large, and as shown in fig. 7, taking the example that the scan lines include the first scan line JG and the second scan line YG, the line width of the routing portion B1 of the first scan line G1 is set to be larger than the line width of the routing portion B2 of the second scan line G2, and the line width of the gate portion S1 of the first scan line G1 is equal to the line width of the gate portion S2 of the second scan line G2. The first scan line G1 includes a first scan line JG1 and a first second scan line YG1, and the second scan line G2 includes a second scan line JG2 and a second scan line YG 2. The resistance of the first scanning line is reduced by increasing the line width of the wire walking part on the first scanning line, so that the overall load of the first scanning line can be reduced, and further, when the display panel is driven to display, the overall load on the first scanning line is approximately the same as the overall load on the second scanning line, the brightness of the sub-pixels driven by the first scanning line is consistent with that of the sub-pixels driven by the second scanning line, and the display uniformity is improved.
In one embodiment, the display panel further includes a power line extending in a first direction, the display panel further includes a pixel circuit including a driving transistor, the power line being connected to the driving transistor for generating a driving current; referring to the pixel circuit shown in fig. 4, the power line is the positive power line PVDD, and the driving transistor is the transistor T7. .
As shown in fig. 7, the power line P is overlapped with the first scan line G1 and the second scan line G2. When the line width of the routing part of the first scanning line is larger than the line width of the routing part of the second scanning line, the overlapping area of the corresponding first scanning line and the power line is enlarged, so that the parasitic capacitance between the first scanning line and the power line is enlarged, and the parasitic capacitance also influences the load on the first scanning line. Furthermore, the area of the insulated overlapping of the power line and the first scanning line is smaller than or equal to the area of the insulated overlapping of the power line and the second scanning line. When the area of the power line which is in insulation overlapping with the first scanning line is equal to the area of the power line which is in insulation overlapping with the second scanning line, the influence of the parasitic capacitance between the first scanning line and the power line on the load of the first scanning line is at least ensured to be the same as the influence of the parasitic capacitance between the second scanning line and the power line on the load of the second scanning line. When the area of the power line and the first scanning line in insulation overlapping is smaller than the area of the power line and the second scanning line in insulation overlapping, the parasitic capacitance between the first scanning line and the power line is smaller than the parasitic capacitance between the second scanning line and the power line, so that the load on the first scanning line is reduced.
Optionally, when the area of the power line in insulation overlapping with the first scan line is set to be smaller than or equal to the area of the power line in insulation overlapping with the second scan line, the area may be implemented by adjusting the line width of the first scan line in the area where the first scan line overlaps with the power line, or by adjusting the line width of the power line in the area where the first scan line overlaps with the power line.
Further, in an embodiment, fig. 8 is a schematic diagram illustrating a comparison of pixel circuits of the first display region and the second display region in the display panel provided in fig. 6. As shown in fig. 8, a portion where the power line P is insulated from the first scan line G1 is a first overlap portion W1, a portion where the power line P is insulated from the second scan line G2 is a second overlap portion W2, and a line width of the first overlap portion W1 is smaller than a line width of the second overlap portion W2. In the figure, the scanning lines include a first scanning line and a second scanning line as an example, and the power line overlaps with the first scanning line and the second scanning line. This embodiment achieves that the area of the power supply line insulatively overlapping the first scan line is equal to the area of the power supply line insulatively overlapping the second scan line, or that the area of the power supply line insulatively overlapping the first scan line is smaller than the area of the power supply line insulatively overlapping the second scan line, by reducing the line width of a part of the power supply line (first overlapping portion). The increase of the line width of the wire walking part of the first scanning line is ensured not to influence the parasitic capacitance between the power line and the first scanning line, and further the parasitic capacitance between the power line and the first scanning line is prevented from playing a reverse role in the purpose of reducing the load on the first scanning line. Or the parasitic capacitance between the power line and the first scanning line is reduced, and the load on the first scanning line is reduced by simultaneously adjusting the line width of the routing part of the first scanning line and the parasitic capacitance between the power line and the first scanning line, so that the overall load on the first scanning line is approximately the same as the overall load on the second scanning line.
Further, fig. 9 is a fourth schematic diagram comparing pixel circuits of the first display area and the second display area in the display panel provided in fig. 6. As shown in fig. 9, the data line D is overlapped with the scan line in an insulating manner, a portion of the first scan line G1 overlapped with the data line D in an insulating manner is a third overlapped part W3, a portion of the second scan line G2 overlapped with the data line D in an insulating manner is a fourth overlapped part W4, and a line width of the third overlapped part W3 is smaller than a line width of the fourth overlapped part W4. In this embodiment, the line width of the third overlapping portion on the first scan line is set to be smaller than the line width of the fourth overlapping portion on the second scan line, so that it can be ensured that the parasitic capacitance between the third overlapping portion and the data line is smaller than the parasitic capacitance between the fourth overlapping portion and the data line, and then the load generated by the parasitic capacitance on the first scan line is smaller than the load generated by the parasitic capacitance on the second scan line, which is beneficial to reducing the size of the whole load on the first scan line. In addition, in the display panel, one data line which simultaneously penetrates through the first display area and the second display area can be overlapped with the third overlapping part and the fourth overlapping part, and in the embodiment, the parasitic capacitance between the third overlapping part and the data line is smaller than that between the fourth overlapping part and the data line, so that the parasitic capacitance on the data line can be reduced, the delay of data writing when a signal is supplied to the data line can be reduced, and the charging speed of the data line is higher.
In the embodiment corresponding to fig. 9, if the line width of the third overlapping portion is set to be smaller than the line width of the fourth overlapping portion, the area where the third overlapping portion overlaps the data line becomes smaller, and the parasitic capacitance between the third overlapping portion and the data line becomes smaller, resulting in a smaller load on the data line. For a display panel with a short data line length, when the load on the data line is too small, the potential of the charged data line may not be maintained, which may affect the magnitude of the data signal written in the data writing stage, and further affect the display effect. The length of the data line is set to be d, wherein d is more than or equal to 100 mm. In the present invention, a portion of the data lines (e.g., the data lines D shown in fig. 1) will penetrate through the entire display area in the first direction, and a portion of the data lines will pass through the second display area, then enter the second display area after being routed in the gap non-display area (e.g., the data lines D shown in fig. 6), and both of the data lines satisfy the above requirement of the length range. The technical scheme provided by the invention is suitable for the display panel with the length of the data line being more than or equal to 100mm, when the line width of the third overlapping part is smaller than the line width of the fourth overlapping part and the parasitic capacitance on the first scanning line is reduced to realize the reduction of the load on the first scanning line, the corresponding reduction of the parasitic capacitance on the data line does not influence the potential after the data line is charged, and meanwhile, the corresponding reduction of the parasitic capacitance on the data line can reduce the load on the data line, thereby reducing the delay of data writing and being beneficial to improving the charging speed of the data line.
In an embodiment, the line width of the first overlapping portion may be set to be smaller than the line width of the second overlapping portion, and the line width of the third overlapping portion may be set to be smaller than the line width of the fourth overlapping portion, so as to reduce the overall load on the first scanning line, which is not described herein again.
In the above embodiment, the first scan line is driven by one shift register at one end, and the second scan line is driven by two shift registers at the two ends. Optionally, the display panel provided by the present invention may also include: the first scanning line is driven by one shift register at one end, while the second scanning line is driven by one shift register at one end.
In an embodiment, fig. 10 is a schematic diagram of another alternative implementation of the display panel according to the embodiment of the present invention. As shown in fig. 10, the display panel further includes shift registers including a first shift register VSR1 and a second shift register VSR 2; the non-display area BA includes a first non-display area BA1 and a second non-display area BA2, in the second direction b, the first non-display area BA1 is located on a side of the first display area AA away from the notch K, the two second non-display areas BA2 are respectively located on two sides of the second display area AA, the first shift register VSR1 is located in the first non-display area BA1, and the second shift register VSR2 is located in the second non-display area BA 2; one first scan line G1 is electrically connected to one first shift register VSR1, and one second scan line G2 is electrically connected to one second shift register VSR 2. Fig. 1 illustrates a situation where the second shift register VSR2 and the first shift register VSR1 are located on the same side of the display area, and optionally, the second shift register VSR2 and the first shift register VSR1 may also be located on different sides of the display area, which is not described herein again.
In another embodiment, fig. 11 is a schematic diagram of another alternative implementation of the display panel according to the embodiment of the present disclosure. As shown in fig. 11, in two adjacent second scanning lines G2: one second scan line G2 is electrically connected to the second shift register VSR2 of one second non-display area BA2, and the other second scan line G2 is electrically connected to the second shift register VSR2 of the other second non-display area BA 2.
In the embodiments corresponding to fig. 10 and fig. 11, the first scan line located in the first display area is electrically connected to a first shift register, and the first shift register is located in the first non-display area, that is, the first scan line is driven in a single-side driving manner, and the shift register connected to the first scan line may not be disposed in the gap non-display area (gap non-display area BAK in the figure) located on the side of the first display area away from the first non-display area in the first direction, so that the space of the gap non-display area can be saved, and the gap non-display area is narrowed. Meanwhile, a second scanning line in the second display area is electrically connected with a second shift register, namely the second scanning line is also driven by adopting a unilateral driving mode, when the display panel is driven to display, in a second direction, a scanning signal on the first scanning line is transmitted from one end to the other end, and a scanning signal on the second scanning line is also transmitted from one end to the other end.
Fig. 10 and fig. 11 correspond to the pixel circuit conditions of the first display area and the second display area in the embodiment shown in fig. 12. Fig. 12 is a fifth schematic diagram illustrating a comparison between pixel circuits in the first display area and the second display area in the display panel according to the embodiment of the invention. As shown in fig. 12, taking the scanning lines including the first scanning line JG and the second scanning line YG as an example, the line width of the routing portion B1 of the first scanning line G1 is smaller than the line width of the routing portion B2 of the second scanning line G2, and the line width of the gate portion S1 of the first scanning line G1 is equal to the line width of the gate portion S2 of the second scanning line G2. The first scan line G1 includes a first scan line JG1 and a first second scan line YG1, and the second scan line G2 includes a second scan line JG2 and a second scan line YG 2. According to the invention, the load on the first scanning line is increased by setting the line width of the wiring part of the first scanning line to be smaller than the line width of the wiring part of the second scanning line. Therefore, the overall load on the first scanning line is approximately the same as the overall load on the second scanning line, the brightness of the sub-pixels driven by the first scanning line is consistent with that of the sub-pixels driven by the second scanning line, and the display uniformity is improved.
In one embodiment, the display panel further includes a power line extending in the first direction, and the display panel further includes a pixel circuit including a driving transistor, the power line being connected to the driving transistor for generating a driving current. The power supply line defined in the present invention can be understood with reference to the corresponding pixel circuit diagram of fig. 4 described above. The power supply line is the positive power supply line PVDD illustrated in fig. 4. Referring to the schematic diagram in fig. 12, the power line P is overlapped with the first scan line G1 in an insulated manner, and the power line P is overlapped with the second scan line G2 in an insulated manner. When the line width of the routing part of the first scanning line is smaller than the line width of the routing part of the second scanning line, the overlapping area of the corresponding first scanning line and the power line is reduced, so that the parasitic capacitance between the first scanning line and the power line is reduced, and the parasitic capacitance also influences the load on the first scanning line. Furthermore, the area of the insulated overlapping of the power line and the first scanning line is larger than or equal to the area of the insulated overlapping of the power line and the second scanning line. When the area of the power line which is in insulation overlapping with the first scanning line is equal to the area of the power line which is in insulation overlapping with the second scanning line, the influence of the parasitic capacitance between the first scanning line and the power line on the load of the first scanning line is at least ensured to be the same as the influence of the parasitic capacitance between the second scanning line and the power line on the load of the second scanning line. When the area of the power line and the first scanning line in insulation overlapping is larger than the area of the power line and the second scanning line in insulation overlapping, the parasitic capacitance between the first scanning line and the power line is larger than the parasitic capacitance between the second scanning line and the power line, so that the load on the first scanning line is increased.
Optionally, when the area of the power line in insulation overlapping with the first scan line is set to be greater than or equal to the area of the power line in insulation overlapping with the second scan line, the area may be implemented by adjusting the line width of the first scan line in the area where the first scan line overlaps with the power line, or by adjusting the line width of the power line in the area where the first scan line overlaps with the power line.
In an embodiment, fig. 13 is a sixth schematic diagram illustrating a comparison of pixel circuits in the first display area and the second display area in the display panel according to the embodiment of the invention. A portion of the power line P insulated and overlapped with the first scan line G1 is a first overlap portion W1, a portion of the power line P insulated and overlapped with the second scan line G2 is a second overlap portion W2, and a line width of the first overlap portion W1 is greater than a line width of the second overlap portion W2. In the figure, taking the scanning lines including the first scanning line JG and the second scanning line YG as an example, the power line P overlaps with both the first scanning line JG and the second scanning line YG. This embodiment achieves that the area of the power supply line insulatively overlapping the first scan line is equal to the area of the power supply line insulatively overlapping the second scan line, or that the area of the power supply line insulatively overlapping the first scan line is larger than the area of the power supply line insulatively overlapping the second scan line, by increasing the line width of a part of the power supply line (first overlapping portion). The reduction of the line width of the wiring part of the first scanning line is ensured not to influence the parasitic capacitance between the power line and the first scanning line, and further the parasitic capacitance between the power line and the first scanning line is prevented from playing a reverse role in the purpose of increasing the load on the first scanning line. Or the parasitic capacitance between the power line and the first scanning line is increased, and the load on the first scanning line is increased by adjusting the line width of the routing part of the first scanning line and the parasitic capacitance between the power line and the first scanning line simultaneously, so that the overall load on the first scanning line is approximately the same as the overall load on the second scanning line.
In an embodiment, fig. 14 is a schematic diagram illustrating a comparison between pixel circuits in a first display area and a second display area in a display panel according to an embodiment of the invention. As shown in fig. 14, a portion where the first scan line G1 is overlapped with the power supply line P in an insulated manner is a fifth overlapping portion W5, a portion where the second scan line G2 is overlapped with the power supply line P in an insulated manner is a sixth overlapping portion W6, and a line width of the fifth overlapping portion W5 is greater than a line width of the sixth overlapping portion W6. This embodiment achieves that the area of the insulated overlap of the power supply line with the first scan line is equal to the area of the insulated overlap of the power supply line with the second scan line, or that the area of the insulated overlap of the power supply line with the first scan line is larger than the area of the insulated overlap of the power supply line with the second scan line, by increasing the line width of a part of the first scan line (fifth overlap). And ensuring that the parasitic capacitance between the power line and the first scanning line is equal to the parasitic capacitance between the power line and the second scanning line, or ensuring that the parasitic capacitance between the power line and the first scanning line is increased. The load on the first scanning line is increased by simultaneously adjusting the line width of the wiring part of the first scanning line and the parasitic capacitance between the power line and the first scanning line, so that the overall load on the first scanning line is ensured to be approximately the same as the overall load on the second scanning line.
In an embodiment, fig. 15 is a schematic diagram illustrating a comparison between pixel circuits in a first display area and a second display area in a display panel according to an embodiment of the invention. As shown in fig. 15, the data line D is overlapped with the scan line in an insulating manner, a portion of the first scan line G1 overlapped with the data line D in an insulating manner is a third overlapping portion W3, a portion of the second scan line G2 overlapped with the data line D in an insulating manner is a fourth overlapping portion W4, and a line width of the third overlapping portion W3 is greater than a line width of the fourth overlapping portion W4. In this embodiment, the line width of the third overlapping portion on the first scan line is set to be greater than the line width of the fourth overlapping portion on the second scan line, so that it can be ensured that the parasitic capacitance between the third overlapping portion and the data line is greater than the parasitic capacitance between the fourth overlapping portion and the data line, and then the load generated by the parasitic capacitance on the first scan line is greater than the load generated by the parasitic capacitance on the second scan line, which is beneficial to increasing the size of the whole load on the first scan line.
In an embodiment, the line width of the first overlapping portion may be set to be greater than the line width of the second overlapping portion, and the line width of the third overlapping portion may be set to be greater than the line width of the fourth overlapping portion, so as to increase the overall load on the first scanning line, which is not described herein again.
Fig. 16 is a schematic view of a display device according to the present invention. As shown in fig. 16, the display device includes a display panel 100 provided in any embodiment of the present invention.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
the invention realizes the adjustment of the load on the scanning line without changing the performance of the switching tube in the pixel circuit by performing differential design on the widths of line segments at different parts on the same scanning line. The integral load on the first scanning line and the integral load on the second scanning line can be approximately the same, so that the brightness of the sub-pixels driven by the first scanning line is consistent with that of the sub-pixels driven by the second scanning line, and the display uniformity is improved.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (6)
1. A display panel is characterized by comprising a display area, a non-display area and at least one notch, wherein the non-display area is arranged around the display area, the display area comprises a plurality of data lines extending along a first direction, the edge of the display panel is sunken towards the inside of the display area along a second direction to form the notch, the second direction is crossed with the first direction, the display area comprises a first display area and a second display area, the first display area is positioned on one side of the notch in the second direction, and the second display area is adjacent to both the notch and the first display area in the first direction; the display area further includes:
a plurality of sub-pixels arranged in an array, the plurality of sub-pixels being arranged in a pixel row along the second direction;
a plurality of scan lines extending along the second direction, one scan line driving a plurality of the sub-pixels in the same pixel row, the scan line including a first scan line in the first display area and a second scan line in the second display area, the number of the sub-pixels electrically connected to the first scan line being less than the number of the sub-pixels electrically connected to the second scan line;
the shift register comprises a first shift register and a second shift register;
the non-display area comprises a first non-display area and a second non-display area, in the second direction, the first non-display area is positioned on one side, away from the notch, of the first display area, the two second non-display areas are respectively positioned on two sides of the second display area, the first shift register is positioned in the first non-display area, and the second shift register is positioned in the second non-display area;
one of the first scanning lines is electrically connected to one of the first shift registers;
two ends of one second scanning line are respectively and electrically connected to two second shift registers respectively positioned in two second non-display areas;
the scanning line comprises a wire walking part and a grid part, wherein the grid part is used as a grid electrode of the switching tube, the line width of the grid part of the first scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the wire walking part of the first scanning line is larger than the line width of the wire walking part of the second scanning line;
the display panel further comprises a power line extending along the first direction, and the display panel further comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor, and the power line is connected with the driving transistor and used for generating driving current;
the power line and the scanning line are overlapped in an insulating mode, and the area of the power line overlapped in the insulating mode with the first scanning line is smaller than or equal to the area of the power line overlapped in the insulating mode with the second scanning line.
2. The display panel according to claim 1,
the scanning lines comprise a first scanning line and a second scanning line, one first scanning line and one second scanning line drive a plurality of sub-pixels in the same pixel row together, in the pixel circuit, the first scanning line provides an effective level signal in an initialization stage, and the second scanning line provides an effective level signal in a data writing stage;
the first scanning line comprises a first scanning line A and a first scanning line B, and the second scanning line comprises a second scanning line A and a second scanning line B;
the line width of the gate part of the first scanning line is equal to the line width of the gate part of the second scanning line, and the line width of the routing part of the first scanning line is different from the line width of the routing part of the second scanning line; and the line width of the grid part of the first second scanning line is equal to the line width of the grid part of the second scanning line, and the line width of the routing part of the first second scanning line is different from the line width of the routing part of the second scanning line.
3. The display panel according to claim 1,
the part of the power line, which is in insulation overlapping with the first scanning line, is a first overlapping part, the part of the power line, which is in insulation overlapping with the second scanning line, is a second overlapping part, and the line width of the first overlapping part is smaller than that of the second overlapping part.
4. The display panel according to claim 1,
the data line and the scanning line are overlapped in an insulation mode, the part, overlapped in an insulation mode, of the first scanning line and the data line is a third overlapping portion, the part, overlapped in an insulation mode, of the second scanning line and the data line is a fourth overlapping portion, and the line width of the third overlapping portion is smaller than the line width of the fourth overlapping portion.
5. The display panel according to claim 4,
the length of the data line is d, wherein d is more than or equal to 100 mm.
6. A display device characterized by comprising the display panel according to any one of claims 1 to 5.
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| CN110718575B (en) * | 2019-10-22 | 2022-08-23 | 京东方科技集团股份有限公司 | Transparent OLED display panel, display device and driving method |
| CN114067738B (en) * | 2020-07-31 | 2023-11-28 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN112767870B (en) * | 2021-01-29 | 2022-06-17 | 武汉天马微电子有限公司 | Display panel and display device |
| US20230413629A1 (en) * | 2021-06-30 | 2023-12-21 | Hefei Boe Joint Technology Co.,Ltd. | Display Substrate, Manufacturing Method Therefor, and Display Device |
| CN114613332B (en) * | 2022-03-01 | 2023-05-12 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107481669A (en) * | 2017-09-08 | 2017-12-15 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108447439A (en) * | 2018-05-14 | 2018-08-24 | 昆山国显光电有限公司 | Array substrate, display screen and display device |
| CN108598139A (en) * | 2018-06-26 | 2018-09-28 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108646477A (en) * | 2018-03-27 | 2018-10-12 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
| CN108807488A (en) * | 2018-06-29 | 2018-11-13 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108962176A (en) * | 2018-08-15 | 2018-12-07 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel and display device |
-
2019
- 2019-01-29 CN CN201910087930.8A patent/CN109637374B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107481669A (en) * | 2017-09-08 | 2017-12-15 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108646477A (en) * | 2018-03-27 | 2018-10-12 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
| CN108447439A (en) * | 2018-05-14 | 2018-08-24 | 昆山国显光电有限公司 | Array substrate, display screen and display device |
| CN108598139A (en) * | 2018-06-26 | 2018-09-28 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108807488A (en) * | 2018-06-29 | 2018-11-13 | 武汉天马微电子有限公司 | Display panel and display device |
| CN108962176A (en) * | 2018-08-15 | 2018-12-07 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel and display device |
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Effective date of registration: 20211019 Address after: No.8, liufangyuanheng Road, Donghu New Technology Development Zone, Wuhan City, Hubei Province, 430074 Patentee after: WUHAN TIANMA MICROELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201 Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. |