CN109634664B - Method and device for CPU to issue command descriptor to hardware circuit - Google Patents
Method and device for CPU to issue command descriptor to hardware circuit Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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Abstract
The invention discloses a method and a device for issuing command descriptors to a hardware circuit by a CPU (Central processing Unit), wherein the method comprises the following steps: reading the command descriptor in the ring FIFO command slot; executing corresponding instruction operation according to the current command descriptor; judging whether the current command descriptor is marked with a next command descriptor to be executed; if yes, returning to the step of reading the command descriptor in the ring-shaped first-in first-out command slot; if not, entering an inquiry waiting period; after the query waiting period, querying whether the current command descriptor has a new command descriptor to be executed; if yes, returning to the step of reading the command descriptor in the ring-shaped first-in first-out command slot; if not, judging whether the hardware circuit is stopped by the CPU, if so, finishing reading the command descriptor; if not, returning to the step of entering the query waiting period. The invention reduces the interaction between the CPU and the hardware circuit, improves the running efficiency of the CPU and saves the memory resource.
Description
Technical Field
The invention relates to a data processing method, in particular to a method and a device for issuing a command descriptor to a hardware circuit by a CPU.
Background
In the prior art, there are two general ways for a CPU to issue a command descriptor to a hardware circuit, one is a single command issuing way, and the other is a command linked list way. Single command issuing mode:
as shown in fig. 1, for the cmd0, the CPU needs to issue an address stored in the memory by the cmd0 to the circuit block0, and the same CPU needs to issue the cmd1 and the storage address of the cmd2 to the circuit block0, which indicates how many addresses need to be issued for how many commands. The CPU belongs to a high speed circuit and frequent access to the low speed circuit via the bus can slow down the CPU performance.
In the command chain table mode, as shown in fig. 2, for cmd0, the CPU needs to issue an address stored in the memory by cmd0 to the circuit block0, but the CPU does not need to issue a storage address of cmd1 and cmd2 to the circuit block0, because the storage address of cmd1 is already given in the command descriptor of cmd0, and the address of cmd2 is stored in the command descriptor of cmd1, the CPU only needs to send the first command descriptor address of the chain table to the hardware circuit. Therefore, each linked list only needs to issue an address once, so that compared with a single-command issuing mode, the times of accessing a low-speed circuit by a CPU are greatly reduced, the running efficiency of the CPU is improved, but a pointer pointing to the next command descriptor is added to the command descriptor, and for a 4GB memory space, the pointer generally needs 32bits, so that the memory resource consumption is increased.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method and a device for issuing a command descriptor to a hardware circuit by a CPU.
In order to achieve the purpose, the invention adopts the following technical scheme: a method of a CPU issuing command descriptors to hardware circuits, the method comprising:
reading the command descriptor in the ring FIFO command slot;
executing corresponding instruction operation according to the current command descriptor;
judging whether the current command descriptor is marked with a next command descriptor to be executed;
if yes, returning to the step of reading the command descriptor in the ring-shaped first-in first-out command slot;
if not, entering an inquiry waiting period;
after the query waiting period, querying whether the current command descriptor has a new command descriptor to be executed;
if yes, returning to the step of reading the command descriptor in the ring-shaped first-in first-out command slot;
if not, judging whether the hardware circuit is stopped by the CPU;
if yes, ending reading the command descriptor;
if not, returning to the step of entering the query waiting period.
The further technical scheme is as follows: before the step of reading the command descriptor in the ring FIFO command slot, the method comprises the following steps:
configuring a start address and an end address of an annular first-in first-out command slot in a memory, and writing address information of the start address and the end address into an internal register of a hardware circuit;
configuring a hardware circuit query waiting period, and writing the query waiting period into an internal register of the hardware circuit;
the CPU writes a command descriptor to be executed from the initial address of the annular first-in first-out command slot in the memory;
judging whether the current command descriptor is written to the end address;
if yes, looping a command descriptor after the current command descriptor back to the initial address for writing.
The further technical scheme is as follows: the command descriptor comprises three parts, namely a command field, a completion state field and a linked list marking field; the command field is filled in by the CPU and used for representing command information for the hardware circuit to obtain and analyze, the completion state field is filled in by the hardware circuit and used for representing the execution result of the hardware circuit, and the linked list marking field is filled in by the CPU and used for representing whether the command descriptor to be executed exists after the current command descriptor.
The further technical scheme is as follows: the step of executing the corresponding instruction operation according to the current command descriptor specifically includes the following steps:
acquiring a command field of a current command descriptor;
executing the specified command operation according to the command field;
the execution results are written back into the completion status field of the current command descriptor.
The further technical scheme is as follows: the step of determining whether the current command descriptor is marked with a next command descriptor to be executed specifically includes the following steps:
acquiring a linked list mark field of a current command descriptor;
judging whether a mark exists in a linked list mark field;
if yes, judging that the next command descriptor to be executed exists in the annular first-in first-out command slot;
if not, the next command descriptor to be executed does not exist in the ring FIFO command slot.
A CPU sends a command descriptor to a hardware circuit, and the device comprises a reading unit, an execution unit, a first judgment unit, a waiting unit, an inquiry unit, a second judgment unit and an end unit;
the reading unit is used for reading the command descriptor in the annular first-in first-out command slot;
the execution unit is used for executing corresponding instruction operation according to the current command descriptor;
the first judging unit is used for judging whether the current command descriptor is marked with a next command descriptor to be executed;
the waiting unit is used for entering an inquiry waiting period;
the query unit is used for querying whether the current command descriptor has a new command descriptor to be executed after the query waiting period;
the second judging unit judges whether the hardware circuit is stopped by the CPU;
the ending unit is used for ending the reading command descriptor.
The further technical scheme is as follows: the device also comprises a first configuration unit, a second configuration unit, a first writing unit, a third judgment unit and a loopback unit;
the first configuration unit is used for configuring the start address and the end address of an annular first-in first-out command slot in the memory and writing the address information of the start address and the end address into an internal register of the hardware circuit;
the second configuration unit is used for configuring the query waiting period of the hardware circuit and writing the query waiting period into an internal register of the hardware circuit;
the first writing unit is used for writing the command descriptor to be executed from the initial address of the annular first-in first-out command slot in the memory by the CPU;
the third judging unit is used for judging whether the current command descriptor is written to the end address;
the loop-back unit is used for looping back a command descriptor after the current command descriptor to the initial address for writing.
The further technical scheme is as follows: the command descriptor comprises three parts, namely a command field, a completion state field and a linked list marking field; the command field is filled in by the CPU and used for representing command information for the hardware circuit to obtain and analyze, the completion state field is filled in by the hardware circuit and used for representing the execution result of the hardware circuit, and the linked list marking field is filled in by the CPU and used for representing whether the command descriptor to be executed exists after the current command descriptor.
The further technical scheme is as follows: the execution unit comprises a first acquisition module, an execution module and a write-back module;
the first obtaining module is used for obtaining a command field of a current command descriptor;
the execution module is used for executing the specified command operation according to the command field;
and the write-back module is used for writing the execution result back to the completion state field of the current command descriptor.
The further technical scheme is as follows: the first judging unit comprises a second obtaining module and a judging module;
the second obtaining module is used for obtaining a linked list mark field of the current command descriptor;
and the judging module is used for judging whether the linked list mark field has a mark or not.
Compared with the prior art, the invention has the beneficial effects that: the annular first-in first-out command slot adopted in the method and the device for issuing the command descriptor to the hardware circuit by the CPU has the advantage of a command chain table, and a series of commands can be sequentially executed by starting the hardware circuit once, so that the interaction between the CPU and the hardware circuit is reduced, and the running efficiency of the CPU is improved. And the adoption of the annular first-in first-out command slot does not need to use a linked list pointer, thereby saving the memory resource. In addition, after the CPU generates a new command by calculation, the hardware circuit is not required to be triggered to execute the new command, the hardware circuit can periodically inquire the linked list mark according to the set inquiry waiting period, and if the new command is found, the linked list mark can be automatically executed, so that the interaction between the CPU and the hardware circuit is further reduced, and the running efficiency of the CPU is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more apparent, the following detailed description will be given of preferred embodiments.
Drawings
FIG. 1 is a diagram illustrating a single command issue method in the prior art;
FIG. 2 is a diagram illustrating a command chain table manner in the prior art;
FIG. 3 is a diagram illustrating an embodiment of a method for issuing a command descriptor to a hardware circuit by a CPU according to the present invention;
FIG. 4 is a diagram of a loop FIFO command slot in an embodiment of the method for a CPU to issue command descriptors to hardware circuits according to the present invention;
FIG. 5 is a schematic diagram illustrating the generation of a command descriptor in an embodiment of a method for issuing a command descriptor to a hardware circuit by a CPU according to the present invention;
FIG. 6 is a first flowchart illustrating a method for issuing command descriptors to a hardware circuit by a CPU according to an embodiment of the present invention;
FIG. 7 is a flowchart II illustrating a method for issuing a command descriptor to a hardware circuit by a CPU according to an embodiment of the present invention;
FIG. 8 is a flowchart III of a method for issuing a command descriptor to a hardware circuit by a CPU according to a specific embodiment of the present invention;
FIG. 9 is a flowchart of a fourth embodiment of a method for issuing command descriptors to a hardware circuit by a CPU according to the present invention;
FIG. 10 is a first block diagram of an embodiment of a device for issuing command descriptors to a hardware circuit by a CPU according to the present invention;
FIG. 11 is a block diagram of a second embodiment of the apparatus for issuing command descriptors to hardware circuits by a CPU according to the present invention;
FIG. 12 is a block diagram of an execution unit in an embodiment of an apparatus for issuing command descriptors to hardware circuits by a CPU of the present invention;
FIG. 13 is a diagram of a first determining unit in an embodiment of an apparatus for issuing command descriptors to a hardware circuit by a CPU according to the present invention.
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
It is to be understood that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity/action/object from another entity/action/object without necessarily requiring or implying any actual such relationship or order between such entities/actions/objects.
It should be further understood that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
As shown in fig. 3 to 9, the present invention provides a method for a CPU to issue a command descriptor to a hardware circuit, the method comprising:
s10, reading the command descriptor in the ring FIFO command slot;
s20, executing corresponding instruction operation according to the current command descriptor;
s30, judging whether the current command descriptor is marked with a next command descriptor to be executed; if yes, return to step S10; if not, S40, entering an inquiry waiting period;
s50, after the inquiry waiting period, inquiring whether the current command descriptor has a new command descriptor to be executed; if yes, return to step S10; if not, S60, judging whether the hardware circuit is stopped by the CPU;
if yes, S70, ending the reading command descriptor;
if not, the process returns to step S40.
Specifically, the meaning of a circular FIFO (first in first out) command slot is: the CPU starts to write command descriptors from an initial address under the instruction of a program, one command descriptor after another without a gap in the middle, loops back after writing to an end address, and writes from the initial address again; the hardware circuit fetches the command descriptors from the starting address, one by one, loops back after fetching the ending address, and fetches from the starting address again. The command descriptor comprises three parts, namely a command field, a completion state field and a linked list marking field; the command field is filled in by the CPU and used for representing command information for the hardware circuit to obtain and analyze, the completion state field is filled in by the hardware circuit and used for representing the execution result of the hardware circuit, and the linked list marking field is filled in by the CPU and used for representing whether the command descriptor to be executed exists after the current command descriptor.
The annular FIFO command slot structure has the advantages of a command chain table, and a hardware circuit can be started once to sequentially execute a string of commands, so that the interaction between a CPU and the hardware circuit is reduced, and the running efficiency of the CPU is improved. Compared with the traditional command linked list structure, the annular FIFO command slot structure saves linked list pointers, thereby saving memory resources.
After the CPU generates a new command by calculation, the hardware circuit does not need to be triggered to execute the new command, the hardware circuit inquires the linked list mark periodically and finds that the new command can be automatically executed, so that the interaction between the CPU and the hardware circuit is further reduced, and the running efficiency of the CPU is improved.
For step S10, when the CPU starts the hardware circuit circular block0, the hardware circuit circular block0 reads the command field and the linked list flag field of the first cmd0 from the high speed memory through the bus according to the address specified by the internal start addr register.
In certain embodiments, the steps are preceded by the steps of:
s1, configuring the start address and the end address of an annular first-in first-out command slot in the memory, and writing the address information of the start address and the end address into an internal register of the hardware circuit;
s2, configuring a hardware circuit query waiting period, and writing the query waiting period into an internal register of the hardware circuit;
s3, writing the command descriptor to be executed from the initial address of the annular first-in first-out command slot in the memory by the CPU;
s4, judging whether the current command descriptor is written to the end address; if yes, S5, looping back a command descriptor after the current command descriptor to the initial address for writing; if not, the next command descriptor is written at an address immediately following the address at which the previous command descriptor was written.
Specifically, the CPU initializes the hardware circuit, configures the start address and the end address of the ring FIFO command slot in the memory, writes these two address information into the hardware circuit internal registers (e.g., the start addr register and the end addr register in the circuit block0 shown in fig. 3), and configures the hardware circuit query latency, and writes this query latency into the hardware circuit internal registers (e.g., the waiting time register in the circuit block0 shown in fig. 3).
The CPU writes the cmd0, cmd1, cmd2 command descriptors to be executed from the start address of the ring FIFO command slot in the high speed memory. The ring FIFO command slot command generation diagram at the time of T0 is shown in FIG. 5, and there are three commands in total, the linked list label of cmd0 represents that cmd1 exists after cmd0, the linked list label of cmd1 represents that cmd2 exists after cmd1, and the linked list label of cmd2 represents that no command exists after cmd 2.
Further, step S20 specifically includes the following steps:
s201, acquiring a command field of a current command descriptor;
s202, executing specified command operation according to the command field;
s203, writing the execution result back to the completion status field of the current command descriptor.
Specifically, the hardware circuitry performs the specified command operation according to the command field of the cmd0, and then writes the execution result of the cmd0 back to the completion status field of the cmd0 via the bus.
Further, step S30 specifically includes the following steps:
s301, acquiring a linked list mark field of the current command descriptor;
s302, judging whether a mark exists in a linked list mark field or not;
if yes, S303, judging that the next command descriptor to be executed exists in the annular first-in first-out command slot;
if not, S304, it is determined that the next command descriptor to be executed does not exist in the ring FIFO command slot.
Specifically, the hardware circuit checks the linked list mark field of the cmd0 acquired before, and if the field is found to be 1, the command to be executed exists in the next command slot of the ring FIFO, so that the hardware circuit reads the command field and the linked list mark field of the cmd1 through the bus, and executes the specified command operation and the write-back completion state field according to the command field; and the process is circulated. When the hardware circuit reads the command field and the linked list mark field of the cmd2, executes and writes back the completion state field, and finds that the linked list mark field is 0, it indicates that the next command slot of the ring FIFO has no command to be executed, and then stops fetching new commands until the first batch of commands cmd 0-cmd 2 are executed.
In addition, for example, there is a new batch of commands issued: at time t0+ Δ t, the CPU needs to issue a new command, as shown in the schematic diagram of command generation in fig. 5, the CPU continues to write cmd3, cmd4 command descriptors into the ring FIFO command slot, and modifies the linked list flag of cmd2 to 1. The behavior of the hardware circuit at this time is divided into two cases:
first, if at time t0+ Δ t, when the CPU modifies the chain table flag of cmd2 to 1, the hardware circuit has not read the command field and the chain table flag field of cmd2, and after the hardware circuit executes cmd1, the hardware circuit will naturally read the command field and the chain table flag field of cmd2, so as to see that the chain table flag of cmd2 is 1, and know that cmd3 is to be executed after cmd 2.
Secondly, if the CPU modifies the link flag of cmd2 to 1 at time t0+ Δ t, and the hardware circuit has already read the command field and link flag field of cmd2, the hardware circuit does not consider the presence of cmd3 because the previously seen cmd2 link flag is 0, but the hardware circuit will wait for a certain time (query waiting period) and then read the link flag of cmd2 again, so the link flag of cmd2 always becomes 1, and the presence of cmd3 is known at this time.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Corresponding to the method for issuing the command descriptor to the hardware circuit by the CPU in the above embodiment, the present invention also provides a device for issuing the command descriptor to the hardware circuit by the CPU. As shown in fig. 3-5 and 10-12, the apparatus includes a reading unit 10, an executing unit 20, a first determining unit 30, a waiting unit 40, an inquiring unit 50, a second determining unit 60, and an ending unit 70;
a reading unit 10 for reading command descriptors in the ring FIFO command slot;
an execution unit 20, configured to execute a corresponding instruction operation according to the current command descriptor;
a first judging unit 30, configured to judge whether the current command descriptor is marked with a next command descriptor to be executed;
a waiting unit 40 for entering a query waiting period;
the query unit 50 is configured to query whether the current command descriptor has a new command descriptor to be executed after the query waiting period;
a second judgment unit 60 that judges whether or not the hardware circuit is stopped by the CPU;
an ending unit 70 for ending the read command descriptor.
Specifically, the meaning of a circular FIFO (first in first out) command slot is: the CPU starts to write command descriptors from an initial address under the instruction of a program, one command descriptor after another without a gap in the middle, loops back after writing to an end address, and writes from the initial address again; the hardware circuit fetches the command descriptors from the starting address, one by one, loops back after fetching the ending address, and fetches from the starting address again. The command descriptor comprises three parts, namely a command field, a completion state field and a linked list marking field; the command field is filled in by the CPU and used for representing command information for the hardware circuit to obtain and analyze, the completion state field is filled in by the hardware circuit and used for representing the execution result of the hardware circuit, and the linked list marking field is filled in by the CPU and used for representing whether the command descriptor to be executed exists after the current command descriptor.
The annular FIFO command slot structure has the advantages of a command chain table, and a hardware circuit can be started once to sequentially execute a string of commands, so that the interaction between a CPU and the hardware circuit is reduced, and the running efficiency of the CPU is improved. Compared with the traditional command linked list structure, the annular FIFO command slot structure saves linked list pointers, thereby saving memory resources.
After the CPU generates a new command by calculation, the hardware circuit does not need to be triggered to execute the new command, the hardware circuit inquires the linked list mark periodically and finds that the new command can be automatically executed, so that the interaction between the CPU and the hardware circuit is further reduced, and the running efficiency of the CPU is improved.
When the CPU starts the hardware circuit circular block0, the hardware circuit circular block0 reads the command field and the linked list tag field of the first cmd0 from the high-speed memory through the bus according to the address specified by the internal start addr register.
In some embodiments, the apparatus further includes a first configuration unit 1, a second configuration unit 2, a first writing unit 3, a third determination unit 4, and a loopback unit 5;
the first configuration unit 1 is used for configuring a start address and an end address of an annular first-in first-out command slot in a memory, and writing address information of the start address and the end address into an internal register of a hardware circuit;
the second configuration unit 2 is used for configuring the query waiting period of the hardware circuit and writing the query waiting period into an internal register of the circuit;
a first writing unit 3, configured to write, by the CPU, a command descriptor to be executed from a start address of the ring fifo command slot in the memory;
a third judgment unit 4 for judging whether the current command descriptor is written to the end address;
and a loopback unit 5, configured to loop back a command descriptor following the current command descriptor to the start address for writing.
Specifically, the CPU initializes the hardware circuit, configures the start address and the end address of the ring FIFO command slot in the memory, writes these two address information into the hardware circuit internal registers (e.g., the start addr register and the end addr register in the circuit block0 shown in fig. 3), and configures the hardware circuit query latency, and writes this query latency into the hardware circuit internal registers (e.g., the waiting time register in the circuit block0 shown in fig. 3).
The CPU writes the cmd0, cmd1, cmd2 command descriptors to be executed from the start address of the ring FIFO command slot in the high speed memory. The ring FIFO command slot state command generation diagram at the time of T0 is shown in FIG. 5, and there are three commands in total, the linked list of cmd0 is marked as 1 to represent that cmd1 exists after cmd0, the linked list of cmd1 is marked as 1 to represent that cmd2 exists after cmd1, and the linked list of cmd2 is marked as 0 to represent that no command exists after cmd 2.
The command descriptor comprises three parts, namely a command field, a completion state field and a linked list marking field; the command field is filled in by the CPU and used for representing command information for the hardware circuit to obtain and analyze, the completion state field is filled in by the hardware and used for representing the execution result of the hardware circuit, and the linked list marking field is filled in by the CPU and used for representing whether the command descriptor to be executed exists after the current command descriptor.
Further, the execution unit 20 includes a first obtaining module 201, an executing module 202, and a write-back module 203;
a first obtaining module 201, configured to obtain a command field of a current command descriptor;
an execution module 202, configured to execute a specified command operation according to the command field;
a write-back module 203 for writing back the execution result to the completion status field of the current command descriptor.
Specifically, the hardware circuitry performs the specified command operation according to the command field of the cmd0, and then writes the execution result of the cmd0 back to the completion status field of the cmd0 via the bus.
Further, the first determining unit 30 includes a second obtaining module 301 and a determining module 302;
a second obtaining module 301, configured to obtain a linked list flag field of a current command descriptor;
a judging module 302, configured to judge whether a flag exists in the linked list flag field.
Specifically, the hardware circuit checks the linked list mark field of the cmd0 acquired before, and if the field is found to be 1, the command to be executed exists in the next command slot of the ring FIFO, so that the hardware circuit reads the command field and the linked list mark field of the cmd1 through the bus, and executes the specified command operation and the write-back completion state field according to the command field; and the process is circulated. When the hardware circuit reads the command field and the linked list mark field of the cmd2, executes and writes back the completion state field, and finds that the linked list mark field is 0, it indicates that the next command slot of the ring FIFO has no command to be executed, and then stops fetching new commands until the first batch of commands cmd 0-cmd 2 are executed.
In addition, for example, there is a new batch of commands issued: at time t0+ Δ t, the CPU needs to issue a new command, as shown in the schematic diagram of command generation in fig. 5, the CPU continues to write cmd3, cmd4 command descriptors into the ring FIFO command slot, and modifies the linked list flag of cmd2 to 1. The behavior of the hardware circuit at this time is divided into two cases:
first, if at time t0+ Δ t, when the CPU modifies the chain table flag of cmd2 to 1, the hardware circuit has not read the command field and the chain table flag field of cmd2, and after the hardware circuit executes cmd1, the hardware circuit will naturally read the command field and the chain table flag field of cmd2, so as to see that the chain table flag of cmd2 is 1, and know that cmd3 is to be executed after cmd 2.
Secondly, if the CPU modifies the link flag of cmd2 to 1 at time t0+ Δ t, and the hardware circuit has already read the command field and link flag field of cmd2, the hardware circuit does not consider the presence of cmd3 because the previously seen cmd2 link flag is 0, but the hardware circuit will wait for a certain time (query waiting period) and then read the link flag of cmd2 again, so the link flag of cmd2 always becomes 1, and the presence of cmd3 is known at this time.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present invention may be implemented in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the above-mentioned apparatus may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical functional division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another device, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (2)
1. A method for a CPU to issue a command descriptor to a hardware circuit, the method comprising:
reading the command descriptor in the ring FIFO command slot;
executing corresponding instruction operation according to the current command descriptor;
judging whether the current command descriptor is marked with a next command descriptor to be executed;
if yes, returning to the step of reading the command descriptor in the ring-shaped first-in first-out command slot;
if not, entering an inquiry waiting period;
after the query waiting period, querying whether the current command descriptor has a new command descriptor to be executed;
if yes, returning to the step of reading the command descriptor in the ring-shaped first-in first-out command slot;
if not, judging whether the hardware circuit is stopped by the CPU;
if yes, ending reading the command descriptor;
if not, returning to the step of entering the query waiting period;
before the step of reading the command descriptor in the ring FIFO command slot, the method comprises the following steps:
configuring a start address and an end address of an annular first-in first-out command slot in a memory, and writing address information of the start address and the end address into an internal register of a hardware circuit;
configuring a hardware circuit query waiting period, and writing the query waiting period into an internal register of the hardware circuit;
the CPU writes a command descriptor to be executed from the initial address of the annular first-in first-out command slot in the memory;
judging whether the current command descriptor is written to the end address;
if yes, looping back a command descriptor behind the current command descriptor to the initial address for writing;
the command descriptor comprises three parts, namely a command field, a completion state field and a linked list marking field; the command field is filled in by the CPU and used for representing command information for the hardware circuit to obtain and analyze, the completion state field is filled in by the hardware and used for representing the execution result of the hardware circuit, and the linked list mark field is filled in by the CPU and used for representing whether a command descriptor to be executed exists after the current command descriptor;
the step of executing the corresponding instruction operation according to the current command descriptor specifically includes the following steps:
acquiring a command field of a current command descriptor;
executing the specified command operation according to the command field;
writing the execution result back into the completion status field of the current command descriptor;
the step of determining whether the current command descriptor is marked with a next command descriptor to be executed specifically includes the following steps:
acquiring a linked list mark field of a current command descriptor;
judging whether a mark exists in a linked list mark field;
if yes, judging that the next command descriptor to be executed exists in the annular first-in first-out command slot;
if not, the next command descriptor to be executed does not exist in the ring FIFO command slot.
2. A device for issuing command descriptors to a hardware circuit by a CPU is characterized by comprising a reading unit, an execution unit, a first judgment unit, a waiting unit, an inquiry unit, a second judgment unit and an end unit;
the reading unit is used for reading the command descriptor in the annular first-in first-out command slot;
the execution unit is used for executing corresponding instruction operation according to the current command descriptor;
the first judging unit is used for judging whether the current command descriptor is marked with a next command descriptor to be executed;
the waiting unit is used for entering an inquiry waiting period;
the query unit is used for querying whether the current command descriptor has a new command descriptor to be executed after the query waiting period;
the second judging unit judges whether the hardware circuit is stopped by the CPU;
the ending unit is used for ending the reading command descriptor;
the device also comprises a first configuration unit, a second configuration unit, a first writing unit, a third judgment unit and a loopback unit;
the first configuration unit is used for configuring the start address and the end address of an annular first-in first-out command slot in the memory and writing the address information of the start address and the end address into an internal register of the hardware circuit;
the second configuration unit is used for configuring the query waiting period of the hardware circuit and writing the query waiting period into an internal register of the hardware circuit;
the first writing unit is used for writing the command descriptor to be executed from the initial address of the annular first-in first-out command slot in the memory by the CPU;
the third judging unit is used for judging whether the current command descriptor is written to the end address;
the loopback unit is used for looping back a command descriptor after the current command descriptor to the initial address for writing;
the command descriptor comprises three parts, namely a command field, a completion state field and a linked list marking field; the command field is filled in by the CPU and used for representing command information for the hardware circuit to obtain and analyze, the completion state field is filled in by the hardware circuit and used for representing the execution result of the hardware circuit, and the linked list mark field is filled in by the CPU and used for representing whether a command descriptor to be executed exists after the current command descriptor;
the execution unit comprises a first acquisition module, an execution module and a write-back module;
the first obtaining module is used for obtaining a command field of a current command descriptor;
the execution module is used for executing the specified command operation according to the command field;
the write-back module is used for writing the execution result back to the completion state field of the current command descriptor;
the first judging unit comprises a second obtaining module and a judging module;
the second obtaining module is used for obtaining a linked list mark field of the current command descriptor;
and the judging module is used for judging whether the linked list mark field has a mark or not.
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| CN110096918B (en) * | 2019-04-28 | 2022-01-21 | 深圳忆联信息系统有限公司 | Method and system for improving NFC descriptor state checking efficiency |
| CN112015527B (en) * | 2019-05-29 | 2024-03-22 | 闪迪技术有限公司 | Managing fetching and executing commands from a commit queue |
| CN110471624A (en) * | 2019-08-07 | 2019-11-19 | 深圳忆联信息系统有限公司 | SSD reads accelerated method, device, computer equipment and the storage medium retried |
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