CN109616409A - A kind of polysilicon deposition method, flash memory and preparation method thereof - Google Patents
A kind of polysilicon deposition method, flash memory and preparation method thereof Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 137
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 133
- 238000000151 deposition Methods 0.000 title claims abstract description 97
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 230000008021 deposition Effects 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000007667 floating Methods 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 23
- 239000013078 crystal Substances 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000011265 semifinished product Substances 0.000 description 6
- 239000011800 void material Substances 0.000 description 5
- 238000011049 filling Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000004627 transmission electron microscopy Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
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Abstract
The application provides a kind of polysilicon deposition method, flash memory and preparation method thereof, wherein polysilicon deposition method includes: to carry out polysilicon primary depositing on the substrate of biggish first groove relative to opening size with bottom size, gap is generated after primary depositing, it performs etching again, clearance position is etched to form opening relative to biggish second groove in bottom, it is deposited again, to fill gap.Multiple polysilicon deposition can also be carried out in the embodiment of the present invention, until there is no gaps namely gap all to be filled by polysilicon in the first groove, to improve the electrical property and yield of flash memory.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology field more particularly to a kind of polysilicon deposition method, flash memory and its
Production method.
Background technique
In flash memory manufacture craft, it is floating gate that the selection of grid, which has a kind of mainstream,；Floating gate usually selects un-doped polysilicon,
By boiler tube deposition, ion implanting, annealing and CMP (Chemical Mechanical Polish, chemical mechanical grinding) etc. one
Series of processes must reach the FGS floating gate structure and performance of requirement.
But polysilicon can generate gap after the series of process process such as deposition, ion implanting, annealing and CMP,
There is gap to will affect electrically and reduce yield in polysilicon.
Summary of the invention
In view of this, the present invention provides a kind of polysilicon deposition method, flash memory and preparation method thereof, to solve the prior art
Gap is generated in middle polysilicon, causes flash memory electrically variation and the lower problem of yield.
To achieve the above object, the invention provides the following technical scheme:
A kind of polysilicon deposition method, comprising:
Substrate is provided, the substrate includes first surface, and the first surface is formed with the first groove, is parallel to institute on edge
It states in the section of first surface, the opening for being greater than first groove there are the area of section of the first groove described at least one exists
Area on the first surface；
Polysilicon primary depositing is carried out on the first surface of the substrate, forms polysilicon layer to be etched；
It etches the polysilicon layer to be etched in first groove, forms the second groove, along being parallel to described the
In the section on one surface, along the direction for deviating from the substrate, the area of section of second groove is gradually increased or described second
The side wall of groove is perpendicular to the first surface；
Polysilicon secondary deposition is carried out in the substrate surface for being formed with second groove；
Judge with the presence or absence of gap in first groove, if so, the polycrystalline that the polysilicon secondary deposition is formed
Silicon layer returns to the polysilicon layer to be etched in etching first groove as polysilicon layer to be etched, forms the
The step of two grooves, until first groove is completely filled.
Preferably, described to carry out polysilicon primary depositing on the first surface of the substrate and be formed with described second
The technique that the substrate surface of groove carries out the use of polysilicon secondary deposition is identical.
Preferably, the concrete technology that uses of polysilicon primary depositing that carries out on the first surface of the substrate is low
Pressure chemical vapor deposition.
Preferably, the polysilicon layer to be etched in first groove is etched, the second groove is formed, specifically includes:
It is passed through etching gas, the etching gas is chlorine, and etching temperature is 200 DEG C -400 DEG C, and pressure is 0-2Torr gas
Body flow is 1slm-10slm, including endpoint value performs etching the polysilicon layer to be etched in first groove, forms the
Two grooves.
Preferably, second groove is V-type groove.
Preferably, second groove is rectangular recess.
The present invention also provides a kind of preparation method for flash memory, comprising:
Semiconductor substrate is provided, the semiconductor substrate includes channel region, positioned at the first of the semiconductor substrate surface
Doped region and the second doped region；
Tunnel oxide is sequentially formed on the channel region surface；
Deposition forms multi-crystal silicon floating bar on the tunnel oxide；
Dielectric layer and control gate between the multi-crystal silicon floating bar sequentially forms polycrystalline away from the surface of the semiconductor substrate；
Wherein, the deposition is formed multi-crystal silicon floating bar and is formed using polysilicon deposition method described in any of the above one.
Preferably, after deposition forms multi-crystal silicon floating bar, further includes:
The multi-crystal silicon floating bar is annealed and planarized.
Preferably, the annealing uses rapid thermal anneal process, and the planarization uses chemical mechanical milling tech.
The present invention also correspondence provides a kind of flash memory, is made to be formed of preparation method for flash memory described in any of the above one；
The flash memory includes:
Semiconductor substrate, the semiconductor substrate include channel region, the first doping positioned at the semiconductor substrate surface
Area and the second doped region；
Stack gradually dielectric layer and control gate between tunnel oxide on the channel region, floating polysilicon grid layer, polycrystalline.
Preferably, the semiconductor substrate is P type substrate.
It can be seen via above technical scheme that polysilicon deposition method provided by the invention, including in opening relative to interior
Polysilicon primary depositing is carried out on the substrate of lesser first groove in portion, generates gap after primary depositing, then perform etching, it will be empty
Gap position, which etches, to form that opening is identical as bottom or opening is relative to biggish second groove in bottom, and it is heavy to carry out polysilicon again
Product, to fill gap.Multiple polysilicon deposition can also be carried out in the embodiment of the present invention, until there is no skies in the first groove
Gap namely gap are all filled by polysilicon, to promote the electrical property of flash memory and improve the yield of flash memory.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the substrat structure schematic diagram provided in the prior art；
Fig. 2 is the flash memory semi-finished product structure schematic diagram after the completion of polysilicon deposition in the prior art；
Fig. 3 is the flash memory semi-finished product structure schematic diagram after annealing in the prior art；
Fig. 4 is the flash memory semi-finished product structure schematic diagram after planarizing in the prior art；
Fig. 5 is a kind of polysilicon deposition method flow schematic diagram provided in an embodiment of the present invention；
Fig. 6-Figure 12 is polysilicon deposition method and process block diagram provided in an embodiment of the present invention；
Figure 13 is the preparation method for flash memory flow chart provided in the embodiment of the present invention；
Figure 14 is a kind of flash memory structure schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Just as described in the background section, polysilicon in the production process, is easy to appear gap in the prior art, thus shadow
Ring the electrical property and yield of flash memory.
Inventors have found that the reason of above-mentioned phenomenon occur is, when forming the floating gate of flash memory, the groove on substrate is opening
It is smaller, and the biggish groove in bottom, as shown in FIG. 1, FIG. 1 is a kind of substrat structure schematic diagrames, due to the groove 011 on substrate 01
Shape limits, and when leading to carry out polysilicon deposition in groove 011, will cause inside grooves, there are no fillings to finish polysilicon
02, the polysilicon of part has sealed on groove, to form gap 012 in groove 011, refers to Fig. 2, Fig. 2 is polycrystalline
Flash memory semi-finished product structure schematic diagram after the completion of siliceous deposits；Although subsequent by annealing, gap 012 can be repaired a part, empty
012 size reduction of gap, refers to Fig. 3, and Fig. 3 is the flash memory semi-finished product structure schematic diagram after annealing；But it is subsequent by planarization
It when technique, generallys use CMP and is planarized, lapping liquid can also corrode gap during corroding polycrystal layer, lead
It causes gap 012 to become larger, refers to Fig. 4, Fig. 4 is the flash memory semi-finished product structure schematic diagram after planarization.After being subsequently formed flash memory,
The presence in gap influences the electrical property of flash memory, reduces the yield of flash memory.
The present invention provides a kind of polysilicon deposition method, comprising:
Substrate is provided, the substrate includes first surface, and the first surface is formed with the first groove, is parallel to institute on edge
It states in the section of first surface, the opening for being greater than first groove there are the area of section of the first groove described at least one exists
Area on the first surface；
Polysilicon primary depositing is carried out on the first surface of the substrate, forms polysilicon layer to be etched；
It etches the polysilicon layer to be etched in first groove, forms the second groove, along being parallel to described the
In the section on one surface, along the direction for deviating from the substrate, the area of section of second groove is gradually increased or described second
The side wall of groove is perpendicular to the first surface；
Polysilicon secondary deposition is carried out in the substrate surface for being formed with second groove；
Judge with the presence or absence of gap in first groove, if so, the polycrystalline that the polysilicon secondary deposition is formed
Silicon layer returns to the polysilicon layer to be etched in etching first groove as polysilicon layer to be etched, forms the
The step of two grooves, until first groove is completely filled.
Polysilicon deposition method provided by the invention is included in bottom size relative to opening size biggish first
Polysilicon primary depositing is carried out on the substrate of groove, generates gap after primary depositing, then perform etching, clearance position is etched into shape
At opening relative to biggish second groove in bottom, deposited again, to fill gap.It can be in the embodiment of the present invention
Multiple polysilicon deposition is carried out, until there is no gaps namely gap all to be filled by polysilicon in the first groove, to be promoted
The electrical property of flash memory and the yield for improving flash memory.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of polysilicon deposition method, refers to Fig. 5, and Fig. 5 is provided in an embodiment of the present invention
A kind of polysilicon deposition method flow schematic diagram；Below with reference to polysilicon deposition method and process block diagram pair shown in Fig. 6-Figure 12
The polysilicon deposition method provided in the present embodiment is described in detail.
The polysilicon deposition method provided in the embodiment of the present invention includes:
S101: providing substrate, and the substrate includes first surface, and the first surface is formed with the first groove, along flat
For row in the section of the first surface, there are the areas of section of the first groove described at least one to be greater than first groove
The area of opening on the first surface；
Fig. 6 is referred to, substrate 1 includes the upper surface in first surface namely Fig. 6, and first surface is formed with the first groove
11, it should be noted that the main reason for polysilicon deposition method gap provided in the present embodiment generates is since first is recessed
Caused by the shape of slot.Specifically, the shape of the first groove 11 is larger for bottom size, and the open-mouth ruler being located on first surface
Very little lesser structure along the section for being parallel to first surface, exists as shown in Figure 6, namely away from the direction Y of substrate
The area of section of at least one the first groove is greater than the case where opening area, is also formed opening relative to internal lesser the
One groove 11, i.e., shown in Fig. 6, opening area S2 is less than bottom area S1.
It should be noted that not limiting the concrete shape of the first groove in the present embodiment, the shape of rule can be, it can also
It to be irregular shape, is not limited this in the present embodiment, wherein regular shape can be along perpendicular to first surface
Section in be trapezoidal namely Fig. 6 shown in structure or the first groove be truncated conical shape.For convenience of description, the present embodiment
In with along on the substrate direction, the first groove is gradually reduced namely the first groove in the area of section for being parallel to first surface
Perpendicular to first surface section be it is trapezoidal for be illustrated, the first groove of other shapes is also applied for the embodiment of the present invention
The polysilicon deposition method of offer.The groove of irregular shape, can also be the rough groove of side wall, right in the present embodiment
This is not construed as limiting.As long as the opening of the first groove 11 is smaller relative to 11 inner space of the first groove, can there be deposit polycrystalline
Occurs the risk in gap during silicon.
In other embodiments, groove shapes are not along the semiconductor that on substrate direction, area of section is gradually reduced
In device fabrication processes, if necessary, polysilicon deposition method provided by the invention can also be used, does not make spy in the present embodiment
It is different to limit.
S102: polysilicon primary depositing is carried out on the first surface of the substrate, forms polysilicon layer to be etched；
The not concrete technology method of restricting poly-silicon primary depositing in the embodiment of the present invention, in one embodiment of the present of invention
In, low-pressure chemical vapor deposition (LP_CVD) can be used.
Fig. 7 is referred to, polysilicon layer 21 to be etched is formed in the entire top of the first surface of substrate, at this point, due to first
The contour limit of groove will form gap 121 in the first groove.It is unlimited in the embodiment of the present invention to be shaped as polysilicon to be etched
The thickness of layer, the first recess sidewall is different relative to the tilt angle of first surface, and interstitial situation is different, e.g., first
Angle between recess sidewall and the first groove floor is smaller, then the gradient of the first recess sidewall is larger, then polysilicon deposition
It is opposite that gap is more readily formed after filling bottom surface, and the angle worked as between the first recess sidewall and the first groove floor is larger, then
The gradient of side wall is smaller, and bottom surface polysilicon is easier to deposition filling, and the gap of formation is smaller, and compares by the upper of the first groove
Portion.
Therefore, different for the shape of the first groove, the thickness of polysilicon layer to be etched can be different in the present embodiment, to
The thickness of etches polycrystalline silicon layer is chosen as thickness when void openings just seal, or when just being sealed less than void openings
Thickness.Thickness when can also just seal less times greater than void openings does not limit this in the present embodiment.
When polysilicon layer thicknesses to be etched are thicker, as shown in Figure 7, void openings sealing；As shown in figure 8, when to be etched
When losing 21 thinner thickness of polysilicon layer, void openings are not sealed, and formation is uncovered structure 121 '.No matter which kind of structure, this
Pass through subsequent step in embodiment, gap can be filled up completely.
S103: the polysilicon layer to be etched in etching first groove forms the second groove, is parallel to institute on edge
It states in the section of first surface, along the direction for deviating from the substrate, the area of section of second groove is gradually increased or described
The side wall of second groove is perpendicular to the first surface；
The polysilicon layer to be etched in first groove is etched, the second groove is formed, specifically includes:
It is passed through etching gas, the etching gas is chlorine, and etching temperature is 200 DEG C -400 DEG C, and pressure is 0-2Torr gas
Body flow is 1slm-10slm, including endpoint value performs etching the polysilicon layer to be etched in first groove, forms the
Two grooves.Wherein, slm is gas flow unit: standard liter/min.
Wherein, the polysilicon layer to be etched in first groove is etched, the position etched is that progress polysilicon is primary
The position in the gap of sealing or opening is formed with after deposition, moreover, the second groove that etching is formed includes the gap, that is,
By forming the second groove, clearance position is extended to the second groove, then be filled to the second groove, so that gap be gone
It removes.
It should be noted that not limiting the concrete shape of the second groove in the present embodiment, institute is parallel on edge as long as meeting
It states in the section of first surface, along the direction for deviating from the substrate, the condition that the area of section of second groove is gradually increased
Namely in the present invention, opening is etched relative to biggish second groove in bottom surface, then carries out polysilicon deposition again, from
And the first groove is sufficient filling with full polysilicon gradually, it avoids generating gap.
In addition, in other embodiments of the invention, the opening of the second groove is identical as interior space shape and area, i.e.,
The side wall of second groove can also be effectively improved the deposition of polysilicon perpendicular to first surface, reduce gap and formed.
The shape for not limiting the second groove in the present embodiment, can be as shown in Figure 9, and the section of the second groove 122 is V
Type namely the second groove are V-type groove.Opening area S3 is greater than the area for being located at each section of opening lower section, and V-type second is recessed
The base area of slot is 0.Second groove 122 shown in Fig. 9 can be adapted for gap shown in Fig. 7.
Second groove can also be as shown in Figure 10, and the second groove 122 ' has the opening that area is S5 and area is S4
Bottom surface.Wherein, S4 is less than S5.In addition, the second groove can also be rectangular channel, i.e. S4 is equal to S5, as long as enabling to be open
More than or equal to the second groove of bottom surface, so that when polysilicon deposits again, can be sufficient filling in the second groove
Portion, without forming gap.
S104: polysilicon secondary deposition is carried out in the substrate surface for being formed with second groove；
Likewise, the not concrete technology of restricting poly-silicon secondary deposition in the present embodiment, can using with polysilicon successively
Identical technique is deposited, different depositing operations can also be used.Optionally, in the present embodiment, the polysilicon primary depositing
It is identical with the technique that the polysilicon secondary deposition uses.
It should be noted that the Multiple depositions of polysilicon are preferably deposited in same process, it is therefore possible to use
In-situ DEP (in situation Deposition, deposit or deposit in situ at the scene) technique is formed, in semiconductor
The inside In-situ DEP is meant, is done directly at a dass inside single board or cavity, rather than point multiple steps
Suddenly it is completed in multiple and different boards.
In the present embodiment equally not restricting poly-silicon secondary deposition when thickness, the second groove can be filled up completely, such as scheme
Shown in 11, thicker polysilicon secondary deposition layer is formed, so that the second inside grooves are completely filled.It can also be formed relatively thin
Polysilicon deposition, then carry out subsequent technique.
What the second inside grooves were completely filled described in the present embodiment is meant that, the inside of the second groove is filled up completely
Polysilicon, and generated without gap.It should be noted that in the actual production process, since manufacture craft limits, the second groove
Internal polysilicon does not accomplish theoretic absolutely not gap, but if the size in gap is smaller, does not produce to the performance of device
It is raw to influence, meet the performance requirement of device, then also falls into the protection that the second inside grooves described herein are completely filled
In range.
S105: judging with the presence or absence of gap in first groove, if so, the polysilicon secondary deposition is formed
Polysilicon layer returns to the polysilicon layer to be etched in etching first groove, shape as polysilicon layer to be etched
The step of at the second groove, until first groove is completely filled.
It should be noted that in above-mentioned steps, if the polysilicon layer thicknesses to be etched that primary depositing generates sink with secondary
In the case that long-pending polysilicon thickness is relatively thin, it is possible to by primary: polysilicon primary depositing --- it is recessed that etching forms second
Slot --- the technique of polysilicon secondary deposition is unable to complete being stuffed entirely with for the first groove, it is also possible to gap is formed, therefore, this
In embodiment judgment step can be carried out, judges whether be completely filled in the first groove after carrying out an above-mentioned steps, if
It is completely filled, does not then influence subsequent anneal and flatening process, and the performance of the flash memory formed, therefore, polysilicon deposition
Step can terminate.If still there is gap in the first groove, be repeated one or more times again: it is recessed that etching forms second
Slot --- the technique of polysilicon secondary deposition guarantees the performance of flash memory to be formed until the first groove is filled by polysilicon completely
And yield.In other embodiments of the present invention, if the thickness of polysilicon secondary deposition is also relatively thin, it can also etched again
Before, it is further added by a polysilicon deposition, this is not described in detail in the present embodiment, can be adjusted according to actual process parameter
It is whole.
Likewise, the first inside grooves described in the present embodiment are meant that by what polysilicon was filled completely, the first groove
Inside there is no gap generation.It should be noted that in the actual production process, since manufacture craft limits, in the first groove
The polysilicon in portion does not accomplish theoretic absolutely not gap, but if the size in gap is smaller, does not generate to the performance of device
It influences, meets the performance requirement of device, then also fall into the protection model that the first inside grooves described herein are completely filled
In enclosing.
The concrete technology for judging to whether there is gap in first groove is not limited in the embodiment of the present invention, optionally,
Include:
After polysilicon CMP, judged in the first groove using optical defect scanning machine scanning wafer with the presence or absence of gap.
After polysilicon deposition, using TEM (Transmission Electron Microscope transmission electron microscopy
Mirror) board slice judge to whether there is gap in the first groove.
Polysilicon deposition method provided by the invention is included in bottom size relative to opening size biggish first
Polysilicon primary depositing is carried out on the substrate of groove, generates gap after primary depositing, then perform etching, clearance position is etched into shape
At opening relative to biggish second groove in bottom, deposited again, to fill gap.It can be in the embodiment of the present invention
Multiple polysilicon deposition is carried out, until there is no gaps namely gap all to be filled by polysilicon in the first groove, to be promoted
The electrical property of flash memory and the yield for improving flash memory.
The embodiment of the present invention also provides a kind of preparation method for flash memory, and 3, Figure 13 is to mention in the embodiment of the present invention referring to Figure 1
The preparation method for flash memory flow chart of confession, the preparation method for flash memory specifically include:
S201: semiconductor substrate is provided, the semiconductor substrate includes channel region, positioned at the semiconductor substrate surface
First doped region and the second doped region；
It should be noted that the specific material of semiconductor substrate is not limited in the present embodiment, in an implementation of the invention
In example, the semiconductor substrate is silicon substrate, and to be doped with the P-type silicon substrate of impurity.First doped region and second is mixed
Miscellaneous area is the biggish region n+ of doping concentration, is being subsequently formed source area and drain region.
S202: tunnel oxide is sequentially formed on the channel region surface；
S203: deposition forms multi-crystal silicon floating bar on the tunnel oxide；
It should be noted that multi-crystal silicon floating bar is using polysilicon deposition described in above example in the embodiment of the present invention
Method is formed.To avoid generating gap in FGS floating gate structure, flash memory is caused electrically to change the problem of reducing with yield.
S204: dielectric layer and control between the multi-crystal silicon floating bar sequentially forms polycrystalline away from the surface of the semiconductor substrate
Grid processed；
In the present embodiment after deposition forms multi-crystal silicon floating bar, further include the multi-crystal silicon floating bar is carried out annealing and it is flat
Chemical industry skill does not limit the concrete technology using annealing and planarization in the present embodiment, and optionally, the annealing uses RTA
(Rapid Thermal Annealing, rapid thermal annealing) technique.The CMP process that the planarization uses.
The preparation method for flash memory provided in the embodiment of the present invention, during forming multi-crystal silicon floating bar, using of the invention real
The polysilicon deposition method applied in example is formed, and avoids occurring gap in multi-crystal silicon floating bar, so as to promote the electrical property of flash memory
And improve the yield of flash memory.
The embodiment of the present invention also provides a kind of flash memory, makes shape using preparation method for flash memory described in above example
At.4, Figure 14 is a kind of flash memory structure schematic diagram provided in an embodiment of the present invention referring to Figure 1；The flash memory includes:
Semiconductor substrate 140, the semiconductor substrate include channel region 141, positioned at 140 surface of semiconductor substrate
First doped region 142 and the second doped region 143；
It is sequentially laminated on dielectric layer 17 between the tunnel oxide 15 on the channel region 141, floating polysilicon grid layer 16, polycrystalline
With control gate 18.
The specific material of semiconductor substrate is not limited in the present embodiment, it is in one embodiment of the invention, described partly to lead
Body substrate is silicon substrate, and to be doped with the P-type silicon substrate of impurity.First doped region and the second doped region are that doping is dense
The biggish region n+ is spent, source area and drain region are being subsequently formed.
The flash memory structure provided in the present embodiment is in multi-crystal silicon floating bar manufacturing process using described in above example
Polysilicon deposition method is formed, and can be avoided and gap occurs during forming multi-crystal silicon floating bar, influence the electrical property of flash memory with
And reduce flash memory yield, thus the flash memory structure provided in the embodiment of the present invention compared with the existing technology in flash memory structure,
Do not have gap in multi-crystal silicon floating bar, yield is higher, and electrical property is more preferable.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of polysilicon deposition method characterized by comprising
Substrate is provided, the substrate includes first surface, and the first surface is formed with the first groove, along being parallel to described the
In the section on one surface, there are the areas of section of the first groove described at least one to be greater than the opening of first groove described
Area on first surface；
Polysilicon primary depositing is carried out on the first surface of the substrate, forms polysilicon layer to be etched；
The polysilicon layer to be etched in first groove is etched, the second groove is formed, is parallel to first table on edge
In the section in face, along the direction for deviating from the substrate, the area of section of second groove is gradually increased or second groove
Side wall perpendicular to the first surface；
Polysilicon secondary deposition is carried out in the substrate surface for being formed with second groove；
Judge with the presence or absence of gap in first groove, if so, the polysilicon layer that the polysilicon secondary deposition is formed
As polysilicon layer to be etched, the polysilicon layer to be etched in etching first groove is returned, it is recessed to form second
The step of slot, until first groove is completely filled.
2. polysilicon deposition method according to claim 1, which is characterized in that it is described on the first surface of the substrate
Carry out polysilicon primary depositing and described in the substrate surface for being formed with second groove progress polysilicon secondary deposition use
Technique it is identical.
3. polysilicon deposition method according to claim 2, which is characterized in that it is described on the first surface of the substrate
The concrete technology that progress polysilicon primary depositing uses is low-pressure chemical vapor deposition.
4. polysilicon deposition method according to claim 1, which is characterized in that be etched in etching first groove
Polysilicon layer forms the second groove, specifically includes:
It is passed through etching gas, the etching gas is chlorine, and etching temperature is 200 DEG C -400 DEG C, and pressure is 0-2Torr gas stream
Amount is 1slm-10slm, including endpoint value, is performed etching to the polysilicon layer to be etched in first groove, and it is recessed to form second
Slot.
5. polysilicon deposition method according to claim 1, which is characterized in that second groove is V-type groove.
6. polysilicon deposition method according to claim 1, which is characterized in that second groove is rectangular recess.
7. a kind of preparation method for flash memory characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes channel region, the first doping positioned at the semiconductor substrate surface
Area and the second doped region；
Tunnel oxide is sequentially formed on the channel region surface；
Deposition forms multi-crystal silicon floating bar on the tunnel oxide；
Dielectric layer and control gate between the multi-crystal silicon floating bar sequentially forms polycrystalline away from the surface of the semiconductor substrate；
Wherein, the deposition forms multi-crystal silicon floating bar using polysilicon deposition method shape as claimed in any one of claims 1 to 6
At.
8. preparation method for flash memory according to claim 7, which is characterized in that after deposition forms multi-crystal silicon floating bar, also wrap
It includes:
The multi-crystal silicon floating bar is annealed and planarized.
9. preparation method for flash memory according to claim 8, which is characterized in that the annealing uses rapid thermal anneal process,
The planarization uses chemical mechanical milling tech.
10. a kind of flash memory, which is characterized in that made to be formed of preparation method for flash memory described in claim 7-9 any one；
The flash memory includes:
Semiconductor substrate, the semiconductor substrate include channel region, positioned at the semiconductor substrate surface the first doped region and
Second doped region；
Stack gradually dielectric layer and control gate between tunnel oxide on the channel region, floating polysilicon grid layer, polycrystalline.
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