CN109614264B

CN109614264B - Data backup method, device and system

Info

Publication number: CN109614264B
Application number: CN201811285163.3A
Authority: CN
Inventors: 维克多.吉辛; 周智
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-10-31
Filing date: 2018-10-31
Publication date: 2023-12-08
Anticipated expiration: 2038-10-31
Also published as: CN109614264A; WO2020087931A1

Abstract

The application discloses a data backup method, device and system. The system includes a first storage device, a second storage device, and a host. The first storage device includes a first controller and a storage medium, and the second storage device includes a second controller and a storage medium. The host triggers a first write instruction to the first controller and triggers a second write instruction to the second controller, wherein the first write instruction carries an association identifier, and the association identifier is used for associating data to be stored with the second write instruction. The first controller acquires a first write instruction and data to be stored, stores the data to be stored in a storage medium of the first storage device according to the first write instruction, and sends a data message to the second controller, wherein the data message comprises the data to be stored and the association identifier. The second controller acquires a second write instruction and a data message, associates the second write instruction with data to be stored according to an association identifier carried in the data message, and stores the data to be stored in a storage medium of the second storage device according to the second write instruction.

Description

Data backup method, device and system

Technical Field

The present application relates to the field of storage, and in particular, to a method, an apparatus, and a system for data backup.

Background

With the development of storage technologies, particularly in Solid State Drives (SSDs) using Flash memory (Flash) as a storage medium, the requirements of the storage device have not been met by the serial advanced technology attachment (serial advanced technologyattachment, SATA) interface and serial ATA advanced host interface/advanced host controller interface (Serial ATA AdvancedHost Control ler Interface, AHCI) standard of the conventional mechanical hard disk design, which is a big bottleneck limiting the processing capacity of the storage device. Non-volatile high speed transport bus (non-volatile memory express, NVMe), an interface that allows a host (host) to communicate with a non-volatile memory (NVM) subsystem, which interface that the NVM subsystem (including controller and storage media) communicates with, is attached to a peripheral component interconnect express bus (Peripheral Component Interconnect express, PCIe) interface in the form of a register interface, providing the advantage of optimizing enterprise-level and consumer-level solid state storage for high performance and low access latency.

In the prior art, one way of data backup is to provide two storage devices, one of which is a backup of the other storage device. When the host computer performs writing operation, the two storage devices trigger NVMe writing instructions respectively, and after the two storage devices acquire the NVMe writing instructions, the two storage devices acquire data from the host computer respectively and write the data to be stored into respective storage media.

Disclosure of Invention

The application discloses a data backup method, a device and a system. In the process of data storage, after the first storage device acquires the data to be stored from the host side, the data message is actively pushed to the second storage device, and the second storage device does not need to acquire the data to be stored from the host.

In a first aspect, the present application discloses a data backup system comprising a first storage device, a second storage device, and a host. The second storage device is a backup of the first storage device, the first storage device comprises a first controller and a storage medium, and the second storage device comprises a second controller and the storage medium. The host is used for triggering a first write instruction to the first controller and triggering a second write instruction to the second controller, wherein the first write instruction carries an association identifier, and the association identifier is used for associating data to be stored with the second write instruction. The first controller is used for acquiring a first write instruction and data to be stored, storing the data to be stored into a storage medium of the first storage device according to the first write instruction, and sending a data message to the second controller, wherein the data message comprises the data to be stored and the association identifier. The second controller is used for acquiring a second write instruction and a data message, associating the second write instruction with data to be stored according to an association identifier carried in the data message, and storing the data to be stored into a storage medium of the second storage device according to the second write instruction.

Wherein the backup system may be a nonvolatile high speed transport bus (non-volatile memory express, NVMe) based backup system and the first write instruction and/or the second write instruction may be an NVMe based commit queue entry (submission queue entry, SQE). Triggering the first write instruction by the host may be writing the first write instruction to a commit queue (SQ) associated with the first controller and notifying the first controller via a doorbell mechanism. Similarly, triggering the second write command by the host may write the second write command to the SQ associated with the second controller for the host and notify the second controller via the doorbell mechanism. The host may also send the first write command directly to the first controller and send the second write command to the second controller. The first controller actively transmits the storage data to the second controller after acquiring the data to be stored, and carries an association identifier for associating the data to be stored with a second writing instruction in a data message, and the second writing instruction associates the second writing instruction with the data to be stored according to the association identifier after receiving the data message, and writes the data to be stored into a storage medium of the second storage device according to the second writing instruction, so that backup operation of the data to be stored is completed. The second controller does not need to acquire the data to be stored from the host, and compared with the prior art that the first controller and the second controller respectively acquire the data to be stored from the host, the data flow of the uplink port of the switching network, which is formed by interconnecting the host and the first storage device and the second storage device, is halved.

In a first possible implementation manner of the first aspect, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the second controller. The first controller can write the data to be stored into the second controller in the form of PCIe messages, and the PCIe address indicated by the associated identification is an entry for writing the data to be stored. The second controller may determine a second write instruction associated with the data to be stored according to the address of the PCIe packet.

In a second possible implementation manner of the first aspect according to the first aspect or the first possible implementation manner of the first aspect, the second controller includes an internal memory, and before the second controller stores the data to be stored in the storage medium of the second storage device, the second controller is further configured to store the data to be stored in a storage space of the internal memory, and record a mapping relationship between the storage space and the association identifier. The invention does not limit the sequence of the second controller for acquiring the second writing instruction and the data to be stored, and the second controller can firstly receive the data message, then cache the data to be stored in the internal memory of the second controller, and record the mapping relation between the storage space for storing the data to be stored and the associated identifier.

In a third possible implementation manner of the first aspect according to the first aspect or any of the foregoing possible implementation manners of the first aspect, the second controller is further configured to determine a storage location of the second write instruction according to the association identifier, and the second controller is configured to obtain the second write instruction according to the storage location of the second write instruction. The host and the second controller maintain a corresponding relation between the associated identifier and the slot of the sending queue, when the host triggers the first write instruction and the second write instruction, the second write instruction is stored in the SQ slot corresponding to the associated identifier, after the second controller acquires the associated identifier, the SQ slot stored by the second write instruction can be determined according to the associated identifier, and the second write instruction is acquired from the SQ slot.

In a fourth possible implementation manner of the first aspect according to the first aspect or any one of the preceding possible implementation manners of the first aspect, the association identifier includes a part field of the second write instruction, and the second controller is configured to obtain the second write instruction according to the part field of the second write instruction. The association identifier may be indication information of the second write instruction, and after the second controller obtains the association identifier, the second controller may query the second write instruction according to the association identifier.

In a fifth possible implementation manner of the first aspect according to the first aspect or any one of the foregoing possible implementation manners of the first aspect, the second controller is further configured to trigger a completion message, where the completion message is used to instruct the second controller to complete a storage operation of the data to be stored, and the host is further configured to obtain the completion message.

The completion message may be a trigger completion queue entry (completion queue entry, CQE) for instructing the second controller to complete the write operation indicated by the second write instruction. The second controller triggering completion message may specifically be that after the second controller completes the write operation, a CQE is written into a Completion Queue (CQ), and the host is notified by an interrupt.

In a second aspect, the present invention provides a data backup method, a data backup system including a first storage device, a second storage device and a host, the second storage device being a backup of the first storage device, the first storage device including a first controller and a storage medium, the second storage device including a second controller and a storage medium, the method comprising: the host triggers a first write instruction, wherein the first write instruction carries an association identifier, and the association identifier is used for associating a second write instruction with data to be stored; the first write instruction is used for instructing the first controller to store data to be stored in a storage medium of the first storage device and instructing the first controller to send a data message to the second controller, wherein the data message comprises the data to be stored and an associated identifier; the host triggers a second write instruction, where the second write instruction is used to instruct the second controller to store the data to be stored in the storage medium of the second storage device.

In a first possible implementation manner of the second aspect according to the second aspect, the method further includes: the host acquires a completion message triggered by the second controller, wherein the completion message is used for indicating the second controller to complete the storage operation of the data to be stored.

In a second possible implementation manner of the second aspect or the first possible implementation manner of the second aspect, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the second controller.

In a third possible implementation manner of the second aspect according to the second aspect or the first possible implementation manner of the second aspect, the association identifier includes a part field of the second write instruction.

In a fourth possible implementation manner of the second aspect according to the second aspect or any one of the possible implementation manners of the second aspect, the first write instruction and/or the second write instruction is an NVMe-based SQE

The second aspect is a method implementation manner of the host side corresponding to the system of the first aspect, and descriptions in the first aspect or any possible implementation manner of the first aspect are correspondingly applicable to the second aspect or any possible implementation manner of the second aspect, which are not described herein.

In a third aspect, the application provides a readable medium comprising execution instructions which, when executed by a processor of a computing device, perform the method of the second aspect above or any one of the possible implementations of the second aspect above.

In a fourth aspect, the present application provides a computing device comprising: a processor, a memory, and a bus; the memory is for storing execution instructions, and the processor is connected to the memory by a bus, the processor executing the execution instructions stored by the memory when the computing device is running to cause the computing device to perform the method of the second aspect above or any one of the possible implementations of the second aspect above.

In a fifth aspect, the present application discloses a data backup method, a data backup system includes a first storage device, a second storage device and a host, the second storage device is a backup of the first storage device, the first storage device includes a first controller and a storage medium, and the second storage device includes a second controller and a storage medium, the method includes: the method comprises the steps that a first controller obtains a first write instruction triggered by a host and data to be stored, the first write instruction carries an association identifier, the association identifier is used for associating the data to be stored with a second write instruction, and the second write instruction is triggered by the host and used for instructing a second controller to write the data to be stored into a storage medium of a second storage device; the first controller stores the data to be stored in a storage medium of the first storage device according to the first write instruction; the first controller sends a data message to the second controller, wherein the data message comprises data to be stored and an associated identifier.

In a first possible implementation manner of the fifth aspect, according to the fifth aspect, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the second controller.

In a second possible implementation manner of the fifth aspect according to the fifth aspect, the association identifies a part field containing the second write instruction.

In a third possible implementation manner of the fifth aspect according to the fifth aspect or any one of the possible implementation manners of the fifth aspect, the first write instruction and/or the second write instruction is an SQE based on NVMe.

The fifth aspect is a method implementation manner of the first controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect is applicable to the fifth aspect or any possible implementation manner of the fifth aspect, which is not repeated herein.

In a sixth aspect, the application provides a readable medium comprising execution instructions which, when executed by a processor of a computing device, perform the method of the fifth aspect above or any one of the possible implementations of the fifth aspect above.

In a seventh aspect, the present application provides a computing device comprising: a processor, a memory, and a bus; the memory is for storing execution instructions, and the processor is connected to the memory by a bus, the processor executing the execution instructions stored by the memory when the computing device is running to cause the computing device to perform the method of the fifth aspect above or any one of the possible implementations of the fifth aspect above.

In an eighth aspect, the present application discloses a data backup method, a data backup system includes a first storage device, a second storage device and a host, the second storage device is a backup of the first storage device, the first storage device includes a first controller and a storage medium, and the second storage device includes a second controller and a storage medium, the method includes: the second controller acquires a write instruction triggered by the host, wherein the write instruction is used for instructing the second controller to write data to be stored into a storage medium of the second storage device; the second controller receives a data message sent by the first controller, wherein the data message comprises data to be stored and an associated identifier, and the associated identifier is used for associating a write instruction with the data to be stored; the second controller stores the data to be stored in the storage medium of the second storage device according to the write instruction.

In a first possible implementation manner of the eighth aspect, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the second controller.

In a second possible implementation manner of the eighth aspect according to the eighth aspect or the first possible implementation manner of the eighth aspect, the second controller includes an internal memory, and before the second controller stores the data to be stored in the storage medium of the second storage device, the method further includes: and the second controller stores the data to be stored into a storage space of the internal memory, and records the mapping relation between the storage space and the associated identifier.

In a third possible implementation manner of the eighth aspect, according to the eighth aspect or any of the above possible implementation manners of the eighth aspect, the method further includes: the second controller determines the storage position of the write instruction according to the association identifier; the second controller obtaining the write instruction includes: the second controller acquires the write instruction according to the storage position of the write instruction.

In a fourth possible implementation form of the eighth aspect according to any of the preceding possible implementation forms of the eighth aspect, the association identifies a partial field containing a write instruction; the second controller obtaining the write instruction includes: the second controller obtains the write instruction according to a part of the fields of the write instruction.

In a fifth possible implementation manner of the eighth aspect according to the eighth aspect or any one of the possible implementation manners of the eighth aspect, the method further includes: the second controller triggers a completion message, which is used to instruct the second controller to complete the storage operation of the data to be stored.

In a sixth possible implementation manner of the eighth aspect according to the eighth aspect or any one of the possible implementation manners of the eighth aspect, the write instruction is an SQE based on NVMe.

The eighth aspect is a method implementation manner of the second controller side corresponding to the system of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect is correspondingly applicable to the eighth aspect or any possible implementation manner of the eighth aspect, which is not described herein.

In a ninth aspect, the application provides a readable medium comprising execution instructions which, when executed by a processor of a computing device, perform the method of the eighth aspect above or any one of the possible implementations of the eighth aspect above.

In a tenth aspect, the present application provides a computing device comprising: a processor, a memory, and a bus; the memory is for storing execution instructions, and the processor is connected to the memory by a bus, the processor executing the execution instructions stored by the memory when the computing device is running to cause the computing device to perform the method of the eighth aspect above or any one of the possible implementations of the eighth aspect above.

In an eleventh aspect, the present application discloses a data backup device, the data backup system includes a first storage device, a second storage device and a data backup device, the second storage device is a backup of the first storage device, the first storage device includes a first controller and a storage medium, the second storage device includes a second controller and a storage medium, the data backup device includes: the processing unit is used for triggering a first write instruction, wherein the first write instruction carries an association identifier, and the association identifier is used for associating a second write instruction with data to be stored; the first write instruction is used for instructing the first controller to store data to be stored in a storage medium of the first storage device and instructing the first controller to send a data message to the second controller, wherein the data message comprises the data to be stored and an associated identifier; the processing unit is further configured to trigger a second write instruction, where the second write instruction is configured to instruct the second controller to store the data to be stored in the storage medium of the second storage device.

According to an eleventh aspect, in a first possible implementation manner of the eleventh aspect, the backup device further includes an obtaining unit, configured to obtain a completion message triggered by the second controller, where the completion message is used to instruct the second controller to complete a storage operation of the data to be stored.

In a second possible implementation manner of the eleventh aspect according to the first possible implementation manner of the eleventh aspect, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the second controller.

In a third possible implementation manner of the eleventh aspect according to the first possible implementation manner of the eleventh aspect, the association identifier includes a part field of the second write instruction.

In a fourth possible implementation manner of the eleventh aspect according to the eleventh aspect or any one of the preceding possible implementation manners of the eleventh aspect, the first write instruction and/or the second write instruction is an SQE based on NVMe.

The eleventh aspect is a device implementation manner on the host side corresponding to the system in the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect is correspondingly applicable to the eleventh aspect or any possible implementation manner of the eleventh aspect, which is not described herein.

In a twelfth aspect, the present application discloses a data backup device, a data backup system including a first storage device, a second storage device and a host, the second storage device being a backup of the first storage device, the first storage device including a data backup device and a storage medium, the second storage device including a controller and a storage medium, the data backup device comprising: the processing unit is used for acquiring a first write instruction triggered by the host and data to be stored, the first write instruction carries an association identifier, the association identifier is used for associating the data to be stored with a second write instruction, the second write instruction is triggered by the host and used for indicating the controller to write the data to be stored into a storage medium of the second storage device, and the data to be stored is stored into the storage medium of the first storage device according to the first write instruction; and the sending unit is used for sending a data message to the controller, wherein the data message comprises data to be stored and an associated identifier.

In a first possible implementation manner of the twelfth aspect according to the twelfth aspect, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the controller.

In a second possible implementation manner of the twelfth aspect according to the twelfth aspect, the association identifies a part field containing the second write instruction.

In a twelfth possible implementation manner according to the twelfth aspect or any one of the possible implementation manners above, in a third possible implementation manner of the twelfth aspect, the first write instruction and/or the second write instruction is an SQE based on NVMe.

The twelfth aspect is a device implementation manner on the first controller side corresponding to the system in the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect is correspondingly applicable to the twelfth aspect or any possible implementation manner of the twelfth aspect, which is not repeated herein.

In a thirteenth aspect, the present application discloses a data backup device, the data backup system including a first storage device, a second storage device and a host, the second storage device being a backup of the first storage device, the first storage device including a controller and a storage medium, the second storage device including a data backup device and a storage medium, the data backup device including: the data backup device comprises an acquisition unit, a storage unit and a storage unit, wherein the acquisition unit is used for acquiring a write instruction triggered by a host, the write instruction is used for instructing a data backup device to write data to be stored into a storage medium of a second storage device, and receiving a data message sent by a controller, the data message comprises the data to be stored and an association identifier, and the association identifier is used for associating the write instruction and the data to be stored; and the processing unit is used for storing the data to be stored into the storage medium of the second storage device according to the write instruction.

In a first possible implementation manner of the thirteenth aspect, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the data backup device.

In a second possible implementation manner of the thirteenth aspect according to the first possible implementation manner of the thirteenth aspect, the data backup device further includes an internal memory, and the processing unit is further configured to store the data to be stored in a storage space of the internal memory before storing the data to be stored in the storage medium of the second storage device, and record a mapping relationship between the storage space and the associated identifier.

In a thirteenth possible implementation manner according to the thirteenth aspect or any of the foregoing possible implementation manners of the thirteenth aspect, the obtaining unit is further configured to determine a storage location of the write instruction according to the association identifier, and obtain the write instruction according to the storage location of the write instruction.

In a fourth possible implementation form of the thirteenth aspect as such or any of the preceding possible implementation forms of the thirteenth aspect, the association identifies a part of the field containing the write instruction; the acquisition unit is further configured to acquire the write instruction according to a part of the field of the write instruction.

In a thirteenth possible implementation manner according to the thirteenth aspect or any one of the foregoing possible implementation manners of the thirteenth aspect, the processing unit is further configured to trigger a completion message, where the completion message is used to instruct the data backup device to complete a storage operation of the data to be stored.

In a thirteenth possible implementation manner according to the thirteenth aspect or any one of the above possible implementation manners of the thirteenth aspect, the write instruction is an NVMe-based SQE.

The thirteenth aspect is an implementation manner of the device on the second controller side corresponding to the system in the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect is applicable to the thirteenth aspect or any possible implementation manner of the thirteenth aspect, which is not repeated herein.

According to the technical scheme disclosed by the embodiment of the invention, the host triggers a first write instruction to the first controller and triggers a second write instruction to the second controller. The first write instruction triggered by the host to the first controller carries an association identifier associated with the second write instruction and data to be stored. After the first controller acquires the data to be stored, the first controller actively transmits a data message to the second controller, wherein the data message carries the data to be stored and the association identifier. After the second controller obtains the data message, the second write instruction and the data to be stored are associated according to the association identifier, and the data to be stored is written into the storage medium of the second storage device according to the second write instruction, so that the process that the second controller obtains the data to be stored from the host is avoided. The data flow of the uplink port of the switching network where the host computer is interconnected with the first storage device and the second storage device is the same as that when the data backup is not performed, so that the overall performance of the system is improved.

Drawings

FIG. 1 is a schematic diagram of a logic structure of an NVMe system according to an embodiment of the present application;

FIG. 2 is a schematic flow chart of an NVMe-based data backup method;

FIG. 3 is a flowchart of a data backup method according to an embodiment of the application;

FIG. 4 is a schematic diagram of a hardware structure of a host according to an embodiment of the application;

FIG. 5 is a schematic diagram of a hardware configuration of a controller according to an embodiment of the application;

FIG. 6 is a schematic diagram of a hardware configuration of a controller according to an embodiment of the application;

FIG. 7 is a flowchart of a data backup method according to an embodiment of the application;

FIG. 8 is a schematic diagram of an entry organization according to an embodiment of the application;

FIG. 9 is a schematic diagram of a PCIe address structure according to one embodiment of the application;

FIG. 10 is a diagram illustrating a data storage structure according to an embodiment of the present application;

FIG. 11 is a schematic diagram illustrating a logic structure of a data backup device according to an embodiment of the application;

FIG. 12 is a schematic diagram illustrating a logic structure of a data backup device according to an embodiment of the application;

FIG. 13 is a schematic diagram illustrating a logic structure of a data backup device according to an embodiment of the application.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings.

The embodiments of the present invention employ the terms first and second, etc. to distinguish between respective objects, e.g., first write instructions and second write instructions, etc., but each "first" and "second" has no logical or chronological dependency between them.

In the embodiment of the invention, the data message refers to a message which is sent by the first storage device to the second storage device and carries the load data and the associated identifier. The payload data is data to be stored or part of the data to be stored. In the embodiment of the present invention, according to the size of the data to be stored, the first storage device may use one data packet to send the data to be stored to the second storage device, or split the data to be stored into a plurality of data packets to send the data packets to the second storage device. In the following description, the embodiments of the present invention refer to load data in a data packet collectively as data to be stored.

In the embodiment of the present invention, the term push refers to that the first storage device actively sends a data packet to the second storage device.

In the embodiment of the present invention, the entry is an address space that is opened by the second storage device to the first storage device, the entry address may be specifically a PCIe address, and the data packet may be a PCIe write packet. More specifically, the portal may be an address space that is opened by the controller of the second storage device to the controller of the first storage device, and the controller of the first storage device may push the data to be stored to the controller of the second storage device according to the address space.

In the embodiment of the invention, the association identifier carried in the data message is used for associating the data to be stored with the write instruction. The association identifier may contain the entry address or a partial field of the entry address.

In the embodiment of the present invention, the first storage device may push the data packet to the second storage device through the entry, where the data packet may carry the entry address. After the second storage device receives the data message, the entry address is identified, a corresponding storage space can be allocated for the entry in the local internal memory, and the load data carried by the data message is cached in the storage space instead of storing the load data in the storage space indicated by the entry address. The internal memory may be embodied as a private memory space of the controller.

In the embodiment of the invention, the storage device comprises a controller and a storage medium, and the storage controller is hereinafter referred to as a controller. The execution subject of the storage device is typically a controller. For example, a first storage device includes a first controller and a storage medium, and a second storage device includes a second controller and a storage medium. The main body of the interaction between the first storage device and the outside is a first controller, and the main body of the interaction between the second storage device and the outside is a second controller. In the following description, embodiments of the present invention do not distinguish between a storage device and a controller when external interaction occurs.

In the embodiment of the present invention, a specific implementation manner of the host triggered instruction may be SQE.

In an embodiment of the present invention, the host is interconnected with the first storage device and the second storage device through a switching network. The upstream port of the switching network refers to a port where the switching network is interconnected with the host. Upstream traffic of the switching network refers to data traffic interacting with the host.

In the embodiment of the present invention, the term host refers to a main body that can interact with a storage device and store data to the storage device. The host may be a physical computer, virtual machine, network card, or the like. The embodiment of the invention is not limited to the specific implementation form of the host.

Fig. 1 is a block diagram of a data backup system 100 according to an embodiment of the invention, and as shown in fig. 1, the system 100 includes a host 101, a switching network 102, a first storage device 103 and a second storage device 105. Wherein the first storage means 103 comprises a first controller 104 and a storage medium, and the second storage means 105 comprises a second controller 106 and a storage medium. The second storage device 105 is a backup of the first storage device 103 (that is, some or all of the data of the first storage device 103 is backed up to the second storage device 105).

In an embodiment of the present invention, the storage medium is typically a nonvolatile storage medium for permanently storing data. The storage medium may be magnetic (e.g., floppy disk, hard disk, magnetic tape), optical (e.g., optical disk), or semiconductor (e.g., flash memory (Flash), etc.), and embodiments of the invention are not limited to a specific implementation of the storage medium.

In an embodiment of the present invention, the switching network 102 may be used to refer to: any manner of interconnection or interconnection protocol of the host 101, the first storage device 103, and the second storage device 105, and the like. For example, the switching network 102 may be a PCIe bus, where the PCIe bus may contain PCIe switches that interconnect with the hosts 101. The switching network 102 may also be a computer device intranet, the Internet, an intranet, a local area network (local area network, LAN), a wide area network (wide area network, WAN), a storage area network (storage area network, SAN), or the like, or any combination thereof. Embodiments of the present invention are not limited to a particular implementation of switching network 102.

As shown in fig. 2, in the conventional backup method, when the host 101 performs data storage, the same write command needs to be triggered to the first storage device 103 and the second storage device 105, respectively. Specifically, the write command is an SQE, and the host 101 writes the SQE to a send queue associated with the first storage device 103 and notifies the first controller 104 of a new SQE through a doorbell mechanism. After receiving the doorbell notification, the first controller 104 sends a queue to obtain a corresponding SQE, where the PRP or SGL field of the SQE carries address information of the data to be stored. The first controller 104 reads data to be stored from the host 101 side according to address information carried in the SQE, and then stores the data to be stored in the storage medium of the first storage device 103. Similarly, the host 101 writes the same read instruction to the send queue associated with the second storage device 105 and notifies the second controller 106 of a new SQE via the command mechanism. After the second controller 106 obtains the SQE, it still needs to read the data to be stored from the host 101 side according to the address information carried by the SQE, then write the data to be stored into the storage medium of the second storage device 105, and trigger a completion message to the host 101. Based on the above procedure, the same data needs to be read twice from the host side, and the upstream data traffic of the switching network 102 is twice that when there is no backup. The upstream data traffic refers to data traffic that interacts with the host 101.

In the embodiment of the present invention, as shown in fig. 3, when the host 101 needs to store data, a first write instruction and a second write instruction are triggered to the first storage device 103 and the second storage device 105 respectively, where the first write instruction carries an association identifier, and the association identifier is used to associate the data to be stored with the second write instruction. After the first controller 104 obtains the first write instruction and the data to be stored, the data to be stored is written into the storage medium of the first storage device 103, and the data message is actively pushed to the second controller 106, where the data message carries the data to be stored and the association identifier. After the second controller 106 obtains the second write command and the data packet, the second write command and the data to be stored are associated according to the association identifier, the data to be stored is written into the storage medium of the second storage device 105 according to the second write command, and the completion message is triggered to the host 101. According to the embodiment of the invention, the first storage device 103 actively pushes the data message containing the data to be stored and the associated identifier to the second storage device 105, so that the step that the second storage device 105 reads the message from the host 101 side is avoided, the flow of the uplink port of the switching network 102, which is formed by interconnecting the first storage device 103 and the host 101, of the second storage device 105 is reduced, and the overall performance of the system is improved.

Fig. 4 is a schematic diagram of a host 400 according to an embodiment of the application.

As shown in fig. 4, the host 400 includes a processor 401, and the processor 401 is connected to a system memory 402. The processor 301 may be a Central Processing Unit (CPU), an image processor (graphics processing unit, GPU), a field programmable gate array (Field Programmable Gate Array, FPGA), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or a digital signal processor (digital signal processor, DSP), or any combination thereof. Processor 301 may be a single-core processor or a multi-core processor.

In one embodiment of the application, processor 401 may further include backup logic 410, and backup logic 410 may be a specific hardware circuit or a firmware module integrated in processor 401. If the backup logic 410 is a specific hardware circuit, the backup logic 410 executes the method according to the embodiment of the present application, and if the backup logic 410 is a firmware module, the processor 410 executes the firmware code in the backup logic 410 to implement the technical solution according to the embodiment of the present application. Backup logic 410 includes: (1) Logic (circuit/firmware code) for triggering a first write instruction, the first write instruction carrying an association identifier for associating a second write instruction with data to be stored, the first write instruction being for instructing a first storage device to store the data to be stored in a storage medium of the first storage device and for instructing the first storage device to send a data message to the second storage device, the data message comprising the data to be stored and the association identifier; (2) Logic (circuit/firmware code) for triggering a second write instruction for instructing the second storage medium to store data to be stored in the storage medium of the second storage device.

Bus 409 is used to transfer information between components of host 400, and bus 409 may be wired or wireless, as the present application is not limited thereto. The bus 409 is also connected with an input/output interface 405 and a communication interface 403.

An input/output device is connected to the input/output interface 405, and is used for receiving input information and outputting an operation result. The input/output device may be a mouse, keyboard, display, or optical drive, etc.

The communication interface 403 is used to enable communication with other devices or networks, and the communication interface 403 may be interconnected with other devices or networks by wired or wireless means. For example, the host 400 may be interconnected with a switching network through the communication interface 403 and connected to a controller through the switching network.

Some features of embodiments of the present application may be implemented/supported by processor 401 executing software code in system memory 402. The system memory 402 may include some software, such as an operating system 408 (e.g., darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, or embedded operating systems (e.g., vxworks)), application programs 407, and backup module 406, among others.

In one embodiment of the present application, the processor 401 executes the backup module 406 to implement the technical solution of the embodiment of the present application. The backup module 406 includes: (1) The first writing instruction carries an association identifier, the association identifier is used for associating the second writing instruction with the data to be stored, the first writing instruction is used for instructing the first storage device to store the data to be stored in a storage medium of the first storage device and instructing the first storage device to send a data message to the second storage device, and the data message contains the data to be stored and the association identifier; (2) Code for triggering a second write instruction for instructing the second storage medium to store the data to be stored in the storage medium of the second storage device.

Moreover, FIG. 4 is merely an example of a host 400, and the host 400 may contain more or fewer components than shown in FIG. 4, or may have a different configuration of components. Meanwhile, various components shown in fig. 4 may be implemented in hardware, software, or a combination of hardware and software.

Fig. 5 is a schematic diagram of a controller 500 according to an embodiment of the application.

As shown in fig. 5, the controller 500 includes a processor 501, and the processor 501 is connected to a system memory 502. The processor 401 may include computational logic such as CPU, GPU, FPGA, ASIC or DSP, or any combination of the above. Processor 401 may be a single-core processor or a multi-core processor.

In one embodiment of the application, the processor 501 may also include backup logic 505, and the backup logic 505 may be specific hardware circuitry or firmware modules integrated into the processor 501. If the backup logic 505 is a specific hardware circuit, the backup logic 505 executes the method according to the embodiment of the present application, and if the backup logic 505 is a firmware module, the processor 501 executes the firmware code in the backup logic 505 to implement the technical solution according to the embodiment of the present application. Backup logic 505 includes: (1) Logic (circuit/firmware code) for acquiring a first write instruction triggered by the host and data to be stored, the first write instruction carrying an association identifier, the association identifier being used for associating the data to be stored with a second write instruction; (2) Logic (circuitry/firmware code) for storing data to be stored in a storage medium of the first storage device according to the first write instruction; (3) Logic (circuit/firmware code) for sending a data message to the second storage device, the data message containing the data to be stored and the associated identification.

The bus 507 is used to transfer information between the components of the controller 500, and the bus 507 may be wired or wireless, which is not limited by the present application. A communication interface 503 may also be connected to the bus 507.

The communication interface 503 is used to enable communication with other devices or networks, and the communication interface 503 may be interconnected to other devices or networks by wired or wireless means. For example, the controller 500 is interconnected with a switching network and a storage medium through a communication interface 503.

Some features of embodiments of the present application may be implemented/supported by processor 501 executing software code in system memory 502. The system memory 502 may include some software, such as an operating system 504 (e.g., darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or an embedded operating system (e.g., vxworks)), and a backup module 506, among others.

In one embodiment of the present application, the processor 501 executes the backup module 506 to implement the technical solution of the embodiment of the present application. The backup module 506 includes: (1) The method comprises the steps of acquiring a first write instruction triggered by a host and a code of data to be stored, wherein the first write instruction carries an association identifier, and the association identifier is used for associating the data to be stored with a second write instruction; (2) Code for storing data to be stored in a storage medium of a first storage device according to a first write instruction; (3) And the code is used for sending a data message to the second storage device, wherein the data message comprises data to be stored and an associated identifier.

In addition, FIG. 5 is merely an example of a controller 500, and the controller 500 may include more or fewer components than shown in FIG. 5, or may have a different configuration of components. Meanwhile, various components shown in fig. 5 may be implemented in hardware, software, or a combination of hardware and software.

Fig. 6 is a schematic structural diagram of a controller 600 according to an embodiment of the application.

As shown in fig. 6, the controller 600 includes a processor 601, and the processor 601 is connected to a system memory 602. The processor 401 may include computational logic such as CPU, GPU, FPGA, ASIC or DSP, or any combination of the above. Processor 401 may be a single-core processor or a multi-core processor.

In embodiments of the present application, the processor 601 may also contain a register within it that is accessible to the controller of other memory devices. More specifically, the register may be opened as a PCIe address space to the controller of the other storage device for the controller of the other storage device to access through the PCIe address.

In one embodiment of the application, processor 601 may also include backup logic 605, and backup logic 605 may be specific hardware circuitry or firmware modules integrated within processor 601. If the backup logic 605 is a specific hardware circuit, the backup logic 605 executes the method according to the embodiment of the present application, and if the backup logic 605 is a firmware module, the processor 601 executes the firmware code in the backup logic 605 to implement the technical solution according to the embodiment of the present application. Backup logic 605 includes: (1) Logic (circuitry/firmware code) to obtain a host-triggered write instruction; (2) Logic (circuit/firmware code) for receiving a data message sent by the first storage device, where the data message includes data to be stored and an association identifier, and the association identifier is used to associate the write instruction with the data to be stored; (3) Logic (circuitry/firmware code) for storing data to be stored in a storage medium of the second storage device in accordance with the write instruction.

Bus 607 is used to transfer information between the components of controller 600. Bus 607 may be wired or wireless, as the application is not limited. The bus 607 may also be connected to a communication interface 603.

The communication interface 603 is used to enable communication with other devices or networks, and the communication interface 603 may be interconnected to other devices or networks by wired or wireless means. For example, the controller 600 is interconnected with a host and a storage medium through the communication interface 603, and the controller 600 may also be connected to a network through the communication interface 603 and interconnected with the host or the storage medium through the network.

Some features of embodiments of the present application may be implemented/supported by processor 601 executing software code in system memory 602. The system memory 602 may include some software, such as an operating system 604 (e.g., darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, macOS, or embedded operating system (e.g., vxworks)), and a backup module 606, among others.

In one embodiment of the present application, the processor 601 executes the backup module 606 to implement the technical solution of the embodiment of the present application. The backup module 606 includes: (1) code for obtaining a host-triggered write instruction; (2) The code is used for receiving a data message sent by the first storage device, wherein the data message comprises data to be stored and an associated identifier, and the associated identifier is used for associating a write instruction with the data to be stored; (3) And code for storing the data to be stored in the storage medium of the second storage device according to the write instruction.

In addition, FIG. 6 is merely an example of a controller 600, and the controller 600 may include more or fewer components than shown in FIG. 6, or may have a different configuration of components. Meanwhile, various components shown in fig. 6 may be implemented in hardware, software, or a combination of hardware and software.

In order to reduce the occupation of bandwidth of an uplink port of a switching network in a data backup process, the embodiment of the invention provides a data backup method. The data backup system comprises a first storage device, a second storage device and a host, wherein the first storage device is a backup of the second storage device, the first storage device comprises a first controller and a storage medium, and the second storage device comprises a second controller and a storage medium. As shown in fig. 7, method 700 includes:

step 701: the host triggers a first write instruction.

The first write instruction carries an association identifier, and the association identifier is used for associating the second write instruction with data to be stored.

In an embodiment of the present invention, the first write instruction may be specifically SQE based on NVMe. In the following description, the first write instruction is exemplified as the SQE. It should be understood that embodiments of the present invention are not limited to a particular implementation of the first write instruction.

In the embodiment of the present invention, the flow of the first write instruction to the trigger by the host may refer to NMVe standard. The host writes the SQE to a transmit queue associated with the first controller and notifies the first controller, via the doorbell, that a new SQE is in the transmit queue associated with the first controller to alert the first controller to read the SQE.

In the embodiment of the present invention, the host triggering the first write instruction may also be in other implementation forms. For example, the host may send the first write instruction directly to the first controller. The invention is not limited to the specific implementation form of triggering the first write instruction by the host.

Step 702: the host triggers a second write instruction.

Similarly, the second write instruction may be an NVMe-based SQE. In the following description, the second write instruction is exemplified as the SQE. It should be understood that embodiments of the present invention are not limited to a particular implementation of the second write instruction.

In an embodiment of the present invention, the second write instruction may be specifically a write instruction, and is used to instruct the second controller to store the data to be stored in the storage medium of the second storage device.

In the embodiment of the invention, triggering the second write command by the host can write the second write command into the sending queue associated with the second controller for the host, and notify the second controller that a new SQE enters the sending queue associated with the second controller through the doorbell, so as to remind the second controller to read the SQE. Other implementations are possible in which the host triggers the second write instruction. For example, the host may send the second write instruction directly to the second controller. The invention is not limited to the specific implementation form in which the host triggers the second write instruction.

Step 703: the first controller obtains a first write instruction.

In an embodiment of the present invention, the first controller may obtain the first write instruction from a transmit queue associated with the host. Specifically, the first controller receives a doorbell notification of the host, where the doorbell is used to indicate that a new SQE arrives in the send queue, and the first controller obtains the SQE in the send queue. The first controller may also directly receive the first write command sent by the host. The embodiment of the invention is not limited to a specific implementation form that the first controller acquires the first write instruction.

Step 704: the first controller acquires data to be stored.

In the embodiment of the present invention, the format of the first write instruction may refer to the NVMe standard, and the host may indicate, in the first write instruction, address information of data to be stored through a PRP or SGL field of the SQE. The first controller reads data to be stored from the host side according to the address information.

In the embodiment of the invention, the host can also directly send the data to be stored to the first controller, and the first controller directly receives the data to be stored from the host. The embodiment of the invention is not limited to a specific implementation form of the first controller for acquiring the data to be stored.

Step 705: the first controller stores the data to be stored in a storage medium of the first storage device according to the first write instruction.

Step 706: the first controller sends a data message to the second controller.

The data message comprises data to be stored and the association identifier. In a specific implementation process, because the size of the load data carried by the data packet is limited, the first controller may divide the data to be stored into a plurality of data packets and send the data packets to the second controller.

In the embodiment of the invention, the first controller can actively push the data message to the second controller. The association identifier carried by the data message is used for associating the data to be stored with the second write instruction. The embodiment of the invention is not limited to a specific implementation manner of the association identifier, and the association identifier can directly or indirectly indicate the second write instruction corresponding to the data to be stored carried in the data message.

In the embodiment of the present invention, the data packet may be a PCIe write operation packet, more specifically, the data packet may be a transaction layer packet, the payload data may be a payload (payload) carried in a transport layer packet (transaction layer packet, TLP), and the association identifier may be a PCIe address of the TLP or a partial field of the PCIe address.

In the embodiment of the invention, the second controller opens a part of the address space to the first controller. More specifically, the address space that the second controller opens to the first controller may be the PCIe address space of the second controller. The first controller may access the PCIe address access. For example, the second controller may open a portion of the PCIe address of the base address register to the first controller for access.

In the following description, a base address register is illustrated, but it should be understood that embodiments of the present invention do not limit the type and form of address space that the second controller opens to the first controller for access.

In an embodiment of the present invention, the second controller may organize PCIe addresses of a portion of the base address register into entries (portals), each occupying a portion of the PCIe address space of the base address register. The first controller may write the data message to the second controller through the portal. The portal, i.e., the data portal where the first controller performs PCIe write operations to the second controller, will be described in more detail below.

In the embodiment of the present invention, the data packet pushed by the first controller to the second controller may be a PCIe packet, where the first controller writes the data to be stored associated with the second write instruction to the second controller through the entry, and an address field of the PCIe packet indicates an entry corresponding to the write operation, that is, the entry address is a PCIe address or a partial field of the PCIe address in the data packet.

In the embodiment of the invention, the association identifier may be an entry address or a partial field of the entry address. And the second controller is also used for determining the storage address of the second write instruction according to the association identifier after receiving the data message and acquiring the second write instruction according to the storage address of the second write instruction. The address storing the second write instruction may be a slot address storing the second write instruction in the commit queue.

In the embodiment of the invention, the host and the second controller maintain the corresponding relation between the entrance and the slot in the sending queue. When triggering the first writing instruction and the second writing instruction, the host stores the second writing instruction into the slot of the sending queue corresponding to the entry indicated by the association identifier, and carries the association identifier in the first writing instruction. And the first controller sends a data message to the second controller according to the association identifier, wherein the association identifier is carried in the data message. After the second controller obtains the data message, determining a slot for storing a second address in a transmission queue associated with the host according to the association identifier, and obtaining a second write instruction associated with the data to be stored from the slot.

The invention does not limit the organization of entries in the PCIe address space, but only needs to ensure that each entry uniquely corresponds to a specific second write instruction during a data backup operation, and each entry uniquely correlates to a specific second write instruction. For example, a portion of the PCIe address of the base address register of the second controller may be organized in the form of through-holes (aperture), each of which contains a plurality of entries, i.e., the entries may be organized in the form of arrays, the entries being addressed by an array base address add port offset, this array being referred to as a through-hole. Each entry is associated with a slot of the transmit queue. Fig. 8 is a schematic diagram of the structure of the base address register, and as shown in fig. 8, each via is composed of a set of entries P0-P N.

FIG. 9 is a PCIe address structure in a PCIe data packet according to one embodiment of the invention. As shown in fig. 9, the PCIe address structure contains the base address of the BAR, the via offset, and the entry offset. Wherein the BAR and via offset are used to uniquely identify a via and the entry offset is used to indicate a specific entry in the via. In the embodiment of the invention, the data to be stored is "pushed" by the first controller to the second controller through the through hole of the PCIe BAR space. "push" refers to a PCIe write transaction initiated by a first controller.

In the embodiment of the invention, the entries can be arbitrarily distributed in the PCIe address space, and the arbitrarily distributed entries in the PCIe space are called arbitrary data entries.

In an embodiment of the invention, the association is identified as the entry address or a partial field of the entry address. The host and the second controller maintain the corresponding relation between the inlet and the slot positions in the SQ, and the SQ slot positions are in one-to-one correspondence with the inlet. The host triggers a first write instruction and a second write instruction through the corresponding relation between the entrance and the SQ slot. The second controller can acquire a corresponding second write instruction according to the corresponding relation between the SQ slot position and the entry and the associated identifier in the data message. According to the embodiment of the invention, the SQ slot for storing the second write instruction is used for associating the entry with the second write instruction, and the second write instruction corresponding to the entry is determined through the SQ slot.

In other implementations of the embodiment of the present invention, the association identifier may also be indication information of the second write instruction. For example, the association identifier may further include a portion of a field of the second write instruction, and the second controller obtains the second write instruction according to the association identifier. Specifically, the second write command may be an SQE, and the indication information identified as the SQE is associated to uniquely determine an SQE.

In the embodiment of the invention, the association between the SQE and the data to be stored is directly realized by carrying the indication information of the SQE in the data message, rather than the indirect association through the SQ slot. For example, if each SQE in one SQ has a respective unique command identification CID, the association identification may consist of a "queue ID+CID". If the CID of each SQE is unique, the associated identifier may be the CID carried by the corresponding SQE. In other implementations, the association identifier may also be part of the CID. In the embodiment of the present invention, the association identifier may also be specified by using a specifically defined SGL type or SGL subtype or other fields in the SQE, so long as the second controller may uniquely determine the second write instruction according to the association identifier.

Step 707: the second controller obtains a second write instruction.

In the embodiment of the present invention, the second controller may obtain the second write instruction from a transmit queue associated with the host. More specifically, the second controller receives a doorbell notification of the host, where the doorbell is used to indicate that a new SQE arrives at a send queue corresponding to the second controller, and after receiving the doorbell of the host, the controller sends the send queue to obtain the second write instruction. The second controller may also directly receive the second write command sent by the host. The embodiment of the invention is not limited to a specific implementation form of the second controller for acquiring the second write instruction.

In the embodiment of the invention, the format of the second write instruction can refer to the NVMe standard, but the embodiment of the invention associates the data to be stored and the second write instruction through the association identifier, and the data to be stored is actively pushed to the second controller by the first controller. The second write instruction does not need the second controller to actively acquire the data to be stored through PCIe read operation, so that the address information of the data to be stored is not needed to be carried in the second write instruction through the SGL domain or the PRP domain. In a specific implementation, the SGL domain or the PRP domain of the second write instruction may not carry other information, and the processing method of the second controller to the SGL domain or the PRP domain may be "ignore", that is, the SGL or the PRP may be omitted in the embodiment of the present invention.

In the embodiment of the invention, the association identifier may be an entry address or a partial field of the entry address. The second controller maintains a correspondence between entries and slots in the transmit queue. And the second controller is also used for determining the storage address of the second write instruction according to the association identifier after receiving the data message and acquiring the second write instruction according to the storage address of the second write instruction.

In the embodiment of the present invention, the association identifier may also be indication information of the second write instruction. For example, the association identifier may also contain a partial field of the second write instruction. The second controller may also look up a second write instruction indicated by the association identifier in the send queue according to the association identifier.

Step 708: the second controller acquires data to be stored.

In the embodiment of the invention, the data message carries the data to be stored. The address information carried in the data message indicates an entry of the second controller, where the entry of the second controller is used for receiving the data message, and is an entry where the first controller sends the data message to the second controller. After the second controller receives the data packet, the storage space for the data to be stored may be an internal memory of the second controller, instead of storing the data to be stored in the storage space indicated by the entry address.

After the second controller receives the data message, analyzing the data message to obtain the address of the data message, obtaining the association identifier, and recognizing that the association identifier is address information of an entrance of the second controller which wants the first controller to open, wherein the second address stores the data to be stored in the data message into the internal memory of the second controller. Specifically, the second controller may allocate a specific storage block in its own internal memory for each entry, for storing the data to be stored received by the entry. To facilitate data management and querying, the second controller may establish a mapping of memory blocks to entries. The internal memory used for storing data by the second controller can not be accessed to the outside through a PCIe addressing mode any more, and is not used as a command memory buffer zone, and the embodiment of the invention is not limited to a specific implementation mode of a memory block used for storing data to be stored.

Alternatively, the first controller may send the data to be stored using a plurality of data messages. The second controller may organize data received from the portal using the root data structure. As shown in fig. 10, the data packet may be specifically a PCIe write packet, where the first controller writes the data to be written into the second controller through a PCIe write operation. After the second controller receives the data message, the data can be organized into a root data structure, so that the management of the data is convenient.

In the embodiment of the invention, after receiving the data message, the second controller decodes the address of the data message and identifies the association identifier, identifies the entry and the root data structure according to the association identifier, allocates idle memory blocks for the data from the memory storage, saves the data to the allocated memory blocks, and attaches the memory blocks to the root data structure. The second controller first stores the data in its own internal memory, and when a predetermined condition is satisfied, stores the data stored in its own internal memory in a storage medium of the second storage device. The satisfaction condition herein may be that the second controller obtains the second write command, or that the data amount is accumulated to such an extent that the second NMVe controller can perform a write operation on the storage medium. The internal memory of the second controller may be a private memory of the controller.

The embodiment of the invention does not limit the sequence of the second controller for acquiring the data message and the second writing instruction, and the second controller can firstly receive the data message pushed by the first controller and determine the second writing instruction according to the association identifier. The second controller may acquire the second write instruction first, and then acquire the corresponding data to be stored according to the second write instruction. For example, the second controller may determine the association identifier according to the second write instruction, then determine the corresponding entry according to the association identifier, and obtain the stored payload data from the storage space allocated for the entry according to the association identifier.

The embodiment of the invention does not limit the order of the data to be stored corresponding to the second write instruction and the second write instruction itself reaching the second controller.

The second controller may maintain a one-to-one correspondence between the SQ slots and the entries, and after a second write instruction is obtained from one slot, the entry corresponding to the second write instruction may be determined according to the maintained correspondence. If the second controller detects that the corresponding entry has not arrived, the second controller suspends the second write command and waits for the arrival of data. And executing the writing operation of the data to be stored until the second controller detects that the corresponding entry has data.

If a part of data arrives at the second controller before the second write instruction, the second controller detects that the second write instruction corresponding to the data does not arrive at the second controller or the corresponding SQ slot according to the association identifier carried in the data message. The second controller may attach data to the root data structure waiting for the associated second write command to arrive until the corresponding second write command reaches the second controller or an SQ slot addressable by the second controller, the second controller obtaining the second write command and storing the data to be stored in the storage medium of the second storage device according to the second write command.

Step 709: the second controller stores the data to be stored in a storage medium of the second storage device.

In the embodiment of the invention, the first controller can send the data to be stored through a plurality of data messages, the second controller receives the data to be stored pushed by the first controller through the inlet, and the writing operation of the second controller to the storage medium of the second storage device can be executed in parallel. If the processing of the data to be stored currently received through the portal is completed, i.e. the data currently received through the portal has been completely written to the storage medium of the second storage device, but the system needs more data to complete the backup operation, the second controller suspends the second write command waiting for the arrival of data.

Step 710: the second controller triggers a completion message.

After the second controller completes the storage operation of the data to be stored, a completion message is triggered. The completion message is used for indicating the second controller to complete the storage operation of the data to be stored.

In an embodiment of the present invention, the completion message may be a trigger completion queue entry (completion queue entry, CQE) that indicates to the second controller to complete the write operation indicated by the second write instruction. The second controller triggering completion message may specifically be that after the second controller completes the write operation, a CQE is written into a Completion Queue (CQ), and the host is notified by an interrupt.

Fig. 11 is a schematic diagram illustrating a logic structure of a data backup device 1100 according to an embodiment of the invention. The data backup system includes a first storage device, which is a backup of the first storage device, a second storage device, which includes a first controller and a storage medium, and a data backup device 1100, which includes a second controller and a storage medium, as shown in fig. 11, the data backup device 1100 includes a processing unit 1101 and an acquisition unit 1102, wherein,

The processing unit 1101 is configured to trigger a first write instruction, where the first write instruction carries an association identifier, and the association identifier is used to associate the second write instruction with the data to be stored; the first write instruction is used for instructing the first controller to store data to be stored in a storage medium of the first storage device and instructing the first controller to send a data message to the second controller, wherein the data message comprises the data to be stored and an associated identifier. The processing unit 1101 is further configured to trigger a second write instruction, where the second write instruction is configured to instruct the second controller to store the data to be stored in the storage medium of the second storage device.

Optionally, the backup apparatus 1100 further includes an obtaining unit 1102, configured to obtain a completion message triggered by the second controller, where the completion message is used to instruct the second controller to complete a storage operation of the data to be stored.

Optionally, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the second controller.

Optionally, the association identifies a portion of a field containing the second write instruction.

Optionally, the first write instruction and/or the second write instruction is an NVMe-based SQE.

In an embodiment of the present application, the processing unit 1101 and the obtaining unit 1102 may be implemented by the backup logic 410 in the processor 401 in fig. 4, or by the backup module 406 in the processor 401 and the system memory 402 in fig. 4.

The embodiments of the present application are device embodiments of the host corresponding to the above embodiments, and the feature descriptions in the above embodiments are applicable to the embodiments of the present application, and are not repeated here.

Fig. 12 is a schematic diagram of a logic structure of a backup device 1200 according to an embodiment of the application. The data backup system includes a first storage device, a second storage device and a host, the second storage device is a backup of the first storage device, the first storage device includes a data backup device 1200 and a storage medium, and the second storage device includes a controller and a storage medium. As shown in fig. 12, the backup apparatus 1200 includes a processing unit 1201 and a transmitting unit 1202, wherein,

the processing unit 1201 is configured to obtain a first write instruction triggered by a host and data to be stored, where the first write instruction carries an association identifier, and the association identifier is configured to associate the data to be stored with a second write instruction, where the second write instruction is triggered by the host and is configured to instruct a controller to write the data to be stored into a storage medium of the second storage device, and store the data to be stored into the storage medium of the first storage device according to the first write instruction.

The sending unit 1202 is configured to send a data packet to the controller, where the data packet includes data to be stored and an association identifier.

Optionally, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the controller.

In an embodiment of the present application, processing unit 1201 and sending unit 1202 may be implemented by backup logic 505 in processor 501 in fig. 5 or by backup module 506 in processor 501 and system memory 502 in fig. 5.

The embodiment of the present application is an embodiment of the apparatus of the first controller corresponding to the above embodiment, and the feature descriptions in the above embodiment are applicable to the embodiment of the present application, and are not repeated herein.

Fig. 13 is a schematic diagram of a logic structure of a backup device 1300 according to an embodiment of the application. The data backup system includes a first storage device, a second storage device and a host, the second storage device is a backup of the first storage device, the first storage device includes a controller and a storage medium, and the second storage device includes a data backup device 1300 and a storage medium. As shown in fig. 13, the backup apparatus 1300 includes an acquisition unit 1301 and a processing unit 1302, wherein,

The obtaining unit 1301 is configured to obtain a write instruction triggered by the host, where the write instruction is configured to instruct the data backup device to write data to be stored in the storage medium of the second storage device, and receive a data packet sent by the controller, where the data packet includes the data to be stored and an association identifier, and the association identifier is used to associate the write instruction with the data to be stored.

The processing unit 1302 is configured to store data to be stored in a storage medium of the second storage device according to the write instruction.

Optionally, the data packet is a PCIe packet, and the association identifier includes a PCIe address field of the data backup device 1301.

Optionally, the data backup device 1300 further includes an internal memory, and before the processing unit 1302 stores the data to be stored in the storage medium of the second storage device, the processing unit is further configured to store the data to be stored in a storage space of the internal memory, and record a mapping relationship between the storage space and the association identifier.

Optionally, the acquiring unit 1301 is further configured to determine a storage location of the write instruction according to the association identifier, and acquire the write instruction according to the storage location of the write instruction.

Optionally, the association identifier includes a part field of the write instruction, and the acquiring unit 1301 is further configured to acquire the write instruction according to the part field of the write instruction.

Optionally, the processing unit 1302 is further configured to trigger a completion message, where the completion message is used to instruct the data backup device 1300 to complete the storage operation of the data to be stored.

Optionally, the write instruction is an NVMe-based SQE.

In an embodiment of the present application, the obtaining unit 1301 and the processing unit 1302 may be implemented by the backup logic 605 in the processor 601 in fig. 6, or by the backup module 606 in the processor 601 and the system memory 602 in fig. 6.

The embodiment of the present application is an embodiment of a device of a second controller corresponding to the above embodiment, and the feature descriptions in the above embodiment are applicable to the embodiment of the present application, and are not repeated herein.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced; such modifications and substitutions do not depart from the scope of the appended claims.

Claims

1. A data backup system, wherein the system comprises a first storage device, a second storage device and a host, wherein the second storage device is a backup of the first storage device, the first storage device comprises a first controller and a storage medium, and the second storage device comprises a second controller and a storage medium;

The host is used for triggering a first write instruction and a second write instruction, the first write instruction carries an association identifier, and the association identifier is used for associating data to be stored with the second write instruction;

the first controller is configured to obtain the first write instruction and the data to be stored, store the data to be stored in a storage medium of the first storage device according to the first write instruction, and send a data packet to the second controller, where the data packet includes the data to be stored and the association identifier; the first controller acquires data to be stored from a host side; the association identifies a partial field containing the entry address or the entry address; an entry is an address space where the second storage device is open to the first storage device;

the second controller is configured to obtain the second write instruction and the data packet, identify an entry address according to the data packet, allocate a corresponding storage space for an entry corresponding to the entry address in a local internal memory, and cache the data to be stored in the storage space according to the second write instruction;

the second controller is further configured to determine a storage location of the second write instruction according to the association identifier, and the second controller is configured to obtain the second write instruction according to the storage location of the second write instruction.

2. The system of claim 1, wherein the data message is a PCIe message and the association identification includes a PCIe address field of the second controller.

3. The system of claim 1, wherein the second controller comprises an internal memory, and wherein the second controller is further configured to store the data to be stored in a storage space of the internal memory and record a mapping relationship between the storage space and the association identifier before storing the data to be stored in the storage medium of the second storage device.

4. A system according to any of claims 1-3, wherein the association identifies a partial field containing the second write instruction, the second controller being configured to retrieve the second write instruction based on the partial field of the second write instruction.

5. A system according to any of claims 1-3, characterized in that the first write instruction and/or the second write instruction is a commit queue entry SQE based on a non-volatile high speed transport bus NVMe.

6. A method of data backup, the data backup system comprising a first storage device, a second storage device and a host, the second storage device being a backup of the first storage device, the first storage device comprising a first controller and a storage medium, the second storage device comprising a second controller and a storage medium, the method comprising:

The host triggers a first write instruction, wherein the first write instruction carries an association identifier, and the association identifier is used for associating a second write instruction with data to be stored; the first write instruction is used for instructing the first controller to store the data to be stored in a storage medium of the first storage device and instructing the first controller to send a data message to the second controller, wherein the data message comprises the data to be stored and the association identifier; the second controller acquires the second write instruction and the data message, identifies an entry address according to the data message, and allocates a corresponding storage space for an entry corresponding to the entry address in a local internal memory; the first controller acquires data to be stored from a host side; the association identifies a partial field containing the entry address or the entry address; an entry is an address space where the second storage device is open to the first storage device; the second controller is further configured to determine a storage location of the second write instruction according to the association identifier, and the second controller is configured to obtain the second write instruction according to the storage location of the second write instruction;

the host triggers a second write instruction, where the second write instruction is used to instruct the second controller to cache the data to be stored into the storage space.

7. The method of claim 6, wherein the first write instruction and/or the second write instruction is a commit queue entry SQE based on a non-volatile high speed transport bus NVMe.

8. The method of claim 6 or 7, wherein the data message is a PCIe message and the association identification includes a PCIe address field of the second controller.

9. The method of claim 6 or 7, wherein the association identifies a partial field containing the second write instruction.

10. A method of data backup, the data backup system comprising a first storage device, a second storage device and a host, the second storage device being a backup of the first storage device, the first storage device comprising a first controller and a storage medium, the second storage device comprising a second controller and a storage medium, the method comprising:

the first controller acquires a first write instruction triggered by the host and data to be stored, wherein the first write instruction carries an association identifier, the association identifier is used for associating the data to be stored with a second write instruction, and the second write instruction is triggered by the host and used for instructing the second controller to write the data to be stored into a storage medium of the second storage device; the first controller acquires data to be stored from a host side;

The first controller stores the data to be stored in a storage medium of the first storage device according to the first write instruction;

the first controller sends a data message to the second controller, wherein the data message comprises the data to be stored and the association identifier; the association identifies a partial field containing the entry address or the entry address; an entry is an address space where the second storage device is open to the first storage device;

11. The method of claim 10, wherein the data message is a PCIe message and the association identification includes a PCIe address field of the second controller.

12. The method of claim 10, wherein the association identifies a partial field containing the second write instruction.

13. A method of data backup, the data backup system comprising a first storage device, a second storage device and a host, the second storage device being a backup of the first storage device, the first storage device comprising a first controller and a storage medium, the second storage device comprising a second controller and a storage medium, the method comprising:

the second controller acquires a write instruction triggered by the host, wherein the write instruction is used for instructing the second controller to write data to be stored into a storage medium of the second storage device;

the second controller receives a data message sent by the first controller, wherein the data message comprises the data to be stored and an association identifier, and the association identifier is used for associating the write instruction and the data to be stored; the first controller acquires data to be stored from a host side; the association identifies a partial field containing the entry address or the entry address; an entry is an address space where the second storage device is open to the first storage device; the second controller identifies an entry address according to the data message, and allocates a corresponding storage space for an entry corresponding to the entry address in a local internal memory;

The second controller stores the data to be stored into the storage space according to the write instruction;

the second controller is further configured to determine a storage location of the write instruction according to the association identifier, and the second controller is configured to obtain the write instruction according to the storage location of the write instruction.

14. The method of claim 13, wherein the data message is a PCIe message and the association identification includes a PCIe address field of the second controller.

15. The method of claim 13, wherein the second controller comprises an internal memory, the method further comprising, prior to storing the data to be stored in the storage medium of the second storage device:

and the second controller stores the data to be stored into a storage space of the internal memory and records the mapping relation between the storage space and the association identifier.

16. The method of any of claims 13-15, wherein the association identifies a partial field containing the write instruction;

the second controller obtaining the write instruction includes: and the second controller acquires the write instruction according to a part of the field of the write instruction.

17. The method according to any of claims 13-15, wherein the write instruction is a commit queue entry SQE based on a non-volatile high speed transport bus NVMe.

18. A data backup device, wherein a data backup system includes a first storage device, a second storage device and the data backup device, the second storage device is a backup of the first storage device, the first storage device includes a first controller and a storage medium, the second storage device includes a second controller and a storage medium, the data backup device includes:

the processing unit is used for triggering a first write instruction, wherein the first write instruction carries an association identifier, and the association identifier is used for associating a second write instruction with data to be stored; the first write instruction is used for instructing the first controller to store the data to be stored in a storage medium of the first storage device and instructing the first controller to send a data message to the second controller, wherein the data message comprises the data to be stored and the association identifier; the first controller acquires data to be stored from a host side; the association identifies a partial field containing the entry address or the entry address; an entry is an address space where the second storage device is open to the first storage device; the second controller acquires the second write instruction and the data message, identifies an entry address according to the data message, and allocates a corresponding storage space for an entry corresponding to the entry address in a local internal memory;

The processing unit is further configured to trigger a second write instruction, where the second write instruction is used to instruct the second controller to store the data to be stored in a storage medium of the second storage device to cache the data to the storage space; and the second controller also determines the storage position of the second write instruction according to the association identifier, and acquires the second write instruction according to the storage position of the second write instruction.

19. The data backup device of claim 18, wherein the first write instruction and/or the second write instruction is a commit queue entry SQE based on a non-volatile high speed transport bus NVMe.

20. The data backup device of claim 18 or 19, wherein the data message is a PCIe message and the association identifier includes a PCIe address field of the second controller.

21. A data backup device as claimed in claim 18 or 19, wherein the association identifies a portion of a field containing the second write instruction.

22. A data backup device, wherein a data backup system comprises a first storage device, a second storage device and a host, the second storage device is a backup of the first storage device, the first storage device comprises the data backup device and a storage medium, the second storage device comprises a controller and a storage medium, and the data backup device comprises:

The processing unit is used for acquiring a first write instruction and data to be stored, which are triggered by the host, wherein the first write instruction carries an association identifier, the association identifier is used for associating the data to be stored with a second write instruction, the data to be stored is stored in a storage medium of the first storage device according to the first write instruction, and the second write instruction is triggered by the host and is used for instructing the controller to write the data to be stored in the storage medium of the second storage device; the processing unit acquires data to be stored from a host side;

the sending unit is used for sending a data message to the controller, wherein the data message comprises the data to be stored and the association identifier; the association identifies a partial field containing the entry address or the entry address; an entry is an address space where the second storage device is open to the first storage device; the controller is configured to obtain the second write instruction and the data packet, identify an entry address according to the data packet, allocate a corresponding storage space for an entry corresponding to the entry address in a local internal memory, and cache the data to be stored in the storage space according to the second write instruction;

The controller is further configured to determine a storage location of the second write instruction according to the association identifier, and the controller is configured to obtain the second write instruction according to the storage location of the second write instruction.

23. The data backup device of claim 22, wherein the data message is a PCIe message and the association identification includes a PCIe address field of the controller.

24. The data backup device of claim 22, wherein the association identifies a portion of a field containing the second write instruction.

25. A data backup device, wherein a data backup system includes a first storage device, a second storage device and a host, the second storage device is a backup of the first storage device, the first storage device includes a controller and a storage medium, the second storage device includes the data backup device and the storage medium, the data backup device includes:

the device comprises an acquisition unit, a controller and a storage unit, wherein the acquisition unit is used for acquiring a write instruction triggered by the host, receiving a data message sent by the controller, identifying an entry address according to the data message, and distributing a corresponding storage space for an entry corresponding to the entry address in a local internal memory, wherein the data message comprises data to be stored and an association identifier, the association identifier is used for associating the write instruction and the data to be stored, and the association identifier comprises the entry address or a part of fields of the entry address; an entry is an address space where the second storage device is open to the first storage device; the write instruction is used for instructing the data backup device to write the data to be stored into the storage medium of the second storage device; the controller acquires data to be stored from a host side;

The processing unit is used for caching the data to be stored into the storage space according to the write instruction;

the acquisition unit is also used for determining the storage position of the write instruction according to the association identifier and acquiring the write instruction according to the storage position of the write instruction.

26. The data backup device of claim 25, wherein the data message is a PCIe message and the association identification includes a PCIe address field of the data backup device.

27. The data backup device of claim 25, further comprising an internal memory, wherein the processing unit is further configured to store the data to be stored in a storage space of the internal memory before storing the data to be stored in the storage medium of the second storage device, and record a mapping relationship between the storage space and the association identifier.

28. The apparatus of any of claims 25-27, wherein the association identifies a partial field containing the write instruction;

the acquisition unit is further configured to acquire the write instruction according to a part of the field of the write instruction.

29. The apparatus of any one of claims 25-27, wherein the write instruction is a commit queue entry SQE based on a nonvolatile high speed transport bus NVMe.