CN109614249B - Method, device and computer readable storage medium for simulating multi-core communication - Google Patents
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Abstract
The embodiment of the invention discloses a method, a device and a computer readable storage medium for simulating multi-core communication, wherein a corresponding data structure is established for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto; recording the mapping relation between the input end and the output end in each data structure; when the first input end of the first data structure receives the IPC message, determining a first output end corresponding to the first input end according to the recorded mapping relation, and transmitting the IPC message to the first output end; according to the access address carried by the IPC message, the IPC message can be transmitted to the target input end of the second data structure through the first output end, so that communication among the multiple cores is realized. The principle of an IPC message mechanism is simulated by establishing a data structure for each kernel, so that the simulation of the solid state disk communication mechanism is realized, and the test of a firmware algorithm is facilitated.
Description
Technical Field
The present invention relates to the field of computer simulation technologies, and in particular, to a method and an apparatus for simulating multi-core communication, and a computer-readable storage medium.
Background
The simulation environment can perform simulation on each performance index of a Solid State Drive (SSD), and according to a simulation result, whether each performance of the SSD meets an index requirement can be quickly checked.
However, for the Communication mechanism between the internal modules of the Solid State Drives (SSD), an Inter-Process Communication (IPC) interaction mechanism is used. The IPC message network is the communication between a processor and a hardware and belongs to a mechanism set on a hardware level, and the simulation environment runs on windows, and the realization on the hardware cannot be seen, so that the IPC message network cannot be directly used in the simulation environment.
Therefore, how to implement the simulation of the solid state disk communication mechanism is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The embodiment of the invention aims to provide a method, a device and a computer readable storage medium for simulating multi-core communication, which can realize simulation of a solid state disk communication mechanism, thereby realizing the test of a firmware algorithm.
To solve the foregoing technical problem, an embodiment of the present invention provides a method for simulating multi-core communication, including:
establishing a corresponding data structure for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto;
recording the mapping relation between the input end and the output end in each data structure;
when a first input end of a first data structure receives an IPC message, determining a first output end corresponding to the first input end according to the mapping relation, and transmitting the IPC message to the first output end;
and transmitting the IPC message to a target input end of a second data structure through the first output end according to the access address carried by the IPC message so as to realize communication among multiple cores.
Optionally, after the transmitting the IPC message to the first output, the method further comprises:
setting the storage state of a target queue in the first input end for storing the IPC message to be invalid;
correspondingly, after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, the method further comprises:
and adjusting the storage state of the target queue to be effective.
Optionally, the adjusting the storage state of the target queue to be valid includes:
and after receiving a response message of the completed processing fed back by the target output end of the second data structure, adjusting the storage state of the target queue to be effective.
Optionally, before the transmitting the IPC message to a target input end of a second data structure through the first output end according to the access address carried by the IPC message, the method further includes:
establishing a thread lock for the first data structure;
correspondingly, after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, the method further comprises:
and releasing the thread lock.
The embodiment of the invention also provides a device for simulating multi-core communication, which comprises an establishing unit, a recording unit, a determining unit and a transmitting unit;
the establishing unit is used for establishing a corresponding data structure for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto;
the recording unit is used for recording the mapping relation between the input end and the output end in each data structure;
the determining unit is used for determining a first output end corresponding to the first input end according to the mapping relation when the first input end of the first data structure receives the IPC message, and transmitting the IPC message to the first output end;
and the transmission unit is used for transmitting the IPC message to a target input end of a second data structure through the first output end according to the access address carried by the IPC message so as to realize communication among multiple cores.
Optionally, the system further comprises a setting unit;
the setting unit is used for setting the storage state of a target queue used for storing the IPC message in the first input end to be invalid after the IPC message is transmitted to the first output end;
correspondingly, the setting unit is further configured to adjust the storage state of the target queue to be valid after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message.
Optionally, the setting unit is specifically configured to adjust the storage state of the target queue to be valid after receiving a response message that is fed back by the target output end of the second data structure and that is processed.
Optionally, the device further comprises a locking unit and a releasing unit;
the locking unit is used for establishing a thread lock for the first data structure before the IPC message is transmitted to a target input end of a second data structure through the first output end according to the access address carried by the IPC message;
correspondingly, the releasing unit is configured to release the thread lock after the IPC message is transmitted to a target input end of a second data structure through the first output end according to the access address carried by the IPC message.
The embodiment of the invention also provides a device for simulating multi-core communication, which comprises:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the method of simulating multi-core communication as described above.
An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for simulating multi-core communication are implemented as described above.
According to the technical scheme, a corresponding data structure is established for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto; recording the mapping relation between the input end and the output end in each data structure; according to the mapping relation, information transmission in each kernel can be realized, when the first input end of the first data structure receives the IPC message, the first output end corresponding to the first input end can be determined according to the recorded mapping relation, and the IPC message can be transmitted to the first output end; according to the access address carried by the IPC message, the IPC message can be transmitted to the target input end of the second data structure through the first output end, so that communication among the multiple cores is realized. In the technical scheme, the principle of the IPC message mechanism is simulated by establishing a data structure for each kernel, so that the IPC message mechanism can be simulated on a simulation platform, namely the simulation of the solid state disk communication mechanism is realized, and the test of a firmware algorithm is facilitated.
Drawings
In order to illustrate the embodiments of the present invention more clearly, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of a method for simulating multi-core communication according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an apparatus for simulating multi-core communication according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a hardware structure of a device for simulating multi-core communication according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Next, a method for simulating multi-core communication according to an embodiment of the present invention is described in detail. Fig. 1 is a flowchart of a method for simulating multi-core communication according to an embodiment of the present invention, where the method includes:
s101: and establishing a corresponding data structure for each core in advance.
In the embodiment of the invention, in order to realize the simulation of the communication mechanism of the solid state disk, the function required by the communication mechanism can be encapsulated to construct the data structure.
At least one input (inbound) and at least one output (outbound) may be included in each data structure.
The number of inbound and outbound can be determined according to the type of function involved in the communication mechanism.
S102: and recording the mapping relation between the input end and the output end in each data structure.
Each inbound has its corresponding message queue (message buffer) that can be used to store data information.
The number of the information queues corresponding to each inbound may be set according to actual requirements, which is not limited herein, for example, 8 information queues may be set for each inbound.
Similarly, for outbend, the corresponding information queue may also be set, and the number of the information queue corresponding to each outbend may be the same as the number of the information queue corresponding to each inbound.
In the embodiment of the invention, a manager can determine the mapping relationship between inbound and outbound in each kernel according to the specific project related to the simulation communication mechanism, and input the mapping relationship into the simulation platform in advance. The simulation platform records the mapping relation between the input end and the output end in each data structure, and can call the corresponding port according to the mapping relation when the communication between the multiple cores needs to be realized subsequently.
S103: when the first input end of the first data structure receives the IPC message, the first output end corresponding to the first input end is determined according to the mapping relation, and the IPC message is transmitted to the first output end.
In practical application, when communication between multiple cores needs to be simulated, IPC messages for accessing another core can be sent to a certain core, so that communication between the two cores is simulated.
In order to facilitate distinguishing the data structures of different cores, in the embodiment of the present invention, the data structure of the received IPC message may be referred to as a first data structure, and correspondingly, the data structure for processing the IPC message may be referred to as a second data structure.
The input of the first data structure for receiving the IPC message is called a first input, and the first output is an output having a mapping relation with the first input.
S104: and according to the access address carried by the IPC message, transmitting the IPC message to a target input end of a second data structure through a first output end so as to realize communication among the multiple cores.
In the embodiment of the present invention, each information queue has its corresponding access address, and the specific form of the access address may be represented by cpu id + qID + Message buffer _ index.
When communication among a plurality of cores is simulated and simulated, in order to distinguish the plurality of cores, a serial number is set for each core, and the cpu id is the serial number of the core.
Each kernel has a corresponding data structure, and the data structure includes an inbound port number and an outbound port number, and each port number may correspond to a plurality of information queues. Wherein qID is used to indicate the port number, and message _ buffer _ index is used to indicate the fourth information queue in the plurality of information queues.
According to the access address carried by the IPC Message, namely, cpu ID + qID + Message buffer _ index, the information queue to be accessed by the IPC Message can be uniquely determined.
It should be noted that, in the above description, the description is developed in terms of a communication process between the first data queue and the second data queue, and in practical applications, the communication between the multiple cores may be implemented by referring to a communication manner between the first data queue and the second data queue.
According to the technical scheme, a corresponding data structure is established for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto; recording the mapping relation between the input end and the output end in each data structure; according to the mapping relation, information transmission in each kernel can be realized, when the first input end of the first data structure receives the IPC message, the first output end corresponding to the first input end can be determined according to the recorded mapping relation, and the IPC message can be transmitted to the first output end; according to the access address carried by the IPC message, the IPC message can be transmitted to the target input end of the second data structure through the first output end, so that communication among the multiple cores is realized. In the technical scheme, the principle of the IPC message mechanism is simulated by establishing a data structure for each kernel, so that the IPC message mechanism can be simulated on a simulation platform, namely the simulation of the solid state disk communication mechanism is realized, and the test of a firmware algorithm is facilitated.
In order to achieve orderly management of the information queues, in the embodiment of the present invention, after the IPC message is transmitted to the first output end, the storage state of the target queue for storing the IPC message in the first input end may be set to be invalid.
When an IPC message is recorded in the target queue, a new IPC message is recorded in the target queue at this time, which causes message processing disorder. By setting the storage state of the target queue to be invalid, new IPC messages can be prevented from being written into the target queue, and the ordered management of the IPC messages is realized.
Correspondingly, after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, the target queue is released, and at the moment, the storage state of the target queue can be adjusted to be effective, so that the target queue can continue to provide services for other IPC messages.
In a specific implementation, the storage state of the target queue may be directly adjusted to be valid after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, or may be adjusted to be valid after a response message of completing the processing and fed back by the target output end of the second data structure is received, which is not limited to this.
In the embodiment of the invention, the ordered processing of the messages is effectively ensured by dynamically adjusting the storage state of the target queue, so that the correctness and the reliability of the simulation are ensured.
In the embodiment of the present invention, before the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, a thread lock may be established for the first data structure.
Accordingly, after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, the thread lock can be released.
By setting the thread lock, confusion caused when different kernels simultaneously access shared memory resources can be effectively avoided, and mutual influence among threads is reduced.
Fig. 2 is a schematic structural diagram of an apparatus for simulating multi-core communication according to an embodiment of the present invention, including an establishing unit 21, a recording unit 22, a determining unit 23, and a transmitting unit 24;
an establishing unit 21, configured to establish a corresponding data structure for each core in advance; wherein each data structure has at least one input and at least one output corresponding thereto;
the recording unit 22 is used for recording the mapping relation between the input end and the output end in each data structure;
a determining unit 23, configured to determine, when the first input end of the first data structure receives the IPC message, a first output end corresponding to the first input end according to the mapping relationship, and transmit the IPC message to the first output end;
and the transmission unit 24 is used for transmitting the IPC message to a target input end of the second data structure through the first output end according to the access address carried by the IPC message so as to realize communication among the multiple cores.
Optionally, the system further comprises a setting unit;
the setting unit is used for setting the storage state of a target queue used for storing the IPC message in the first input end to be invalid after the IPC message is transmitted to the first output end;
correspondingly, the setting unit is further configured to adjust the storage state of the target queue to be valid after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message.
Optionally, the setting unit is specifically configured to adjust the storage state of the target queue to be valid after receiving a response message that is fed back by the target output end of the second data structure and that is processed.
Optionally, the device further comprises a locking unit and a releasing unit;
the locking unit is used for establishing a thread lock for the first data structure before the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message;
correspondingly, the releasing unit is used for releasing the thread lock after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message.
The description of the features in the embodiment corresponding to fig. 2 may refer to the related description of the embodiment corresponding to fig. 1, and is not repeated here.
According to the technical scheme, a corresponding data structure is established for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto; recording the mapping relation between the input end and the output end in each data structure; according to the mapping relation, information transmission in each kernel can be realized, when the first input end of the first data structure receives the IPC message, the first output end corresponding to the first input end can be determined according to the recorded mapping relation, and the IPC message can be transmitted to the first output end; according to the access address carried by the IPC message, the IPC message can be transmitted to the target input end of the second data structure through the first output end, so that communication among the multiple cores is realized. In the technical scheme, the principle of the IPC message mechanism is simulated by establishing a data structure for each kernel, so that the IPC message mechanism can be simulated on a simulation platform, namely the simulation of the solid state disk communication mechanism is realized, and the test of a firmware algorithm is facilitated.
Fig. 3 is a schematic hardware structure diagram of a device 30 for simulating multi-core communication according to an embodiment of the present invention, including:
a memory 31 for storing a computer program;
a processor 32 for executing a computer program to implement the steps of the method of simulating multi-core communication as described above.
The embodiment of the invention also provides a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and when being executed by a processor, the computer program realizes the steps of the method for simulating multi-core communication.
The method, the apparatus, and the computer-readable storage medium for simulating multi-core communication according to the embodiments of the present invention are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Claims (8)
1. A method for simulating multi-core communication, comprising:
establishing a corresponding data structure for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto;
recording the mapping relation between the input end and the output end in each data structure;
when a first input end of a first data structure receives an IPC message, determining a first output end corresponding to the first input end according to the mapping relation, and transmitting the IPC message to the first output end;
according to the access address carried by the IPC message, the IPC message is transmitted to a target input end of a second data structure through the first output end, so that communication among multiple cores is realized;
after the transmitting the IPC message to the first output, further comprising:
setting the storage state of a target queue in the first input end for storing the IPC message to be invalid;
correspondingly, after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, the method further comprises:
and adjusting the storage state of the target queue to be effective.
2. The method of claim 1, wherein the adjusting the storage status of the target queue to valid comprises:
and after receiving a response message of the completed processing fed back by the target output end of the second data structure, adjusting the storage state of the target queue to be effective.
3. The method of any of claims 1-2, further comprising, prior to said transmitting the IPC message through the first output to a target input of a second data structure according to an access address carried by the IPC message:
establishing a thread lock for the first data structure;
correspondingly, after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message, the method further comprises:
and releasing the thread lock.
4. The device for simulating multi-core communication is characterized by comprising an establishing unit, a recording unit, a determining unit and a transmitting unit;
the establishing unit is used for establishing a corresponding data structure for each kernel in advance; wherein each data structure has at least one input and at least one output corresponding thereto;
the recording unit is used for recording the mapping relation between the input end and the output end in each data structure;
the determining unit is used for determining a first output end corresponding to the first input end according to the mapping relation when the first input end of the first data structure receives the IPC message, and transmitting the IPC message to the first output end;
the transmission unit is used for transmitting the IPC message to a target input end of a second data structure through the first output end according to the access address carried by the IPC message so as to realize communication among multiple cores;
also includes a setting unit;
the setting unit is used for setting the storage state of a target queue used for storing the IPC message in the first input end to be invalid after the IPC message is transmitted to the first output end;
correspondingly, the setting unit is further configured to adjust the storage state of the target queue to be valid after the IPC message is transmitted to the target input end of the second data structure through the first output end according to the access address carried by the IPC message.
5. The apparatus according to claim 4, wherein the setting unit is specifically configured to, after receiving a response message that the processing is completed and is fed back by the target output end of the second data structure, adjust the storage status of the target queue to be valid.
6. The apparatus according to any one of claims 4 to 5, further comprising a locking unit and a releasing unit;
the locking unit is used for establishing a thread lock for the first data structure before the IPC message is transmitted to a target input end of a second data structure through the first output end according to the access address carried by the IPC message;
correspondingly, the releasing unit is configured to release the thread lock after the IPC message is transmitted to a target input end of a second data structure through the first output end according to the access address carried by the IPC message.
7. An apparatus that simulates multi-core communication, comprising:
a memory for storing a computer program;
a processor for executing the computer program for implementing the steps of the method of simulating multi-core communication according to any of claims 1 to 3.
8. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method of simulating multi-core communication according to any one of claims 1 to 3.
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| CN102789399A (en) * | 2012-07-06 | 2012-11-21 | 苏州汉明科技有限公司 | Inter-process communication method of multi-core distribution system |
| TW201317897A (en) * | 2011-10-31 | 2013-05-01 | Univ Nat Taiwan | Task scheduling and allocation for multi-core/many-core management framework and method thereof |
| CN108900259A (en) * | 2018-06-21 | 2018-11-27 | 厦门大学 | A kind of online underwater sound communication test of heuristics device based on multi-core processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201317897A (en) * | 2011-10-31 | 2013-05-01 | Univ Nat Taiwan | Task scheduling and allocation for multi-core/many-core management framework and method thereof |
| CN102789399A (en) * | 2012-07-06 | 2012-11-21 | 苏州汉明科技有限公司 | Inter-process communication method of multi-core distribution system |
| CN108900259A (en) * | 2018-06-21 | 2018-11-27 | 厦门大学 | A kind of online underwater sound communication test of heuristics device based on multi-core processor |
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